CN102376687A - Semiconductor component packaging structure and manufacturing method thereof - Google Patents
Semiconductor component packaging structure and manufacturing method thereof Download PDFInfo
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- CN102376687A CN102376687A CN2011102310140A CN201110231014A CN102376687A CN 102376687 A CN102376687 A CN 102376687A CN 2011102310140 A CN2011102310140 A CN 2011102310140A CN 201110231014 A CN201110231014 A CN 201110231014A CN 102376687 A CN102376687 A CN 102376687A
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/24155—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
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- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The present invention relates to a semiconductor component packaging structure and a manufacturing method thereof. The semiconductor component packaging structure comprises a first substrate which is provided with a grain metal pad, a first conducting wire circuit and a second conducting wire circuit; grains which are arranged on the upper surface of the grain metal pad; a second substrate which is provided with a grain accommodating opening for accommodating the grains, a third conducting wire circuit and a forth conducting wire circuit, wherein the depth of the grains is equal to that of the second substrate; glue layers which are arranged on the upper surface of the first substrate and bottom surfaces of the second substrate and the grains; and first dielectric layers which are arranged on upper surfaces of the grains and the second substrate, and between sides walls of the grains and side walls of the grain accommodating openings, and each first dielectric layer comprises a plurality of hole areas. The semiconductor component packaging structure has excellent thermal expansion coefficient matching performance and downsizing size, the substrate is provided with the grain accommodating opening, thus the mechanical reliability can be improved and the size of components can be reduced.
Description
Technical field
The present invention relates to a kind of crystal grain flush type board structure that forms the encapsulation of panel form, particularly a kind of semiconductor component packaging structure and manufacturing approach thereof.
Background technology
Investment casting is commonly called lost wax process, and it is a kind of casting technique, can make metal or metal alloy can be made into nearly end form (near-net-shape) metal parts.Investment casting is generally used for forming in the technology of crisscross and complicated shape with high accuracy.Fire-resistant crucible is used for wrapping die cast technology, in order to the deposite metal alloy.In this viewpoint, alloy melting then injects a mould with the cast that is shaped from said crucible in a crucible.Traditional fire-resistant crucible, for example, the zirconia crucible, its part has loose structure usually, and is minimum to increase the ability of resisting thermal shock and the possibility of breaking is dropped to.
In the semiconductor element field, along with component size is constantly dwindled, component density also constantly improves.Technical need for encapsulation or inner online aspect also must improve, to meet above-mentioned situation.Traditionally, in covering brilliant method of attachment (flip-chip attachment method), a solder projection array is formed at the surface of above-mentioned crystal grain.The formation of above-mentioned solder projection can produce required solder projection pattern through pad shielding (solder mask) through using a soldering composite material (solder compositematerial).The function of Chip Packaging comprises power and transmits (power distribution), signal transmission (signal distribution), heat radiation (heat dissipation) and protection and support etc.When semiconductor variable more complicated; Traditional encapsulation technology; For example; Leaded package (lead frame package), contraction type encapsulation (flex package), rigid encapsulation technology (rigid package technique) can't satisfy the demand of on a littler chip, making high density components.
Moreover, because after traditional encapsulation technology is divided into little crystal grain with crystal grain big on the wafer, encapsulate respectively again.Therefore, these technological technologies are consuming time.So far the chip encapsulation technology development that is integrated circuit to heavens influences; So,, also produce demand to encapsulation technology along with the demand of circuit size.According to above-mentioned reason, Development of Packaging Technology trend is towards ball grid array, covers crystalline substance, chip size packages and wafer-level packaging now." wafer-level packaging " is exactly that whole encapsulation is online the same with other technology with all inside as literal explanation, all is before wafer is cutting into little crystal grain, to be done.In general, after accomplishing all assemblings and canned program, individual other semiconductor packages will be divided into most semiconductor grains from a wafer.This wafer-level packaging is very small dimensions and extremely excellent electrical combining.
On complete wafer, make and test through crystal grain, the wafer-level packaging technology is a kind of advanced person's a encapsulation technology.Afterwards, above-mentioned wafer is cut into crystal grain, to inlay line (surface-mount line) assembling according to the surface.Because above-mentioned wafer-level packaging technology is utilized the full wafer wafer as an object, but not utilizes a chip or crystal grain, therefore carrying out cutting process (scribing process) before, just accomplished packaging and testing.In addition, because wafer-level packaging is so advanced technology, so can omit routing (wirebonding), sticking brilliant (die mount) covers the technology that glue (molding) and/or primer are filled (under-fill).Through using the wafer-level packaging technology, can save cost and process time; And crystal grain is the same therewith for this technological final structure; Therefore, this technology can satisfy the demand of electronic component miniaturization.
Though the wafer-level packaging technology has above-mentioned advantage, still there are some problems, but influence the acceptance of this technology.For example, in the wafer-level packaging technology, the hot coefficient of dilatation difference of this two storeroom of a material and motherboard in its structure; This person becomes the key factor of construction machine property unstable (mechanical instability).Total terminal array number of said structure is limited by the chip size.Before this wafer of cutting, can't use multicore sheet and system in package in the encapsulation of full wafer wafer.The 6th, 239,482B1 United States Patent (USP) (Figure 15) announcement one has the encapsulation of mechanicalness buckling problem.This is because aforementioned prior art is embedded in aforesaid substrate 18 or nucleus with silicon 12, and only supports above-mentioned crystal grain 12 with sticky material 20.As everyone knows; In the process of mechanicalness crooked (mechanical bending); Because the hardness (hardness) of silicon crystal grain and baseplate material 18 and sticky material 20 is all different with material character; This curvature effect (bending effect) will cause material boundary to break, and rerouting layer metal wire 32 damaged, and therefore reliability test (reliability test) also lost efficacy aspect mechanical stress.In addition, because dielectric layer too thick (dielectric layer 22 with dielectric layer 16), and the hot coefficient of dilatation between dielectric layer 22, dielectric layer 16, metal 30 and the material 20 etc. do not match, and causes not good reliability and rate of finished products yet.United States Patent (USP) the 6th, 506, the encapsulation that 632B1 United States Patent (USP) (Figure 16) discloses also produces same mechanism's problem.
In addition, above-mentioned prior art needs complicated technology when forming the encapsulation of panel form.The glue instrument that covers (mold tool) that above-mentioned arts demand is used to encapsulate, and inject encapsulating material or inject the point gum machine (dispenser) of above-mentioned sticky material.Because potting compound or epoxy resin (epoxy) be the meeting warpage after hot curing, crystal grain is difficult to be controlled at identical horizontal plane with the surface of above-claimed cpd, thus need chemical mechanical milling tech to grind this uneven surface, so therefore cost also improves.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of semiconductor component packaging structure, to carry out preferable motherboard level reliability test, for example bending, vibration-testing etc.
In order to achieve the above object, the present invention provides a kind of semiconductor component packaging structure, and said semiconductor component packaging structure comprises:
One first substrate, it has second wire circuit that first wire circuit and that a crystal grain metal gasket, is positioned at said first upper surface of base plate is positioned at said first substrate base surface, and wherein said crystal grain metal gasket comprises an alignment mark;
One crystal grain, it is disposed at the upper surface of said crystal grain metal gasket;
One second substrate; The privates circuit and one that its die receiving opening, one with a confession die receiving is positioned at said second upper surface of base plate is positioned at the privates circuit on said second substrate base surface, and the thickness of wherein said crystal grain equals the thickness of said second substrate;
One adhesion coating, it is arranged at the basal surface of the upper surface of said first substrate, said second substrate and said crystal grain; And
One first dielectric layer, it is arranged at the upper surface of said crystal grain and said second substrate, and is arranged between the sidewall of sidewall and said die receiving opening of said crystal grain, and wherein said first dielectric layer comprises most holes zones.
Preferred version as above-mentioned a kind of semiconductor component packaging structure; Wherein said semiconductor component packaging structure also comprises most conduction perforation; It runs through first substrate and second substrate, and connects first wire circuit, second wire circuit, privates circuit and privates circuit.
Preferred version as above-mentioned a kind of semiconductor component packaging structure; Wherein said semiconductor component packaging structure also comprises the rerouting layer that is positioned on most the hole zones and first dielectric layer; And the connection gasket and the privates circuit of coupling crystal grain, and further be coupled to through the conduction between first substrate and second substrate and bore a hole through the 3rd conducting wire.
Preferred version as above-mentioned a kind of semiconductor component packaging structure; Wherein said semiconductor component packaging structure also comprises second dielectric layer that is formed on first dielectric layer and the rerouting layer, and second dielectric layer has can make the projection underlying metal be formed at wherein and connect the opening of rerouting layer.
As the preferred version of above-mentioned a kind of semiconductor component packaging structure, wherein said semiconductor component packaging structure also is contained in the conduction perforation that runs through first substrate, and it connects the crystal grain metal gasket and second wire circuit.
In addition, the present invention also provides a kind of manufacturing approach of semiconductor component packaging structure, and the manufacturing approach of said semiconductor component packaging structure comprises the following step:
Prepare one first substrate and one second substrate, wherein said first substrate comprises a crystal grain metal gasket, has an alignment mark on the crystal grain metal gasket;
Utilize laser or process for stamping to form a die receiving opening through said second substrate;
Prepare a sticky material;
Utilize said sticky material that said first substrate is adhered on said second substrate;
Utilize alignment mark one crystal grain of crystal grain metal gasket, and utilize said sticky material that crystal grain is adhered on the crystal grain metal gasket;
Form one first dielectric layer in the upper surface of second substrate and crystal grain, and first dielectric layer is pushed into the gap between said crystal grain sidewall and the said die receiving opening sidewalls;
Form most hole zones in first dielectric layer; And
Form a rerouting layer in most hole zones and on first dielectric layer.
As the preferred version of the manufacturing approach of above-mentioned a kind of semiconductor component packaging structure, the manufacturing approach of wherein said semiconductor component packaging structure also comprises and forms one second dielectric layer on first dielectric layer and rerouting layer.
As the preferred version of the manufacturing approach of above-mentioned a kind of semiconductor component packaging structure, the manufacturing approach of wherein said semiconductor component packaging structure also comprises the conduction perforation of formation through first and second substrate.
As the preferred version of the manufacturing approach of above-mentioned a kind of semiconductor component packaging structure, wherein said first substrate utilizes sticky material to be adhered to second substrate under vacuum state.
As the preferred version of the manufacturing approach of above-mentioned a kind of semiconductor component packaging structure, wherein said first dielectric layer is urged the gap between crystal grain sidewall and the die receiving opening sidewalls under vacuum state.
The present invention has following beneficial effect:
Semiconductor component packaging structure provided by the present invention, it has splendid hot coefficient of dilatation matching performance and downsizing size; Its substrate has the die receiving opening, to improve mechanical reliability and to dwindle size of component;
The manufacturing approach of semiconductor component packaging structure provided by the present invention is redistributed the spacing of connection gasket and the size of conduction connecting line, thereby can be improved heat dissipation capability through the rerouting layer; Can form panel-type structure easily, and easily control panel coarse (smooth) degree; The thickness of control basal plate easily, but also can get rid of the problem of crystal grain displacement; The ejection formation instrument can be omitted, also chemical mechanical milling tech must be do not imported; Can not produce warpage yet; Through panel form packaging technology, the above-mentioned coupling that increases a layer beneath material (motherboard and substrate) thermal coefficient of expansion can make has preferable reliability; Can increase encapsulation productivity ratio, reduce the manufacturing cycle.
Description of drawings
Fig. 1 is according to embodiments of the invention, illustrates the sectional view of a undressed board structure;
Fig. 2 is according to embodiments of the invention, and diagram one has the sectional view of the substrate of die receiving opening;
Fig. 3 is according to embodiments of the invention, illustrates the sectional view that a crystal grain is redistributed instrument, and the upper surface of instrument has aligned pattern and temporary transient glue;
Fig. 4 is according to embodiments of the invention, and diagram one has second substrate of die receiving opening, the sectional view that itself and instrument are connected;
Fig. 5 is according to embodiments of the invention, and diagram one has the die receiving opening and second substrate that is connected with instrument and the sectional view of a crystal grain;
Fig. 6 is according to embodiments of the invention, and the diagram adhesive material is packed into the sectional view of panel type substrate;
Fig. 7 is according to embodiments of the invention, illustrates the sectional view that first substrate is connected with the adhesive material vacuum;
Fig. 7 A is according to embodiments of the invention, the sectional view that graphic panel type substrate and instrument separate;
Fig. 8 is according to embodiments of the invention, illustrates the panel type substrate of a crystal grain flush type;
Fig. 9 is according to embodiments of the invention, and diagram is positioned at the vertical view of the undressed wafer in the lead-type encapsulation;
Figure 10 is according to embodiments of the invention, illustrates the vertical view that a crystal grain flush type side increases laminar substrate;
Figure 11 is according to embodiments of the invention, and diagram is cut into sub-panel type substrate to weld the vertical view with the panel type substrate of final test;
Figure 12 is according to embodiments of the invention, the sectional view of system shown class encapsulation structure;
Figure 13 is according to embodiments of the invention, and the diagram metal covering is attached to the sectional view on system-in-package structure surface;
Figure 14 is according to embodiments of the invention, illustrates the sectional view of a board structure;
Figure 15 is one of sectional view of diagram one prior art;
Figure 16 for the diagram one prior art sectional view two;
Figure 17 is according to embodiments of the invention, illustrates the sectional view of a crystal grain flush type substrate, and its dual side build-up layers is positioned at upper surface and basal surface with the form of ball grid array;
Figure 18 is according to embodiments of the invention, illustrates the cross-sectional view of the system-in-package structure of a ball grid array form;
Figure 19 is according to embodiments of the invention, illustrates the sectional view of the polycrystalline encapsulating structure of a nesting structural embedded control;
Figure 20 illustrates the cross-sectional view of semiconductor element encapsulating structure for according to another embodiment of the present invention;
Figure 21 is for according to another embodiment of the present invention, one of flow chart of the manufacturing approach of diagram semiconductor element encapsulating structure;
Figure 22 is for according to another embodiment of the present invention, diagram form the semiconductor element encapsulating structure manufacturing approach flow chart two;
Figure 23 is for according to another embodiment of the present invention, diagram form the semiconductor element encapsulating structure manufacturing approach flow chart three;
Figure 24 is for according to another embodiment of the present invention, diagram form the semiconductor element encapsulating structure manufacturing approach flow chart four;
Figure 25 is for according to another embodiment of the present invention, diagram form the semiconductor element encapsulating structure manufacturing approach flow chart five;
Figure 26 is for according to another embodiment of the present invention, diagram form the semiconductor element encapsulating structure manufacturing approach flow chart six;
Figure 27 is for according to another embodiment of the present invention, diagram form the semiconductor element encapsulating structure manufacturing approach flow chart seven;
Figure 28 is the embodiment according to diffused ball grid array formula of the present invention, the cross-sectional view of icon semiconductor element encapsulating structure;
Figure 29 is according to one embodiment of the invention, the cross-sectional view of icon semiconductor element encapsulating structure.
[main element symbol description]
100-first substrate; The 101-wire pattern; 101a-crystal grain metal gasket; The 102-wire pattern; 103-conducts electricity perforation; 104-second substrate; The 105-wire pattern; The 106-wire pattern; 107-die receiving opening; The 110-instrument; The 111-alignment mark; The temporary transient pattern glue of 112-; 120-crystal grain/chip; 121-aluminium pad; 122-sticky material/stress-buffering material; 130-thickness; The slim mechanical bit of 140-; The 150-framework; 151-crystal grain; The blue glued membrane of 152-; 153-setting-out groove; 159-conducts electricity perforation; The 16-dielectric layer; 160-hole/kind of brilliant metal level; 161-first dielectric layer; 162-rerouting layer metal wire; 163-second dielectric layer; 164-metal coupling base; 165-weld metal pad; The 170-panel; The 171-sub-panel; The 18-baseplate material; The 180-pad; 181-crystal grain; 182-electric capacity; 183-resistance; The 184-metal covering;
The 20-sticky material; Substrate-200; Crystal grain-201; 202-second substrate; 203-first substrate; 204-sticky material/stress-buffer layer; The 22-dielectric layer;
The 30-metal; 32-rerouting layer;
The 400-dielectric layer; The 401-hole; 402-rerouting layer; The 403-dielectric layer; 404-hole/metal coupling base; The 405-solder sphere;
600-crystal grain; 601-sticky material/stress-buffer layer; 603-aluminium matter wiring pad; The 604-hole; 605-rerouting layer; The 606-dielectric material; The 607-dielectric layer; 620-core colloid;
700-first substrate; The 701-wire circuit; 701a-crystal grain metal gasket; The 702-wire circuit; 703-connects the conduction perforation; 704-second substrate; The 705-wire circuit; The 706-wire circuit; 707-die receiving opening; 720-crystal grain; The 721-connection gasket; The 722-sticky material; 723-first dielectric layer; 759-conducts electricity perforation; 760-hole zone; 761-rerouting layer; 762-second dielectric layer; The 780-soldered ball; The 790-reflector; Luminescent material-791.
Embodiment
The present invention will describe with preferred embodiment and accompanying drawing.Yet must know to be that these are with reference to the usefulness that only supplies diagram with inventive embodiments.Except the preferred embodiment of mentioning here, the present invention also can extensively be rendered among other embodiment.
The present invention discloses crystal grain or multicore sheet flush type board structure; Aforesaid substrate has the construction layer (dual built up layers) that is covered in two side surfaces.Figure 12 is the sectional view of diagram one system in package (system in package) structure; Aforesaid substrate has crystal grain embedded structure, bilateral layer (double side build uplayers), passive device, wafer level chip scale package structure (the wafer level chip scale package of increasing; WL-CSP), chip scale package structure (chip scale package; CSP), ball grid array (ball gridarray, BGA) and cover crystalline substance (flip-chip) etc.The content according to the present invention, surface are inlayed and are positioned at top and increase layer, and the terminal pin is positioned at offside.Above-mentioned encapsulating structure comprise one have crystal grain metal gasket 101a (be beneficial to conduct heat) first substrate, 100, one wire patterns 101 be positioned at the upper surface of first substrate 100, and another wire pattern 102 is positioned at the basal surface of first substrate 100.One connects conduction perforation 103 formation connects wire pattern 101 and wire pattern 102 to pass first substrate 100, and this disposes as the ground connection or the usefulness of radiator (heat sink).The back side of one crystal grain/chip 120 has sticky material 122, whereby with first substrate 100 on crystal grain metal gasket 101a adhere to.Above-mentioned crystal grain 120 has aluminium pad 121 (output/input pad) on it.Crystal grain 120 is disposed at the die receiving opening of second substrate 104, and adheres to sticky material 122.One second substrate 104 is positioned on first substrate 100, and wherein a die receiving opening and a wire pattern 105 are positioned at the upper surface of second substrate 104, and another wire pattern 106 then is positioned at the basal surface of above-mentioned second substrate 104.Above-mentioned sticky material (stress-buffering material) 122 is received in the gap between crystal grain 120 back sides and first substrate, 100 upper surfaces; And the gap between the sidewall of crystal grain 120 sidewalls and die receiving opening; And the dorsal part of second substrate 104.In the basal surface printing of crystal grain 120, film or jet flow sticky material 122, whereby with crystal grain 120 sealings.In one embodiment, sticky material 122 is covered in upper surface, surface, the hole of second substrate 104 and the below that increase layer of crystal grain 120 except aluminium pad 121 zones of second substrate 104.Through sticky material 122, the surface water plane of the surface water plane of crystal grain 120 and second substrate 104 is at same horizontal plane.One conduction perforation 159 is through first substrate 100 and second substrate 104, with the lead 105 that connects second substrate, 104 upper surfaces and basal surface and the lead 101 and the lead 102 of lead 106 and first substrate, 100 upper surfaces and basal surface.In one embodiment, above-mentioned conduction perforation 159 connects the basal surface lead 102 of above-mentioned crystal grain pad 101a and above-mentioned first substrate 100, and this configuration is as the usefulness of ground connection and heat radiation.One first dielectric layer 161 is formed on the crystal grain 120 and second substrate 104, and has a hole zone and make that hole 160 can be formed thereon.To obtain preferable reliability is consideration, and first dielectric layer 161 is Bao Yuehao more.One rerouting layer 162 is formed on the hole 160 and first dielectric layer 161, to be coupled with hole 160.First increases layer is formed at the top of crystal grain 120 circuit side and the top on second substrate, 104 surfaces.One second dielectric layer 163 is formed on first dielectric layer 161 and the rerouting layer plain conductor 162, and second dielectric layer 163 has the hole zone and makes metal coupling base 164 be formed in it.Second increases layer can be formed at the bottom side of first substrate 100 or attach and be placed on first and increase on the layer.This representes that the 3rd dielectric layer 400 is formed on the wire circuit on first substrate base surface, and the 3rd dielectric layer has the hole zone and makes that the rerouting layer is formed thereon.Weld metal pad 165 is formed on the metal coupling base 164.Soldering paste (solder paste) or pad 180 are formed on the weld metal pad 165.Most chip scale package structures, wafer level chip scale package structure, ball grid array, cover crystalline substance and passive device 181, passive device 182, passive device 183 is welded on the metal gasket through soldered ball (solder ball) 180; Above-mentioned metal gasket is the metal coupling base that increases the circuit side (opposite side of terminal metal pad) of layer.
The material of first substrate 100 and second substrate 104 is good with organic substrate (for example) epoxy resin (refractory glass fibre plate (FR5), BMI triazine resin (BT)) and printed circuit board (PCB).The thermal coefficient of expansion of first substrate 100 and second substrate 104 is the same with motherboard (printed circuit board (PCB)) to be good.Above-mentioned organic substrate is good with the epoxy resin (refractory glass fibre plate, BMI triazine resin) with high glass transition temperature (Tg), and above-mentioned material can form in circuit pattern and the inner online perforation easily.The thermal coefficient of expansion of metallic copper is approximately 16, also can be applicable among first and second baseplate material.And glass, pottery and silicon also can be used to be used as substrate.Above-mentioned sticky material 122 is good with silicone rubber based elastomeric material.
The thermal coefficient of expansion of organic substrate of above-mentioned epoxy resin (refractory glass fibre plate, BMI triazine resin) is about 14～17 in the X/Y direction; Be about 30～60 in the Z direction, therefore can select the thermal coefficient of expansion crystal grain redistribution instrument close with aforesaid substrate; So can reduce the crystal grain displacement problem of sticky material in the temperature-curable process.As if if the hot stage of temperature cycles is near glass transition temperature, above-mentioned refractory glass fibre plate/BMI triazine resin can't be got back to original position after temperature cycles.In the technology of panel form encapsulation, need use several high-temperature technologies, for example, the temperature-curable technology of dielectric material and sticky material etc.; If the thermal coefficient of expansion of materials used does not match, then can cause the crystal grain displacement in the panel-form.
Above-mentioned first and second substrate can be circle, for example, wafer form, its diameter can be 200 millimeters, 300 millimeters or higher.Above-mentioned first and second substrate also can be a rectangle, for example, and the form of panel.Size when its size is preferably substrate/flexible circuit board (flexible printed circuit) technology is made board because so can fully use aforesaid substrate/flexible circuit board, also can reduce unit cost simultaneously.
In one embodiment of this invention, first dielectric layer 161 and second dielectric layer 163 are good with the elastomeric dielectric material, and the elastomeric dielectric material is the silicone rubber based dielectric material that siloxane polymer, dow corning w15000 series and combination thereof are constituted.In another embodiment, first dielectric layer 161 and second dielectric layer 163 are made up of polyimides (polyimides) or silica gel base resin (silicone based resin).First dielectric layer 161 and second dielectric layer 163 are good with the formed photosensitive layer of simple process.
In one embodiment of this invention, the elastomeric dielectric layer be its thermal coefficient of expansion of a kind of material greater than 100 (ppm/ ℃), elongation is approximately 40% (between 30% to 50% for good), and hardness circle of above-mentioned material is between plastics and rubber.The thickness of above-mentioned elastomeric dielectric layer accumulates on the stress of rerouting layer/dielectric interface when looking closely temperature cycling test and decides.
In one embodiment of this invention, above-mentioned rerouting layer material comprises titanium/copper/billon or titanium/copper/nickel/billon, and the thickness of rerouting layer is the scope (if needs are arranged, can increase thickness to 25 micron) between 2 microns to 15 microns.The Ti/Cu alloy utilizes sputter (sputtering) technology to form, and can be used as kind of a brilliant metal level; Cu/Au alloy or Cu/Ni/Au alloy then are to utilize electroplating technology to form.Use electroplating technology to form the rerouting layer and can make it have enough thickness and preferable engineering properties, do not match with the thermal expansion coefficient of opposing in temperature cycles and mechanical bent process.Above-mentioned metal gasket can be metallic aluminium or metallic copper or its combination.
Formation has the technology of flush type crystal grain board structure in the content of the present invention, comprises: prepare one first substrate 100 and one second substrate 104 (raw material with glass mat (FR4)/refractory glass fibre plate (FR5)/BMI triazine resin (BT) is good); And be used for being used as the wire circuit pattern, be formed at wire pattern 101, the wire pattern 102 of the last and basal surface of first substrate 100 respectively; And be used for being used as wire circuit, and form wire pattern 105, the wire pattern 106 of the last and basal surface of second substrate 104 respectively, as shown in Figure 1.The crystal grain metal gasket 101a of wire pattern 101, wire pattern 102, wire pattern 105, wire pattern 106 and substrate can form with the method for electro-coppering/nickel/golden structure.Above-mentioned binding conduction perforation 103 can form to run through first substrate 100, connects crystal grain metal gasket 101a and wire pattern 102, is beneficial to ground connection and radiator (it can be made in the process of making substrate in advance).Die receiving opening 107 utilize laser cutting or mechanical press's (polycrystalline grain punch press) manufacture for every limit be a bit larger tham grain size add about 100 microns to 200 microns, as shown in Figure 2.The degree of depth and the die thickness of above-mentioned opening close (or thickness is about 25 microns).
Next step is for providing an instrument 110, for crystal grain/substrate is done the location and is aimed at, its have alignment mark 111 (being positioned on the single crystal grain) and temporarily pattern glue 112 be formed at the upper surface of instrument 110, as shown in Figure 3.The alignment mark 111 of above-mentioned instrument 110 comprises aiming at the mark of the single die alignment mark and second substrate 104.Temporary transient pattern glue 112 is good with the metal hole that is covered in aluminium pad and substrate, but its need balanced design to keep crystal grain in a smooth level.Temporary transient pattern glue 112 is printed (or some glue) surface with the adhesion crystal grain and second substrate on instrument 110.Temporary transient pattern glue has pattern with the aluminium welding pad 121 that adheres to crystal grain 120 and the wire pattern 105 of second substrate 104.
Afterwards, technology of the present invention comprises the aiming at and adhere to of temporary transient pattern glue 112 of second substrate 104 and instrument 110, and for example, wire pattern 105 can adhere to through aiming at temporary transient pattern glue 112, and is as shown in Figure 4.Next, crystal grain prepares according to following step, comprises brilliant back-grinding to desired thickness, for example is 127 or 200 microns; See through blue glued membrane 152 (blue tape) wafer is attached on the framework 150, along line of cut 153 crystal grain on the framework 150 151 is cut again, with the mode of reflection (mapping) wafer is distinguished at last, as shown in Figure 9.Crystal grain 120 with crystal grain pad 121 is aimed at (through alignment mark 111) and is attached on the temporary transient pattern glue 112 of its instrument 110 that faces down; Wherein little alignment system selected and places by crystal grain through use, aimed at and is placed on the instrument; Above-mentioned selecting with little alignment system has the function of covering crystalline substance, can the spacing of crystal grain with expectation be reassigned on the instrument, and be as shown in Figure 5.Above-mentioned temporary transient pattern glue 112 adheres to the interior crystal grain 120 (in the active surface side) of second substrate, 104 die receiving openings on instrument 110.Next, print a sticky material (packing material) 122, for example, the bottom side of printing elastic core colloidal materials (elastic core paste material) to the dorsal part and second substrate of crystal grain 120.Above-mentioned packing material 122 is filled in the space (gap) between the crystal grain 120, is covered in the bottom side of crystal grain 120 dorsal parts and second substrate, and is as shown in Figure 6.Sticky material 122 is good with the surface that can cover wire pattern 105.Next, first substrate, 100 vacuum are attached to sticky material 122, and are as shown in Figure 7.Curing process utilizes ultraviolet ray or thermal curing method, sticky material 122 is solidified, to connect first substrate 100.Panel welding (Bonding) machine is to be used for first substrate 100 is soldered to the dorsal part of second substrate 104 and crystal grain 120, to form parts.The thickness 130 of above-mentioned parts can Be Controlled.After accomplishing vacuum welding, then remove temporary transient pattern glue 112, again with instrument 100 from above-mentioned parts separately, to form display panel substrate (having built-in type crystal grain 120, first substrate 100, second substrate and sticky material 122), as shown in Figure 8.Above-mentioned display panel substrate separation method comprises and is positioned on the heating plate above-mentioned object or in the baking box; When the temperature of baking box during on 100 ℃; Above-mentioned temporary transient pattern glue 112 can become soft and the forfeiture adherence; Apply the edge of an external force then, use a slim mechanical bit 140 that the temporary transient pattern glue 112 of display panel substrate same edge is struck off simultaneously in above-mentioned display panel substrate; Therefore display panel substrate and instrument were opened in 110 minutes, shown in Fig. 7 A.In addition, can use solvent to remove display panel substrate, to remove temporary transient pattern glue residue.In one embodiment, the material of temporary transient pattern glue comprises polydimethylsiloxaneresins resins (polydimethy-siloxane g micron) and pitch dispersant (resin dispersion).
Above-mentioned display panel substrate and instrument carried out a cleaning procedure after opening in 110 minutes; Clean the surface of crystal grain through applying a wet type and/or dry type (electricity slurry).After above-mentioned display panel substrate formed, ensuing technology is the upper surface formation layer reinforced structure at the crystal grain and second substrate 104, and was shown in figure 10.Also can take another kind of the selection, form layer reinforced structure in the bottom side of first substrate 100; Can when utilizing substrate/flexible circuit board technology, form upper strata and bottom layer reinforced structure.The first step that forms layer reinforced structure is for utilizing the mode of rotation/spraying, films or forms one first dielectric layer in circuit side.So first dielectric layer 161 is formed at the top of the crystal grain 120 and second substrate 104; First dielectric layer 161 has hole 160 and is formed at wherein; Utilize the lithography process of exposure, development, curing schedule can expose aluminium connection gasket 121 (crystal grain I/o pad) and wire pattern 105 (substrate I/o pad); In certain embodiments, need etch process.Carry out electricity subsequently and starch the surface that cleaning cleans hole and aluminium pad.Next (computernumerical control, CNC) boring or laser drill form perforation between the wire pattern 106 under 105 to first substrates 100 of the wire pattern on second substrate 104 to carry out computer numerical control; Follow the filled conductive material, for example copper (Cu) is in above-mentioned perforation, to form conduction perforation 159.Above-mentioned conduction perforation 159 is for forming with the up and down wire circuit that connects second substrate 104 and the up and down wire circuit of first substrate 100.Next step again with titanium/copper as seed metal layer 160 sputters on first dielectric layer 161, hole and perforation.Afterwards, on first dielectric layer 161 and the brilliant metal level 160 of kind, be coated with photoresistance (can use photopolymer layer), then again photoresistance made public, develops, to form the pattern of rerouting metal level.Then, carry out electroplating technology again to form the rerouting layer metal of copper/gold or copper/nickel/gold.At last, utilize and to divest above-mentioned photoresistance and wet etch method forms rerouting layer metal wire 162 on kind of brilliant metal level 160.Generally speaking, the construction simultaneously of above-mentioned technology goes out above-mentioned conduction perforation 159 and rerouting layer.
Then, be with one second dielectric layer film, printing or press mold be on said first dielectric layer 161 and rerouting layer metal wire 162.Therefore said second dielectric layer 163 is formed on first dielectric layer 161 and the rerouting layer metal wire 162, and wherein has metal coupling base hole.Utilize the lithography process of exposure, development, curing schedule can expose rerouting layer metal wire 162, need etch process in certain embodiments.Next step again with titanium/copper (0.05/0.3 micron) as planting brilliant metal level sputter on the hole of second dielectric layer 163 and metal coupling base 164.Then, be coated with photoresistance (dry film is pressed layer) with planting brilliant metal level, then more above-mentioned photoresistance made public, develops to form the pattern of weld metal pad 165 at second dielectric layer 163.Then, carry out electroplating technology again, to go up the weld metal pad 165 that forms copper/nickel/gold (3/3/0.2 micron) at kind of a brilliant metal level (planting brilliant metal level).At last, divest above-mentioned photoresistance again, clean weld metal pad 165 with the metal wet etch method.Can repeat above-mentioned kind crystal layer, photoresistance and plating or divest/etch process, form multilayer rerouting layer and dielectric layer with single face and/or two sides at display panel substrate.
Afterwards, can become sub-panel form substrate to carry out final test panel form substrate cut.For example, the panel 170 that 0.51m is big or small cuts into the sub-panel 171 of four 0.255m sizes, and is shown in figure 11.Next, solder sphere implantation or pad 180 are printed on the weld metal pad 165.After printing solder sphere implantation or solder paste (solder paste), carry out a hot reflux (heat re-flow) technology in solder sphere side (as far as spherical matrix type encapsulation).Then; Utilize traditional welding technology; To be used for crystal wafer chip dimension encapsulation, chip size packages, ball grid array, cover the passive device of encapsulation such as crystalline substance; Be attached to the pad 180 of (on the rerouting layer) on the circuit of crystal grain 120 like electric capacity 182, resistance 183 and other crystal grain 181, shown in figure 12.Above-mentioned sub-panel 171 can be cut into most unit again.Next, test.The modularization final test can carry out through using vertical epoxy resin probe contact terminal wire pattern 102.In one embodiment,, can above electric capacity 182, resistance 183 and other crystal grain 181, cover metal covering 184 for the purpose of electromagnetic immunity (EMI), shown in figure 13.The cell substrate structure of above-mentioned panel type substrate 200 can be with reference to Figure 14, and it comprises crystal grain 201; One first substrate 203, its upside and bottom side have wire circuit; One second substrate 202, it has the wire circuit and the sticky material 204 (stress-buffer layer) of die receiving opening, upside and bottom side.Behind the EOT, above-mentioned encapsulation is selected respectively, and is positioned in pallet (Tray), the adhesive tape type cylinder (Tape&Reel).
Another embodiment of the present invention is the final terminal form of a ball grid array packages, like Figure 17 and shown in Figure 180.Encapsulating structure among Figure 17 and Figure 18 all comprise upside increase the layer with the bottom side increase layer.It is all similar with Figure 13 with Figure 10 with the formation that the bottom side increases layer that above-mentioned upside increases layer, and its described details is omitted at this.Above-mentioned bottom side increases layer and comprises a dielectric layer 400, hole 401, rerouting layer 402, a dielectric layer 403, hole 404 (metal coupling base) and solder sphere 405.Above-mentioned solder sphere 405 is formed on the above-mentioned hole 404 (metal coupling base) through the mode of printing.
Another embodiment of the present invention is the substrate that at least two in storehouse has flush type crystal grain (can be the polycrystalline grain), and it has the conduction perforation with the interior connection signal of telecommunication, and is shown in figure 19.The encapsulating structure of Figure 19 comprise a crystal grain 120, a crystal grain 600 have an aluminum bond pad 603, upside increase layer, in increase layer and the bottom side increases layer; Above-mentioned upside increase the layer, in increase the layer and the bottom side increase the layer formation similar with Figure 10 with Figure 13, the details of its description is omitted at this.Upside increases layer and comprises a dielectric layer 606, hole 604, rerouting layer 605 and a dielectric layer 607.The dorsal part of above-mentioned crystal grain/chip 600 has sticky material (stress-buffer layer) 601, and is attached on the crystal grain pad 162 of second substrate 104.Can optionally form core colloid 620 on the dielectric layer 607.It is above-mentioned that conduction perforation 159 can through the computer numerical keyhole or laser drill forms.
Please refer to Figure 20, be another embodiment of the present invention.Said semiconductor component packaging structure comprises one first substrate 700, and said first substrate 700 has the crystal grain metal gasket 701a that a wire circuit 701 and has an alignment mark and is positioned at its upper surface, and other has a wire circuit 702 and is positioned at its basal surface.One connects conduction perforation 703 is arranged at first substrate 700, to connect crystal grain metal gasket 701a and wire circuit 702, in order to ground connection and heat radiation.In addition, semiconductor component packaging structure comprises one second substrate 704.Said second substrate 704 have one be positioned at its upper surface wire circuit 705, be positioned at the wire circuit 706 of its basal surface and have the die receiving opening that holds crystal grain 720.The upper surface of crystal grain 720 is provided with connection gasket 721.The material of connection gasket 721 can use aluminium (aluminum).In one embodiment of this invention, the thickness of crystal grain 720 can approximate the thickness of second substrate 704 in fact.
One sticky material 722 is arranged at the upper surface of first substrate 700, and the basal surface of second substrate 704 and crystal grain 720, in order to the crystal grain 720 and second substrate 704 are adhered on first substrate 700.In one embodiment of the invention, sticky material 722 can use universe membrane type.The thickness of adhesion coating 722 is about 10 to 30 microns.In one embodiment, sticky material 722 can be transparent mode, with as lighting application.Conduction perforation 759 is formed between wire circuit 702 to the wire circuit 705; Through running through first substrate 700 and 704 formation of second substrate; And electric conducting material is filled up in said conduction perforation 759, in order to wire circuit 701, the wire circuit 702 of the wire circuit 705, wire circuit 706 and first substrate 700 that connect second substrate 704.
One have most holes zones 760 first dielectric layer 723 be arranged at the upper surface of second substrate 704 and crystal grain 720, and be arranged between crystal grain 720 sidewalls and the die receiving opening sidewalls.In one embodiment of the invention, the material of first dielectric layer 723 can be universe membrane type or liquid dielectric material.One rerouting layer 761 is arranged in the hole zone 760 and on first dielectric layer 723, in order to pad 721 and the wire circuit 705 of being of coupled connections, also further is coupled to conduction perforation 759 through wire circuit 705.One second dielectric layer 762 is arranged on first dielectric layer 723 and the rerouting layer 761.In one embodiment, first dielectric layer 723 and second dielectric layer 762 can be transparent mode, with as lighting application.One marked, for example, a trade mark or part number, laser capable of using or printing process are formed at second dielectric layer 762, and the terminal pad of grid array type (LGA type) encapsulation or ball grid array formula (BGA type) encapsulation can be formed on the wire circuit 702.Please refer to Figure 28, in an embodiment of diffusion type ball grid array packages structure of the present invention, several openings are arranged at second dielectric layer 762, and in wherein, and most soldered balls 780 can be arranged on the said metal coupling base in order to configuration metal coupling base.One mark, for example, a trade mark or part numeral can use wire circuit 702 to be formed at the basal surface of first substrate 700.
Please refer to Figure 21 to Figure 27, for describing another embodiment of a kind of semiconductor component packaging structure manufacturing approach of the present invention.At first, prepare one first substrate 700 and one second substrate 704.Said first substrate 700 has the crystal grain metal gasket 701a that a wire circuit 701 and has an alignment mark and is positioned at its upper surface, and has a wire circuit 702 and be positioned at its basal surface.Be positioned at its upper surface and said second substrate 704 has a wire circuit 705, and have a wire circuit and be positioned at its basal surface, shown in figure 21.
Secondly, utilize laser or process for stamping on said second substrate 704, to form a die receiving opening 707, shown in figure 22.Then, prepare a sticky material 722, shown in figure 23.Utilize above-mentioned sticky material 722, said first substrate 700 is adhered to said second substrate 704 in vacuum state, shown in figure 24.Then, use the alignment mark of crystal grain metal gasket 701a, crystal grain 720 is aimed at, and utilized the adhesive force of sticky material 722, crystal grain 720 is adhered to crystal grain metal gasket 701a, shown in figure 25.Then, with sticky material 722 sclerosis.
Then; Upper surface at second substrate 704 and crystal grain 720 forms first dielectric layer 723; And said first dielectric layer 723 is pushed into the gap between crystal grain 720 sidewalls and die receiving opening 707 sidewalls; Shown in figure 26, it can fill up the second coarse substrate 704, and the last surface smoothness of may command first dielectric layer.Need not fill up the crystal grain sidewall and not have the gap of conducting electricity between the die receiving opening sidewalls of boring a hole, because the perforation of said conduction can be vacuum state, it will can not influence the problem of temperature cycles.Then, use optical treatment or laser mode form the hole zone of first dielectric layer 723, and be shown in figure 27.Then, with 723 sclerosis of first dielectric layer.Other program that forms rerouting layer, conduction perforation or second dielectric layer etc. is similar to the narration of the foregoing description, so in this omission.
Please refer to Figure 29, in one embodiment of the invention, can be before forming dielectric layer; Form a luminescent material 791, for example, phosphorus (phosphor) is on crystal grain 720; As lighting application, and form a reflector 790, for example; Silver (Ag), gold (Au) or aluminium (A1) are on die receiving opening 707 sidewalls and crystal grain metal gasket 701a, as lighting application, to add the high light reflection factor.In one embodiment, luminescent material 791 can be covered on the crystal grain 720.In one embodiment, can the reflector be plated on die receiving opening 707 sidewalls and the crystal grain metal gasket 701a.
The advantage that the present invention has is:
Above-mentioned technology can form panel-type structure easily, and easily control panel coarse (smooth) degree.The thickness of aforesaid substrate can be controlled easily, and in technology, also can get rid of the problem of crystal grain displacement.Can omit the ejection formation instrument; Must not import chemical mechanical milling tech yet; This technology can not produce warpage yet.Through panel form packaging technology, above-mentioned panel type substrate can be done easily.The above-mentioned coupling that increases a layer beneath material (motherboard and substrate) thermal coefficient of expansion can make has preferable reliability, and also can not produce thermal stress in the X/Y of substrate direction, and the use of elastomeric dielectric material can absorb the stress of Z direction.Unit material can be cut in the process of separating (cutting).
Aforesaid substrate is predisposed to has preformed die receiving opening, inner online perforation (if desired) and terminal contacting metal (as far as organic substrate); Above-mentioned die receiving opening is of a size of every limit increases about 100 μ m～200 μ m than the size of crystal grain; Through filling the elastic core colloid; Above-mentioned opening can be used as the stress buffer release areas; Absorption does not match the thermal stress that is caused by thermal coefficient of expansion between silicon crystal grain and the substrate (refractory glass fibre plate/BMI triazine resin).In addition, also can between crystal grain and substrate sidewall spacers, fill the elastomeric dielectric material, to absorb mechanical bend and/or the thermal stress that does not match and caused by thermal coefficient of expansion.Owing to apply the above-mentioned layer that simply increases at upper surface and basal surface simultaneously, can increase encapsulation productivity ratio (reducing the manufacturing cycle).Above-mentioned terminal pad is formed at the opposite side of crystal grain active surface.
The placement technology of above-mentioned crystal grain is used and is selected and place technology.In the present invention, elastic core colloid (resin, epoxy resin compound or silicon rubber etc.) by the gap of backfill between crystal grain edge and perforated side wall, is connected with first substrate afterwards, to become the buffer release of thermal stress, carries out the vacuum hot curing at last again.The process that panel forms has overcome the unmatched problem of thermal coefficient of expansion.Depth difference between above-mentioned crystal grain and the substrate is about 25 μ m, and dielectric layer and rerouting layer all are formed at the upper surface and the basal surface of panel.Have only silicon rubber dielectric material (is good with silicone compositions) to be applied in active surface and substrate surface (is good with glass mat/refractory glass fibre plate/BMI triazine resin).Because dielectric layer is a photosensitive layer, the contacting metal pad can be opened through light shield technology.Above-mentioned crystal grain and substrate (comprising first and second substrate) link together.The reliability of above-mentioned encapsulation and motherboard (motherboard) level encapsulation is also better than in the past.Especially as far as motherboard level package temperature loop test, because substrate is consistent with the thermal coefficient of expansion of printed circuit board (PCB) (motherboard), so do not have any thermal and mechanical stress that puts on soldering projection/ball; As far as motherboard level packaging machinery crooked test, the grained region that the machine plate bottom side of supported mechanical intensity can the absorptive substrate upside and the stress of borderline region; Encapsulating structure with defencive function, its thickness is quite thin, and it can not surpass 200 μ m～300 μ m.It is with low cost and technology is simple.This technology also can form most die package (can then a ground crystal grain is imbedded display panel substrate to form most die package) easily.
The above is merely preferred embodiment of the present invention.Be not in order to limit patent protection interest field of the present invention.Change or modification that those of ordinary skill in the art is done in not breaking away from this patent spirit or scope all belong in the protection range of claims of the present invention.
Claims (10)
1. a semiconductor component packaging structure is characterized in that, said semiconductor component packaging structure comprises:
One first substrate, it has second wire circuit that first wire circuit and that a crystal grain metal gasket, is positioned at said first upper surface of base plate is positioned at said first substrate base surface, and wherein said crystal grain metal gasket comprises an alignment mark;
One crystal grain, it is disposed at the upper surface of said crystal grain metal gasket;
One second substrate; The privates circuit and one that its die receiving opening, one with a confession die receiving is positioned at said second upper surface of base plate is positioned at the privates circuit on said second substrate base surface, and the thickness of wherein said crystal grain equals the thickness of second substrate;
One adhesion coating, it is arranged at the basal surface of the upper surface of said first substrate, said second substrate and said crystal grain; And
One first dielectric layer, it is arranged at the upper surface of said crystal grain and said second substrate, and is arranged between the sidewall of sidewall and said die receiving opening of said crystal grain, and wherein said first dielectric layer comprises most holes zones.
2. semiconductor component packaging structure as claimed in claim 1; It is characterized in that; Said semiconductor component packaging structure also comprises most conduction perforation, and it runs through first substrate and second substrate, and connects first wire circuit, second wire circuit, privates circuit and privates circuit.
3. semiconductor component packaging structure as claimed in claim 1; It is characterized in that; Said semiconductor component packaging structure also comprises the rerouting layer that is positioned on most the hole zones and first dielectric layer; And the connection gasket and the privates circuit of coupling crystal grain, and further be coupled to through the conduction between first substrate and second substrate and bore a hole through the 3rd conducting wire.
4. semiconductor component packaging structure as claimed in claim 3; It is characterized in that; Said semiconductor component packaging structure also comprises second dielectric layer that is formed on first dielectric layer and the rerouting layer, and second dielectric layer has can make the projection underlying metal be formed at wherein and connect the opening of rerouting layer.
5. semiconductor component packaging structure as claimed in claim 1 is characterized in that, said semiconductor component packaging structure also is contained in the conduction perforation that runs through first substrate, and it connects the crystal grain metal gasket and second wire circuit.
6. the manufacturing approach of a semiconductor component packaging structure is characterized in that, the manufacturing approach of said semiconductor component packaging structure comprises the following step:
Prepare one first substrate and one second substrate, wherein said first substrate comprises a crystal grain metal gasket, has an alignment mark on the crystal grain metal gasket;
Utilize laser or process for stamping to form a die receiving opening through said second substrate;
Prepare a sticky material;
Utilize said sticky material that said first substrate is adhered on said second substrate;
Utilize alignment mark one crystal grain of crystal grain metal gasket, and utilize said sticky material that crystal grain is adhered on the crystal grain metal;
Form one first dielectric layer in the upper surface of second substrate and crystal grain, and first dielectric layer is pushed into the gap between crystal grain sidewall and the die receiving opening sidewalls;
Form most hole zones in first dielectric layer; And
Form a rerouting layer in most hole zones and on first dielectric layer.
7. like the manufacturing approach of the said semiconductor component packaging structure of claim 6, it is characterized in that the manufacturing approach of said semiconductor component packaging structure also comprises formation one second dielectric layer on first dielectric layer and rerouting layer.
8. like the manufacturing approach of the said semiconductor component packaging structure of claim 6, it is characterized in that the manufacturing approach of said semiconductor component packaging structure also comprises the conduction perforation of formation through first and second substrate.
9. like the manufacturing approach of the said semiconductor component packaging structure of claim 6, it is characterized in that said first substrate utilizes sticky material to be adhered to second substrate under vacuum state.
10. like the manufacturing approach of the said semiconductor component packaging structure of claim 6, it is characterized in that said first dielectric layer is urged the gap between crystal grain sidewall and the die receiving opening sidewalls under vacuum state.
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| US12/855,705 US8350377B2 (en) | 2008-09-25 | 2010-08-13 | Semiconductor device package structure and method for the same |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108369939A (en) * | 2015-12-22 | 2018-08-03 | 英特尔公司 | Semiconductor packages with electromagnetic interference shield |
| CN108369939B (en) * | 2015-12-22 | 2022-07-01 | 英特尔公司 | Semiconductor package with electromagnetic interference shielding |
| CN107230640A (en) * | 2016-03-24 | 2017-10-03 | 钰桥半导体股份有限公司 | Have radiating seat and the heat-dissipating gain-type semiconductor subassembly and its preparation method of double build-up circuitries |
| CN111755426A (en) * | 2019-03-28 | 2020-10-09 | 三星电子株式会社 | Semiconductor package |
| US11842956B2 (en) | 2019-03-28 | 2023-12-12 | Samsung Electronics Co., Ltd. | Semiconductor package |
| CN111755426B (en) * | 2019-03-28 | 2024-05-24 | 三星电子株式会社 | Semiconductor Package |
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| Publication number | Publication date |
|---|---|
| TWI533412B (en) | 2016-05-11 |
| TW201208004A (en) | 2012-02-16 |
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