CN102347317A - 半导体装置 - Google Patents
半导体装置 Download PDFInfo
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- CN102347317A CN102347317A CN2011102131916A CN201110213191A CN102347317A CN 102347317 A CN102347317 A CN 102347317A CN 2011102131916 A CN2011102131916 A CN 2011102131916A CN 201110213191 A CN201110213191 A CN 201110213191A CN 102347317 A CN102347317 A CN 102347317A
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Abstract
本发明的实施例公开了半导体装置。该半导体装置包括:基板;第一半导体裸芯,被安装在所述基板上,且具有第一组裸芯键合焊垫,x轴和y轴与第一半导体裸芯的直角边缘平行;第二半导体裸芯,被安装在第一半导体裸芯的顶部上,且具有第二组裸芯键合焊垫,第二半导体裸芯沿着x轴相对于第一半导体裸芯偏移,且第二半导体裸芯沿着y轴相对于第一半导体裸芯错排;第一组引线键合,在所述第一组裸芯键合焊垫和所述基板之间;以及第二组引线键合,在所述第二组裸芯键合焊垫和所述基板之间,第一和第二组引线键合彼此插置。
Description
技术领域
本技术涉及半导体封装。
背景技术
便携式消费电子的需求的强烈增长驱动了高容量的存储装置的需求。诸如闪存存储卡的非易失性半导体存储器装置正变得广泛用于满足对数字信息存储和交换的日益增长的需要。其便携性、多用性和强健的设计以及其高可靠性和大容量性已经使得这种存储器装置理想地用在各种电子装置中,包括例如数码相机、数字音乐播放器、视频游戏控制台、PDA和蜂窝电话中。
虽然已知了多种封装体配置,但是通常可以由所谓3-D半导体装置制造闪存存储卡。这种装置包括例如***级封装体(SiP)或多芯片模块(MCM),其中,在基板上安装堆叠配置的多个裸芯。在现有技术的图1和2中示出传统的3-D半导体封装体20(而没有模塑复合物)的侧视图。典型的封装体包括安装到基板26的多个半导体裸芯22。在所示的例子中,裸芯堆叠具有四个裸芯22a、22b、22c和22d。其他例子具有在堆叠中的更多或更少的裸芯。虽然未在图1和2中示出,但是半导体裸芯22形成有在裸芯的上表面上的裸芯键合焊垫。基板26可以由上和下导电层以及夹在其之间的电绝缘核形成。上和/或下导电层可以被蚀刻以形成包括电导线和接触焊垫的导电图案。引线键合30被热焊接在半导体裸芯22的裸芯键合焊垫和基板26的接触焊垫之间,以将半导体裸芯电耦合到基板。在基板上的电导线继而提供了裸芯和主机装置之间的电路径。一旦进行在裸芯和基板之间的电连接,则典型地在模塑复合物中包封该装配部件,以提供保护性封装。
已知通过偏移配置(现有技术图1)或对准配置(现有技术图2)彼此叠置堆叠半导体裸芯22。在图1的偏移配置中,偏移堆叠该裸芯22,使得在下面的裸芯的键合焊垫被暴露且可由引线键合装置接近。在例如Lin等人的美国专利No.6,359,340的“Multichip Module Having a Stacked ChipArrangement”中示出了这种配置,该专利的全部内容被引用合并于此。偏移配置提供方便地接近在每个半导体裸芯上的键合焊垫的优点。但是,偏移需要在基板上的更大的足印,而在基板上空间是宝贵的。
在现有技术图2的对准配置中,半导体裸芯22被直接彼此叠置堆叠,由此相比于偏移配置在基板上占据更少的足印。但是,在对准的配置中,必须对于键合引线30在相邻半导体裸芯之间提供空间。除了键合引线30自身的高度以外,必须在键合引线之上留下另外的空间,因为一个裸芯的键合引线30与上面的裸芯的接触可能导致电短路。如图2所示,因此知道提供介电间隔层34来为在相邻裸芯22之间键合的键合引线30提供足够的空间。间隔层的需求增加了裸芯堆叠的高度,且是对可以被包括在该堆叠中以仍然适合于在标准存储器卡形式因素的高度内的裸芯数量的限制因素。
虽然现有技术图1和2中所示的引线配置可以用于具有较少数量的裸芯的裸芯堆叠的半导体,但是在大于四个裸芯的裸芯堆叠中的裸芯的引线变得更有问题。除了垂直的引线键合以外,可能需要沿对角形成引线键合,且/或可能需要另外的基板接触焊垫。现有技术图3和4是包括被安装到基板26的八个裸芯的典型NAND半导体封装体20(而没有模塑复合物)的俯视图和侧视图。图3示出任意设定的x-y轴。传统地,沿着x轴偏移彼此叠置裸芯22,从裸芯0开始并顺序地继续到裸芯7。
如所注意的,基板26包括接触焊垫、诸如现有技术图3所示的接触焊垫38。包括大量裸芯的裸芯堆叠可能需要两组接触焊垫38来影响对堆叠中的裸芯的输入/输出(I/O)。在图3和4的例子中,在各个裸芯0-3上的对应的裸芯键合焊垫40彼此连接,且经由一组引线键合30a而连接到基板26上的第一组接触焊垫38a,引线键合30a从裸芯0的键合焊垫40延伸到键合焊垫38a。如在此使用的,在不同裸芯上的“对应的”裸芯键合焊垫指的是在沿着y轴彼此对准的不同裸芯上的裸芯键合焊垫。因此,例如,从图3的角度,在每个裸芯0-3上的第一(最底部)裸芯焊垫彼此对应,且被引线键合到一起,在裸芯0-3的每个的第二最底部裸芯焊垫彼此对应,且被引线键合到一起。
类似地,在各个裸芯4-7上的对应的裸芯键合焊垫40彼此连接,且经由一组引线键合30b而连接到基板26上的第二组接触焊垫38b,引线键合30b从裸芯4的键合焊垫40延伸到键合焊垫38b。在所示的实施例中,接触焊垫38a可以与基板上的接触焊垫38b交替。通过这种引线配置,引线键合的引线长度将是长的。且在堆叠中的裸芯之间的引线与引线空间可能变得更小以至于发生引线之间的电短路。这导致封装故障和对装配良率的不利影响。
为了使得上述问题最小化,如在现有技术图5和6的俯视和侧视图所示地使用裸芯堆叠旋转。在图5和6的例子中,在第一方向上偏移地堆叠第一组裸芯0-3,且第一组裸芯0-3经由引线键合30a连接到在基板26的第一侧上的一组接触焊垫38a。第二组裸芯4-7在与第一方向相反的第二方向上偏移地堆叠,且经由引线键合30b连接到在基板26的与第一侧相反的第二侧上的一组接触焊垫38b。
具有裸芯堆叠旋转的一个缺点是第一组裸芯0-3被附接且被引线键合,且然后第二组裸芯4-7被附接且被引线键合。多个裸芯附接和引线键合工艺增加周期时间,且由于在制造期间更多地操作半导体封装体而导致更低的装配良率。裸芯堆叠设计需要允许两组裸芯被引线键合到基板上的两组接触焊垫,同时避免上述问题。
传统堆叠的封装体的另一缺点是将键合引线暴露在最终的包封封装体的外部。这问题专属于具有不规则封装体轮廓的存储器封装体,诸如microSD和MsMicro。现有技术图7到9示出在microSD存储器封装体20中的堆叠的裸芯的例子。图7和9还示出了在裸芯堆叠顶上的控制器裸芯50。可以使用如上述的裸芯堆叠旋转来装配裸芯堆叠,且如图9所示。在这种实施例中,基板可能具有沿着封装体的第一边缘的接触焊垫38a,与第一组裸芯的相邻裸芯键合焊垫对准,如图7中沿边缘40所示。但是,如果封装体有不规则形状,例如,沿着封装体20的边缘42,一些裸芯键合焊垫被连接到接触焊垫38b,接触焊垫38b与其连接的裸芯键合焊垫沿对角隔开。图8示出了图7中的区域8-8的放大图。当基板被包封且单个化为封装体的最终形状时,沿着不规则形状的边缘42的一个或多个引线键合(诸如引线键合30a)可能处在包封之外,或否则过于接近封装体边缘。存在对允许高效地沿着封装体的不规则形状的边缘的引线键合、而不将引线暴露在完成的包封的封装体外部的裸芯堆叠设计的需要。
发明内容
根据本技术的一个实施例,提供一种半导体装置,其包括:基板;第一半导体裸芯,被安装在所述基板上,且具有第一组裸芯键合焊垫,x轴和y轴与第一半导体裸芯的直角边缘平行;第二半导体裸芯,被安装在第一半导体裸芯的顶部上,且具有第二组裸芯键合焊垫,第二半导体裸芯沿着x轴相对于第一半导体裸芯偏移,且第二半导体裸芯沿着y轴相对于第一半导体裸芯错排;第一组引线键合,在所述第一组裸芯键合焊垫和所述基板之间;以及第二组引线键合,在所述第二组裸芯键合焊垫和所述基板之间,第一和第二组引线键合彼此插置。
根据本技术的另一个实施例,提供一种半导体装置,其包括:基板;第一半导体裸芯,被安装在所述基板上,x轴和y轴被定义为与第一半导体裸芯的直角边缘平行;第二半导体裸芯,被安装在第一半导体裸芯的顶部上,第二半导体裸芯沿着x轴相对于第一半导体裸芯偏移,且第二半导体裸芯沿着y轴相对于第一半导体裸芯错排;以及第三半导体裸芯,被安装在第二半导体裸芯的顶部上,第三半导体裸芯沿着x轴相对于第二半导体裸芯偏移,且第三半导体裸芯沿着y轴错排以沿着y轴与第一半导体裸芯对准。
根据本技术的另一个实施例,提供一种半导体装置,其包括:基板;第一组半导体裸芯,被安装在所述基板上,第一组半导体裸芯中的每个半导体裸芯具有第一组裸芯键合焊垫,x轴和y轴被定义为与第一组半导体裸芯中的半导体裸芯的直角边缘平行;第二组半导体裸芯,被安装在所述基板上,第二组半导体裸芯中的每个半导体裸芯具有第二组裸芯键合焊垫,来自被安装在基板上的第一和第二组的半导体裸芯彼此插置,且来自第一和第二组的半导体裸芯沿着x轴相对于彼此而偏移,且来自第一组的半导体裸芯沿着y轴相对于来自第二组的半导体裸芯而错排;第一组引线键合,电耦合第一组裸芯的第一组键合焊垫的对应的裸芯键合焊垫;以及第二组引线键合,电耦合第二组裸芯的第二组裸芯键合焊垫的对应的裸芯键合焊垫,所述第一和第二组引线键合彼此插置。
根据本技术的另一个实施例,提供一种包括不规则形状的边缘的半导体装置,其包括:基板,具有相邻于不规则形状的边缘的接触焊垫;多个半导体裸芯,形成被附接到基板的裸芯堆叠,该裸芯堆叠的最低半导体裸芯直接附接到基板,且该裸芯堆叠的剩余半导体裸芯附接到最低半导体裸芯;多个对应的裸芯键合焊垫,在多个半导体裸芯中的每个上有一个对应的裸芯键合焊垫,多个对应的裸芯键合焊垫在多个半导体裸芯上彼此对应;一组引线键合,彼此电耦合多个对应的裸芯键合焊垫,该组引线键合包括从最低半导体裸芯之上的半导体裸芯的裸芯键合焊垫到基板接触焊垫的引线键合,其中,最低半导体裸芯的裸芯键合焊垫和基板接触焊垫之间的直线包括半导体装置的不规则形状的边缘之外的部分。
附图说明
图1是传统半导体装置的侧视图,该半导体装置包括以偏移关系堆叠的半导体裸芯。
图2是传统半导体装置的侧视图,该半导体装置包括以对准关系堆叠的且由间隔层分隔的半导体裸芯。
图3是半导体裸芯堆叠的俯视图,该半导体裸芯堆叠包括被引线键合到基板的八个半导体裸芯。
图4是图3所示的半导体裸芯堆叠的侧视图。
图5是包括八个半导体裸芯的旋转裸芯堆叠的俯视图。
图6是图5所示的旋转裸芯堆叠的侧视图。
图7是不规则形状的半导体裸芯封装体的俯视图。
图8是图7的一部分的放大的图,其示出包封的封装体外部的引线键合的一部分。
图9是图7所示的半导体封装体的侧视图。
图10是根据本发明的实施例的装配半导体封装体的流程图。
图11是根据本技术的在制造的第一阶段期间的半导体封装体的俯视图。
图12是根据本技术的在制造的第一阶段期间的半导体封装体的透视图。
图13是根据本技术的在制造的第二阶段期间的半导体封装体的俯视图。
图14是根据本技术的在制造的第二阶段期间的半导体封装体的透视图。
图15是根据本技术的在制造的第三阶段期间的半导体封装体的俯视图。
图16是根据本技术的在制造的第三阶段期间的半导体封装体的透视图。
图17是根据本技术的在制造的第四阶段期间的半导体封装体的俯视图。
图18是根据本技术的在制造的第四阶段期间的半导体封装体的透视图。
图19是用模塑复合物包封的根据本技术的完成的半导体封装体的侧视图。
图20是根据本发明的替换实施例的装配半导体封装体的流程图。
图21是根据本技术的另一实施例引线键合的不规则形状的半导体裸芯封装体的俯视图。
图22是图21的半导体封装体的一部分的放大图,其示出根据本技术的实施例的引线键合。
图23示出根据本技术的另一实施例的如在图22中的半导体封装体的一部分。
图24是被包封在模塑复合物内的根据本技术的实施例的完成的半导体封装体的侧视图。
具体实施方式
现在将参考图10到24来描述实施例,这涉及具有包括错排的裸芯和/或高效的引线键合的裸芯堆叠布置的半导体装置。可以理解,本发明可以不同形式实施,且应该不被解释限于在此阐述的实施例。相反,这些实施例被提供使得该公开将是充分且完整的,且将向本领域技术人员完整传授本发明。确实,本发明旨在覆盖这些实施例的替换、修改和等同,这些被包括在如由所附权利要求限定的本发明的范围和精神内。另外,在本发明的以下详细描述中,阐述多个具体细节以便提供本发明的充分理解。但是,本领域技术人员将清楚可以在没有这些具体细节的情况下实践本发明。
在此使用术语“顶部”、“底部”、“上”、“下”、“垂直”和/或“水平”仅为了方便和例示目的,但这不意味着限制本发明的描述,因为所引用的项目可以在位置上交换。
现在将参考图10的流程图和示出制造的各种阶段中的封装体100的图11到19的各图来描述根据本***的实施例的形成半导体封装体100的工艺。初始地参考图11和12的俯视图和透视图,在步骤210中,第一半导体裸芯102a可以被安装在基板120上。裸芯102a可以经由裸芯附接粘接剂在已知粘接或共晶的裸芯键合工艺中被安装到基板120。
裸芯102a可以包括沿着裸芯102a的边缘106形成的裸芯键合焊垫104。可以理解,所示的裸芯键合焊垫104的数量仅是例子,且可以在其他实施例中在裸芯102a中存在更多或更少的裸芯键合焊垫104。在实施例中,裸芯102a可以是存储器裸芯、诸如NAND闪存裸芯。但是,在其他实施例中,裸芯102a可以是其他类型的半导体裸芯、诸如例如NOR、DRAM和各种其他存储器裸芯。
虽然未示出,但是基板120可以是一板的基板的一部分,使得根据本技术的半导体封装体可以经济规模成批进行。虽然以下描述了单个半导体封装体的制造,但是可以理解,以下描述可以适用于在一板基板上形成的所有封装体。基板120可以是各种不同芯片载体介质,包括印刷电路板(PCB)、引线框架、或带载自动键合(TAB)。在基板120是PCB的情况下,基板可以由核以及在该核上形成的顶部和/或底部导电层形成。该核可以是各种介电材料,诸如例如聚酰亚胺层叠、包括FR4和FR5的环氧树脂、双马来酰亚胺-三嗪树脂(BT)等。
导电层可以由铜或铜合金、镀铜或镀铜合金、合金42(42FE/58NI)、镀铜钢板或其他金属或在基板上使用的已知材料形成。导电层可以被蚀刻为导电图案,导电图案已知用于在半导体裸芯102和外部装置(未示出)之间传送信号。基板120可能另外包括暴露的金属部分,其在基板120的上表面上形成接触焊垫122。示出接触焊垫122的数量仅作为例子,且在其他实施例中,可能存在更多或更少的接触焊垫。在半导体封装体是焊盘栅格阵列(LGA)封装体的情况下,还可以在基板120的下表面上界定触指(contact finger)(未示出)。接触焊垫122和/或触指可以被镀了一个或多个金层,例如在本领域中已知的电镀工艺中。
沿着基板120的边缘124的接触焊垫122可以设置为两个组:接触焊垫122a和接触焊垫122b。在实施例中,接触焊垫122a与接触焊垫122b交替。如以下说明的,接触焊垫122a与第一组半导体裸芯连接,且接触焊垫122b与第二组半导体裸芯连接。
在步骤214中,第二裸芯102b可以被堆叠在裸芯102a上,如在图11和12的俯视图和透视图中所示。裸芯102b可以是与裸芯102a相同的存储器裸芯,且可以包括类似数量的裸芯键合焊垫104(虽然为了清楚且与图中的裸芯102a区别,裸芯102b被示出稍微的阴影)。在其他实施例中,可以设想裸芯102a和10b不需要的相同的配置。可以在相对于裸芯102a错排和偏移的取向上固定裸芯102b。也就是说,可以相对于裸芯102a沿着y轴错排且相对于裸芯102a沿着x轴偏移裸芯102b。
裸芯102b可以被错排,使得裸芯102b的裸芯键合焊垫104在裸芯102a的裸芯键合焊垫104之间排列(且反之亦然)。在一个实施例中,裸芯102b可以相对于裸芯102a向下移动在相邻裸芯键合焊垫104之间(中心到中心)的(沿着y轴的)距离的一半以提供错排的位置。裸芯102b还可以相对于裸芯102a偏移了(沿着x轴的)一定距离,使得传统引线键合装置可以接近并将键合引线附接到裸芯102a的裸芯键合焊垫104。
虽然示出了裸芯102b相对于裸芯102a在负y方向(在图11中向下)上错排,但是在其他实施例中,裸芯102b可以在正y方向上错排,而裸芯102a的键合焊垫104位于裸芯102b的裸芯键合焊垫104之间。
裸芯102a和102b一起形成裸芯堆叠132。在不同的实施例中,裸芯堆叠132可以具有不同数量的裸芯。再次参考图10的流程图,在步骤216中,如果存在被添加于堆叠132的另外的裸芯,则在步骤220中添加另外的裸芯。例如,图13和14示出包括八个半导体裸芯102a到102h的裸芯堆叠132的俯视图和透视图。可以理解,在其他实施例中,裸芯堆叠132可以包括更少或更多的数量的裸芯。
当向堆叠添加新的裸芯时,新裸芯相对于在其上安装该新裸芯的裸芯错排且偏移。如以上所指示的,在该实施例中,裸芯102b相对于裸芯102a沿着y轴向下错排。因此,裸芯102c可以被添加到裸芯102b的顶部上,沿着y轴向上错排,使得裸芯102b的裸芯键合焊垫位于在裸芯102c的裸芯键合焊垫104之间(且反之亦然)。在实施例中,可以在裸芯102a上直接沿着y轴对准(但沿着x轴偏移)裸芯102c。被添加到裸芯堆叠的所有剩余裸芯可以类似地以相对于其所安装到的裸芯以错排和偏移的方式被添加。
每个裸芯102b到102h可以相对于其所安装到的裸芯沿着x轴以恒量偏移。另外,可以相对于其所安装到的裸芯沿着y轴向上和向下交替错排每个裸芯102b到102h。该错排的图案可能导致第一组裸芯(102a,102c,102e,102g)沿着y轴向上错排且彼此对准。该错排的图案还可能导致第二组裸芯(102b,102d,102f,102h)沿着y轴向下错排且彼此对准。
如上所述,例如参考现有技术图3和4,在传统堆叠中的裸芯可以彼此叠置偏移安装,开始于裸芯0且顺序地继续到裸芯7(在八裸芯堆叠中)。如所知的,为了唯一地寻址堆叠中的每个裸芯,在每个裸芯上的某些裸芯键合焊垫被用作芯片地址引脚。对于在堆叠中的给定裸芯,对地址引脚之一的低电压表示逻辑零,且对地址引脚之一的高电压表示逻辑一。因此,例如在每个裸芯上使用三个地址裸芯,在传统八裸芯堆叠中的每个裸芯可以被唯一地顺序寻址,从堆叠底部处的000(裸芯0)到在堆叠顶部处的111(裸芯7)。
根据本***的实施例,第一和第二组裸芯可以彼此插置,使得在以下表1中示出在堆叠132中的裸芯的编号。
表1
堆叠底部: | 裸芯0(102a) |
裸芯4(102b) | |
裸芯1(102c) | |
裸芯5(102d) | |
裸芯2(102e) | |
裸芯6(102f) | |
裸芯3(102g) | |
堆叠顶部: | 裸芯7(102h) |
如上所述,裸芯被交替地错排,使得采用堆叠中裸芯的上述顺序,第一组y轴对准的裸芯102a,102c,102e和102g顺序包括裸芯0到裸芯3。类似地,第二组y轴对准的裸芯102b,102d,102f和102h顺序包括裸芯4到裸芯7。
可以理解,在本技术的其他实施例中,裸芯堆叠中的裸芯的顺序可以不同。例如,表2示出在裸芯堆叠132中具有八个裸芯的实施例中的裸芯顺序的其他例子。
表2
堆叠底部: | 裸芯0(102a) | 裸芯4(102a) | 裸芯0(102a) | 裸芯7(102a) |
裸芯1(102b) | 裸芯0(102b) | 裸芯1(102b) | 裸芯3(102b) | |
裸芯2(102c) | 裸芯5(102c) | 裸芯4(102c) | 裸芯6(102c) | |
裸芯3(102d) | 裸芯1(102d) | 裸芯5(102d) | 裸芯2(102d) | |
裸芯4(102e) | 裸芯6(102e) | 裸芯2(102e) | 裸芯5(102e) | |
裸芯5(102f) | 裸芯2(102f) | 裸芯3(102f) | 裸芯1(102f) | |
裸芯6(102g) | 裸芯7(102g) | 裸芯6(102g) | 裸芯4(102g) | |
堆叠顶部: | 裸芯7(102h) | 裸芯3(102h) | 裸芯7(102h) | 裸芯0(102h) |
可以设想裸芯堆叠132中的裸芯的其他顺序。
现在参考图15和16的俯视图和透视图,在步骤224中,使用引线键合136,裸芯堆叠132中的裸芯可以被引线键合到基板120。具体地,在第一组中的裸芯102a、102c、102e和102g可以被引线键合,使得在该组中的每个裸芯上的对应的裸芯键合焊垫104(沿着y轴)可以被引线键合在一起。在第一组中的底部裸芯(裸芯102a)可以被引线键合到基板120上的第一组接触焊垫122a。类似地,在第二组中的裸芯102b,102d,102f和102h可以被引线键合到一起,使得在该组中的每个裸芯上的对应的裸芯键合焊垫104(沿着y轴)可以被引线键合到一起。在第一组中的底部裸芯(裸芯102b)可以被引线键合到基板120上的第二组接触焊垫122b。
可以沿裸芯堆叠的y轴以单次通过进行引线键合工艺,使得第一组裸芯上的第一组对应的键合焊垫被引线键合,第二组裸芯上的第一组对应的键合焊垫被引线键合,第一组裸芯上的第二组键合焊垫被引线键合,第二组裸芯上的第二组键合焊垫被引线键合,等等,直到形成图15和16所示的所有引线键合。或者,可以形成第一组裸芯的所有引线键合,且然后可以形成第二组裸芯的所有引线键合(或反之亦然)。可以在前向或反向引线键合工艺中形成引线键合136。
由于第一和第二组裸芯沿着y轴错排,因此第一组可以彼此引线键合,且第二组可以彼此引线键合,而没有在两组之间的键合引线的电短路。因此,例如图15和16中所示的本技术的实施例允许两个分离组的裸芯被彼此引线键合且引线键合到基板,同时避免现有技术中发现的问题。即,第一和第二组可以被分别引线键合到基板,同时最小化引线长度且防止电短路。另外,所有裸芯安装在堆叠中之后,可以单次通过进行堆叠中的所有裸芯的引线键合工艺。这避免裸芯堆叠旋转中的增加的周期次数和减小的良率,在裸芯堆叠旋转中进行了多次裸芯附接和引线键合工艺。
在上述实施例中,引线键合136可能是未镀层的金,虽然它们可以替换地是铜、铝或其他金属。在本***的另一实施例中,引线键合可以用聚合物绝缘体来预先绝缘,这使得引线的表面不导电。适用于在本***中使用的预先绝缘的引线键合的两个例子在以下中公开:美国专利5,396,104,题为,“Resin Coated Bonding Wire,Method Of Manufacturing The Same,AndSemiconductor Device”和美国公开专利申请No.2004/0124545,题为,“HighDensity Integrated Circuits And The Method Of Packaging the Same”,两者通过引用整体合并于此。
现在参考图17的俯视图和透视图,一旦已经在裸芯堆叠中提供了所有裸芯102,在步骤228中可以将控制器裸芯140固定到堆叠顶部。控制器裸芯140可以例如是ASIC,但在其他实施例中可以是其他控制器裸芯。在步骤232中,控制器裸芯140可以被引线键合到基板120上的接触焊垫122(在图17和18中为了清楚仅示出一些引线键合)。在所示的例子中,控制器裸芯140可以具有离开裸芯的两个相邻边缘的裸芯键合焊垫,其被键合到在基板120的相邻边缘上的接触焊垫122。在其他实施例中,控制器裸芯140可以具有沿着单个边缘或大于2个边缘的裸芯键合焊垫。
现在参考图19的侧视图,在裸芯堆叠被形成且被引线键合到基板120上的键合焊垫之后,在步骤236中,裸芯堆叠可以被包在模塑复合物146内。在步骤240中,包封的封装体则可以由基板单个化,以形成完成的半导体裸芯封装体100。模塑复合物146可以是已知环氧树脂,诸如可从在日本具有总部的Sumitomo公司和Nitto Denko公司可得的环氧树脂。在一些实施例中,可以可选地在步骤242中将完成的封装体100封入盖中。
如在背景部分中阐述的,对于不规则形状的封装体,可能出现沿着封装体的不规则形状的部分的一些引线被模塑在封装体之外,或过于靠近封装体的边缘。图20是用于解决该问题的本技术的另一实施例的流程图。在步骤310、314、316和320中,裸芯可以被堆叠在基板上。例如,图21和24示出包括附接到基板120的多个裸芯102a-102h的裸芯堆叠132的俯视图和侧视图。如图21的俯视图所示,基板120可以是不规则形状,诸如例如microSD存储器封装体的形状。当裸芯102被安装在基板120上时,基板可以具有不规则形状,或者在裸芯被安装在基板上之后,基板可以被形成为不规则形状。
在当前实施例中,可以沿着x轴使用裸芯堆叠旋转来安装裸芯,如图24所示。但是,可以理解,可以沿着x轴使用直的偏移来堆叠裸芯(诸如图13和14所示)。在当前实施例中,裸芯不需要沿着y轴错排,虽然在其他实施例中可构想该裸芯是y轴错排的。
在步骤324中,裸芯可以被彼此引线键合且引线键合到基板120上的接触焊垫122。底部裸芯102a具有裸芯键合焊垫104a,裸芯102b具有键合焊垫104b,裸芯102c具有键合焊垫104c等。如所示,在各个裸芯上沿着y轴彼此对应的裸芯键合焊垫104a、104b、104c等可以被彼此引线键合。
根据当前实施例,除了从底部裸芯102a的裸芯键合焊垫104a引线键合到基板120之外,还可以从在堆叠132中较高的裸芯上的键合焊垫形成一个或多个引线键合136到基板120。因此,例如,可以从裸芯102b上的裸芯键合焊垫104b形成引线键合136到基板120。如图21和图22的放大图所示,通过从较高的键合焊垫(例如键合焊垫104b)键合到基板120,引线键合都位于封装体轮廓内,与封装体的边缘隔开。在其他实施例中,可以从裸芯102b之上的裸芯形成引线键合到基板。
在实施例中,可以从最低裸芯的(一个或多个)键合焊垫形成到基板120的引线键合,其允许所有引线被包封在封装体内,与封装体的边缘隔开。在现有技术图8中所示的例子中,仅最高引线键合(从图9的视角)是有问题的。因此,在这种例子中,仅最高的引线键合可以被移动到堆叠中的较高裸芯(如图23的放大图所示)。在图23中,从裸芯102c上的键合焊垫104c形成最高引线键合(从图23的视角)。从最低裸芯102a的键合焊垫104a形成剩余的引线键合到基板。可以构想其他引线键合配置,其中,从底部裸芯102a之上的裸芯形成一个或多个引线键合到基板。
对该实施例,一旦在步骤324中进行引线键合,则可以如上所述地继续剩余步骤。在步骤332中,控制器裸芯140可以被引线键合到基板120上的接触焊垫122,如图24的侧视图和图21所示。然后,在步骤336中,裸芯堆叠可以被包封在模塑复合物146内,且然后,在步骤340中,包封的封装体可以由基板单个化,以形成完成的半导体裸芯封装体100。在一些实施例中,完成的封装体100可以可选地在步骤342中被包封在盖子内。
在上述实施例的任一中,半导体裸芯102可以是一个或多个闪存芯片,使得通过控制器裸芯140,封装体100可以被用作闪存装置。可以理解,在本***的其他实施例中,封装体100可以包括被配置以进行其他功能的半导体裸芯。上述实施例的至少一些中的封装体100可以被用在多个标准存储卡中,包括但不限于紧致闪存卡(CompactFlash card,)、智能媒体卡(SmartMediacard)、存储棒(Memory Stick)、安全数字卡(Secure Digital card)、迷你SD卡(miniSD card)、微SD卡(microSD card)、USB存储卡(USB memory card)等。
为了例示和描述的目的,已经呈现了本发明的前述详细描述。不旨在穷举或限制本发明到所公开的精确形式。在上述教导下,许多修改和变化是可能的。选择所描述的实施例使得最佳地说明本发明的原理和其实际的应用,以从而使得本领域技术人员能够以各种实施例以及适合于所构思的具体用途的各种变体最佳地使用本发明。本发明的范围旨在由所附权利要求定义。
Claims (24)
1.一种半导体装置,包括:
基板;
第一半导体裸芯,被安装在所述基板上,且具有第一组裸芯键合焊垫,x轴和y轴与所述第一半导体裸芯的直角边缘平行;
第二半导体裸芯,被安装在所述第一半导体裸芯的顶部上,且具有第二组裸芯键合焊垫,所述第二半导体裸芯沿着x轴相对于所述第一半导体裸芯偏移,且所述第二半导体裸芯沿着y轴相对于所述第一半导体裸芯错排;
第一组引线键合,在所述第一组裸芯键合焊垫和所述基板之间;以及
第二组引线键合,在所述第二组裸芯键合焊垫和所述基板之间,所述第一和第二组引线键合彼此插置。
2.根据权利要求1的半导体装置,其中,所述第一和第二半导体裸芯是闪存半导体裸芯。
3.根据权利要求1的半导体装置,其中,所述第一和第二半导体裸芯是NAND半导体裸芯。
4.根据权利要求1的半导体装置,还包括控制器裸芯,被安装在所述第二半导体裸芯上且电连接到所述基板。
5.根据权利要求4的半导体装置,还包括至少围绕着所述第一和第二半导体裸芯、所述第一和第二组引线键合和所述控制器裸芯的模塑复合物。
6.根据权利要求1的半导体装置,其中,所述基板是印刷电路板、引线框架、和带载自动键合之一。
7.根据权利要求1的半导体装置,其中,所述半导体装置包括紧致闪存卡、智能媒体卡、存储棒、安全数字卡、迷你SD卡、微SD卡、和USB存储卡之一。
8.根据权利要求1的半导体装置,其中,所述第一和第二组引线键合的至少之一被电绝缘。
9.一种半导体装置,包括:
基板;
第一半导体裸芯,被安装在所述基板上,x轴和y轴被定义为与所述第一半导体裸芯的直角边缘平行;
第二半导体裸芯,被安装在所述第一半导体裸芯的顶部上,所述第二半导体裸芯沿着x轴相对于所述第一半导体裸芯偏移,且所述第二半导体裸芯沿着y轴相对于所述第一半导体裸芯错排;以及
第三半导体裸芯,被安装在所述第二半导体裸芯的顶部上,所述第三半导体裸芯沿着x轴相对于所述第二半导体裸芯偏移,且所述第三半导体裸芯沿着y轴错排以沿着y轴与所述第一半导体裸芯对准。
10.根据权利要求9的半导体装置,还包括第四半导体裸芯,被安装在所述第三半导体裸芯的顶部上,所述第四半导体裸芯沿着x轴相对于所述第三半导体裸芯偏移,且所述第四半导体裸芯沿着y轴错排以沿着y轴与所述第二半导体裸芯对准。
11.根据权利要求10的半导体装置,还包括:
在所述第一、第二、第三和第四半导体裸芯的每个上的裸芯键合焊垫;
第一组引线键合,将所述第一和第三半导体裸芯上的对应的裸芯键合焊垫连接到所述基板;以及
第二组引线键合,将所述第二和第四半导体裸芯上的对应的裸芯键合焊垫连接到所述基板。
12.根据权利要求11的半导体装置,其中,所述第一和第二组键合引线彼此插置。
13.根据权利要求11的半导体装置,其中,所述第一和第二组引线键合中的至少一个被电绝缘。
14.根据权利要求9的半导体装置,还包括控制器裸芯。
15.根据权利要求9的半导体装置,还包括模塑复合物,用于包封所述第一、第二和第三半导体裸芯。
16.一种半导体装置,包括:
基板;
第一组半导体裸芯,被安装在所述基板上,在所述第一组半导体裸芯中的每个半导体裸芯具有第一组裸芯键合焊垫,x轴和y轴被定义为与所述第一组半导体裸芯中的半导体裸芯的直角边缘平行;
第二组半导体裸芯,被安装在所述基板上,在所述第二组半导体裸芯中的每个半导体裸芯具有第二组裸芯键合焊垫,来自被安装在基板上的第一和第二组的半导体裸芯彼此插置,且来自所述第一和第二组的半导体裸芯沿着x轴相对于彼此而偏移,且来自所述第一组的半导体裸芯沿着y轴相对于来自所述第二组的半导体裸芯而错排;
第一组引线键合,电耦合所述第一组裸芯的第一组键合焊垫的对应的裸芯键合焊垫;以及
第二组引线键合,电耦合所述第二组裸芯的第二组裸芯键合焊垫的对应的裸芯键合焊垫,所述第一和第二组引线键合彼此插置。
17.根据权利要求16的半导体装置,其中,所述第一组半导体裸芯沿着y轴彼此对准。
18.根据权利要求17的半导体装置,其中,所述第二组半导体裸芯沿着y轴彼此对准。
19.根据权利要求16的半导体装置,其中,所述第一组半导体裸芯包括四个半导体裸芯,且所述第二组半导体裸芯包括四个半导体裸芯。
20.根据权利要求19的半导体装置,其中,彼此叠置的裸芯的为了寻址目的顺序是裸芯0、裸芯4、裸芯1、裸芯5、裸芯2、裸芯6、裸芯3、裸芯7、且所述裸芯0、所述裸芯1、所述裸芯2和所述裸芯3属于所述第一组半导体裸芯,且所述裸芯4、所述裸芯5、所述裸芯6和所述裸芯7属于所述第二组半导体裸芯。
21.一种包括不规则形状的边缘的半导体装置,包括:
基板,具有相邻于所述不规则形状的边缘的接触焊垫;
多个半导体裸芯,形成被附接到所述基板的裸芯堆叠,所述裸芯堆叠的最低半导体裸芯直接附接到所述基板,且所述裸芯堆叠的剩余半导体裸芯附接到所述最低半导体裸芯;
多个对应的裸芯键合焊垫,在所述多个半导体裸芯中的每个上有一个对应的裸芯键合焊垫,所述多个对应的裸芯键合焊垫在所述多个半导体裸芯上彼此对应;
一组引线键合,彼此电耦合所述多个对应的裸芯键合焊垫,该组引线键合包括从所述最低半导体裸芯之上的半导体裸芯的裸芯键合焊垫到所述基板接触焊垫的引线键合,其中,所述最低半导体裸芯的裸芯键合焊垫和所述基板接触焊垫之间的直线包括所述半导体装置的不规则形状的边缘之外的部分。
22.根据权利要求21的半导体装置,其中,具有引线键合到所述基板接触焊垫的裸芯键合焊垫的半导体裸芯是自所述裸芯堆叠的底部的第二裸芯。
23.根据权利要求21的半导体装置,其中,具有引线键合到所述基板接触焊垫的裸芯键合焊垫的半导体裸芯是自所述裸芯堆叠的底部的第三裸芯。
24.根据权利要求21的半导体装置,其中,所述半导体装置包括微SD卡和MsMicro卡之一。
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