CN102347076A

CN102347076A - Memory element and injection method for memory selecting hot carriers of NAND gate flash memory

Info

Publication number: CN102347076A
Application number: CN2010102448921A
Authority: CN
Inventors: 黄竣祥; 蔡文哲
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2010-07-27
Filing date: 2010-07-27
Publication date: 2012-02-08
Anticipated expiration: 2030-07-27
Also published as: CN102347076B

Abstract

The invention relates to a memory element and an injection method for memory selecting hot carriers of an NAND gate flash memory. The memory element described by the invention comprises a plurality of memory cells which are arranged in a manner of series connection in a semiconductor main body, such as an NAND array, and has a plurality of word lines. One selected memory cell is programmed through hot-carrier injection; and the hot carriers are generated by building a heating electric field with the adoption of the electric potential of a lifting channel to cross over a channel of the selected memory cell. The hot-carrier injection of the lifting channel is realized by blocking current of the selected memory cell from a first side to a second side in the NAND array; the voltage of a main body zone of a first semiconductor is boosted per se to a self-boost voltage through a capacitive coupling; a main body zone of a second semiconductor is biased to a reference voltage step; a programmed electric potential which is more than a channel hot-carrier injection energy barrier step is applied to select memory cells so that energy carriers can detent and claim for the memory cells from the main body zone of the second semiconductor so as to generate the hot-carrier injection.

Description

Hot carrier injecting method is remembered in choosing of memory cell and Sheffer stroke gate fast flash memory bank

Technical field

The present invention relates to a kind of fast-flash memory body technique, particularly relate to a kind of in the Sheffer stroke gate configuration suitable operation skill as low-voltage sequencing and erase operation.

Background technology

Fast flash memory bank is a type of non-volatile ic memory technology.Traditional fast flash memory bank uses the floating grid memory cell.Along with the density of memory storage promotes, exceed between the floating grid memory cell and add closely, the electric charge reciprocal effect that is stored in the adjacent floating grid promptly throws into question, and therefore forms restriction, makes and adopts the fast-flash memory volume density of floating grid to promote.The employed memory cell of another kind of fast flash memory bank is called the charge-trapping memory cell, and it adopts electric charge capture layer to replace floating grid.The charge-trapping memory cell is to utilize the charge-trapping material, can not cause influencing each other between indivedual memory cells like floating grid, and can be applied to highdensity fast flash memory bank.

Typical Charge Storage memory cell comprises a field-effect transistor (FET) structure; Wherein comprise the source electrode and the drain electrode of separating by passage; And by a charge storing structure and with the grid of channel separation, wherein this charge storing structure comprise tunneling dielectric layer, electric charge storage layer (floating grid or dielectric layer), with resistance barrier dielectric layer.Early traditional design such as SONOS device; Wherein source electrode, drain electrode and tunnel-shaped are formed on the silicon substrate (S), and tunneling dielectric layer is then formed by monox (O), and electric charge storage layer forms (N) by silicon nitride; Resistance barrier dielectric layer is formed by monox (O), and grid then is a polysilicon (S).

The fast-flash memory body device can use Sheffer stroke gate (NAND) or rejection gate (NOR) framework to implement usually, but also can be other framework, comprises and door (AND) framework.This Sheffer stroke gate (NAND) framework special because its favored in the high density of data storage application facet and advantage at a high speed.Rejection gate (NOR) framework then is that to be suitable for for example be that law of procedure storage waits other to use, because random access is the important function demand.In a Sheffer stroke gate (NAND) framework, programmed process normally relies on Fu Le-Nuo Dehan (FN) and wears tunnel, and needs high voltage, normally in 20 voltage magnitudes, and needs high voltage transistor to handle.High voltage transistor that this is extra and collocation are used in the transistor of logic and other data streams in same integrated circuit, can cause the complicacy of technology to increase.Like this then can increase the manufacturing cost of this device.

This shows that above-mentioned existing fast-flash memory body device obviously still has inconvenience and defective, and demands urgently further improving in product structure and use.In order to solve the problem of above-mentioned existence; Relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly; But do not see always that for a long time suitable design is developed completion; And common product and method do not have appropriate structure and method to address the above problem, and this obviously is the problem that the anxious desire of relevant dealer solves.Therefore how to found a kind of new memory cell and choosing of Sheffer stroke gate fast flash memory bank and remember hot carrier injecting method, real one of the current important research and development problem that belongs to, also becoming the current industry utmost point needs improved target.

Summary of the invention

The objective of the invention is to; Overcome the defective that existing fast-flash memory body device exists; And provide a kind of new memory cell and choosing of Sheffer stroke gate fast flash memory bank to remember hot carrier injecting method; Technical matters to be solved is to make it in Sheffer stroke gate (NAND) framework, utilize low-voltage can realize programming operations, is very suitable for practicality.

The object of the invention and solve its technical matters and adopt following technical scheme to realize.According to a kind of memory cell that the present invention proposes, comprise: a plurality of memory cells are series in the semiconductor main body, many character lines, and the character line in these many character lines couples with memory cell in these corresponding a plurality of memory cells; And control circuit and this many bit lines couple, and with the following step one in corresponding this a plurality of memory cells of one selected character line are chosen memory cell and carry out sequencing: when a sequencing is interval, apply one through the voltage character line of one first side of this selected character line extremely; By capacitive couplings with the self-voltage rise voltage of the self-voltage rise in one first semiconductor body zone; When this sequencing is interval, apply a sequencing voltage to this selected character line; When this sequencing is interval, be biased in one second semiconductor body zone to a reference voltage of one second side of this selected character line; And apply one and switch voltage to the one character line adjacent with this selected character line; This switched voltage has a phase one and a subordinate phase when this sequencing is interval; With will be corresponding in this phase one with this selected character line this choose memory cell and this reference voltage and isolate, and this is chosen memory cell and this reference voltage couples in this subordinate phase.

The object of the invention and solve its technical matters and also can adopt following technical measures further to realize.

Aforesaid memory cell, wherein corresponding with this selected character line this are chosen memory cell and when this subordinate phase, are biased to this switched voltage to carry out the hot carrier sequencing of passage.

Aforesaid memory cell, wherein said switched voltage are less than this sequencing voltage when this subordinate phase.

Aforesaid memory cell, wherein said a plurality of memory cells are arranged to a Sheffer stroke gate tandem.

Aforesaid memory cell; Comprise that also one first change-over switch is between one first side of a bit line and these a plurality of memory cells; Reach one second change-over switch between one second side of a reference line and these a plurality of memory cells, and wherein this control circuit opens this first change-over switch and cuts out this second change-over switch in this sequencing interval.

Aforesaid memory cell; Comprise that also more than second memory cell and these many character lines couple; And wherein this control circuit applies one second corresponding bit line of more than second memory cell of a voltage to one and this will isolating with semiconductor body region in this corresponding more than second memory cell of this second side of this selected character line, and applies one and produce hot carrier with semiconductor body region to a voltage at this more than second memory cell place of self- voltage rise with the memory cell in this more than second memory cell that suppresses to couple with this selected character line in the corresponding character line of this second side of this selected character line by voltage.

Aforesaid memory cell; Also comprising extra memory cell is series in this semiconductor body zone and an extra character line with these a plurality of memory cells; And this extra memory cell is placed between these a plurality of memory cells and this second change-over switch; And pass through voltage in this extra character line when this control circuit applies one in this sequencing interval, therefore the capacitance in this semiconductor body zone of this first side of this selected character line improves.

Aforesaid memory cell, wherein said control circuit is opened this second change-over switch in this phase one of the part of this switched voltage, and this switched voltage this subordinate phase of at least a portion close this second change-over switch.

Aforesaid memory cell; Comprise that also one first change-over switch is between one first side of a bit line and these a plurality of memory cells; Reach one second change-over switch between one second side of a reference line and these a plurality of memory cells, and wherein this control circuit cuts out this first change-over switch and opens this second change-over switch in this sequencing interval.

Aforesaid memory cell; Comprise that also more than second memory cell and these many character lines and one second bit line couple; And the one first semiconductor body zone of this control circuit in interval this second bit line of bias voltage of this sequencing makes this more than second memory cell in this first side of this selected character line wherein, and one second semiconductor body zone in this more than second memory cell of this second side of this selected character line is biased to a reference voltage to suppress the generation of hot carrier.

Aforesaid memory cell; Also comprising extra memory cell is series in this semiconductor body zone and an extra character line with these a plurality of memory cells; And this extra memory cell is placed between these a plurality of memory cells and this first change-over switch; And pass through voltage in this extra character line when this control circuit applies one in this sequencing interval, therefore the capacitance in this semiconductor body zone of this first side of this selected character line improves.

Aforesaid memory cell, wherein said control circuit apply one and switch voltage bar character line at the most when this sequencing is interval.

Aforesaid memory cell; Wherein said many character lines comprise the end of first group of character line near these a plurality of memory cells; And the other end of second group of close these a plurality of memory cell of character line; And it is at this first group or second group that this control circuit determines this to choose the character line, and distributes this this first end of choosing the character line for comprising this first group or second group.

Aforesaid memory cell; These a plurality of memory cells that wherein are series in the semiconductor main body are between first and second switching transistor, and these many character lines comprise that one first tandem selection wire and one second tandem selection wire couple with this first and second switching transistor respectively.

The object of the invention and solve its technical matters and also adopt following technical scheme to realize.According to a kind of memory cell that the present invention proposes, comprise: a Sheffer stroke gate tandem comprises that a plurality of memory cells are series in the semiconductor main body; Many character lines, the character line in these many character lines couples with memory cell in these corresponding a plurality of memory cells; And control circuit and this many bit lines couple, and with the following step one in corresponding this a plurality of memory cells of one selected character line are chosen memory cell and carry out sequencing: stop that the carrier of choosing between the one second semiconductor body zone of one second side of memory cell between this of one first semiconductor body zone and this Sheffer stroke gate tandem that this of this Sheffer stroke gate tandem chosen one first side of memory cell is mobile; By capacitive couplings with the self-voltage rise voltage of this first semiconductor body self-voltage rise in zone; This second semiconductor body zone is biased into a reference voltage; Apply greater than a sequencing current potential of a hot carrier injection energy barrier and choose memory cell to this; And the activation carrier is chosen memory cell to cause the generation of hot carrier from this second semiconductor body zone flows to this.

The object of the invention and solve its technical matters and adopt following technical scheme to realize in addition again.A kind of Sheffer stroke gate fast flash memory bank that proposes according to the present invention choose the hot carrier injecting method of memory, it may further comprise the steps: stop that the carrier of choosing between the one second semiconductor body zone of one second side of memory cell between this of one first semiconductor body zone and this Sheffer stroke gate tandem that this of this Sheffer stroke gate tandem chosen one first side of memory cell is mobile; By capacitive couplings with the self-voltage rise voltage of this first semiconductor body self-voltage rise in zone; This second semiconductor body zone is biased into a reference voltage; Apply greater than a sequencing current potential of a hot carrier injection energy barrier and choose memory cell to this; And the activation carrier is chosen memory cell to cause the generation of hot carrier from this second semiconductor body zone flows to this.

Hot carrier injecting method is remembered in choosing of aforesaid Sheffer stroke gate fast flash memory bank; Comprise that adjacent this that applies in two stage switched voltages to this Sheffer stroke gate tandem choose a memory cell of memory cell; Comprise that a phase one closes this memory cell and stop to implement this, and a subordinate phase is opened this memory cell to implement this activation.

Hot carrier injecting method is remembered in choosing of aforesaid NAND gate fast flash memory bank; This NAND gate tandem in the wherein said NAND gate array comprises that one first change-over switch is between one first side and a bit line or a reference line of this NAND gate tandem; And one second change-over switch is between one second side and this reference line or bit line of these a plurality of memory cells; And wherein should oneself's voltage rise comprise: close one comprise in this NAND gate tandem of choosing memory cell this first change-over switch with this first semiconductor body zone isolation and apply one by voltage in choosing the character line that this first side in the NAND gate tandem of memory cell couples with this, and open this second change-over switch and apply a reference voltage to this second semiconductor body zone via this second change-over switch.

Hot carrier injecting method is remembered in choosing of aforesaid Sheffer stroke gate fast flash memory bank, comprises and closes this first and second change-over switch of not choosing in the Sheffer stroke gate tandem.

Aforesaid Sheffer stroke gate fast flash memory bank choose the hot carrier injecting method of memory, comprise that unlatching do not choose this first and second change-over switch in the Sheffer stroke gate tandem.

Hot carrier injecting method is remembered in choosing of aforesaid NAND gate fast flash memory bank; This NAND gate tandem of wherein said array comprises one first group M memory cell and one second group N memory cell; And if this to choose memory cell be in this M of first group memory cell; Then this NAND gate tandem of bias voltage makes this first semiconductor body zone comprise this N of second group memory cell at least; And if this to choose memory cell be in this N of second group memory cell, then this NAND gate tandem of bias voltage makes this first semiconductor body zone comprise this M of first group memory cell at least.

The present invention compared with prior art has tangible advantage and beneficial effect.Can know that by above technical scheme major technique of the present invention thes contents are as follows:

Memory cell described herein comprises a plurality of memory cell series connection and is arranged in the semiconductor main body, for example can be applied in the Sheffer stroke gate tandem of Sheffer stroke gate array, has many character lines and couples with corresponding memory cell.Control circuit and this many bit lines and semiconductor body couple, and being fit to by hot carrier injection one selected memory cell being carried out sequencing, these hot carriers are to use the lifting channeling potential to add thermoelectric field with foundation and stride across this and choose the passage of memory cell and produce.Apply the character line of one first side through voltage to this selected character line when using the hot carrier of this technology can be by control circuit in a sequencing interval; With by capacitive couplings with the self-voltage rise voltage of the self-voltage rise in one first semiconductor body zone; And it can apply a sequencing voltage to this selected character line when this sequencing is interval, and when this sequencing interval, be biased in this selected character line one second side one second semiconductor body zone to reference voltage class and reach.One switch voltage be applied to one with the character line of this selected character line adjacency; This switched voltage has a phase one and a subordinate phase when this sequencing is interval; With this phase one by closing corresponding memory cell with first and second semiconductor body zone isolation and set up respectively should oneself's voltage rise voltage class and reference voltage class, and corresponding memory cell is selected memory cell with this and this reference voltage class couples and cause hot carrier to be injected by opening in this subordinate phase.

This selected character line is enough to overcome hot carrier injection energy barrier height in this sequencing interval by a sequencing voltage and comes bias voltage.Yet this sequencing voltage can be required far below typical Fu Le-Nuo Dehan (FN) sequencing.It is low to pass through voltage to suppress the interference of other memory cells than sequencing voltage that corresponding with these a plurality of memory cells other character lines receive one.Switched voltage in the interval subordinate phase of sequencing also is to be lower than sequencing voltage similarly to suppress to switch the interference of memory cell.

As far as a Sheffer stroke gate tandem configuration embodiment; One first change-over switch (ground connection is selected change-over switch or end bit line options change-over switch) is between one first side of a bit line and these a plurality of memory cells, and one second change-over switch (tandem is selected change-over switch or top bit line options change-over switch) is between one second side of a reference line and these a plurality of memory cells.In this embodiment, control circuit operates in interval this first change-over switch of opening of this sequencing by isolating this semiconductor body and this first side of choosing the character line with activation oneself voltage rise channeling potential.Control circuit operates in interval this second change-over switch of opening of this sequencing and borrows and connect this semiconductor body and this reference voltage line of choosing the pairing bit line of second side of character line or applying reference voltage.

More than second memory cell couples with these identical many character lines; For example in a parallel Sheffer stroke gate tandem of not choosing on the bit line; This control circuit is by first and second change-over switch of cutting out this more than second memory cell and apply one and choose the memory cell of memory cell both sides through voltage to this, arranges to carry out " self-voltage rise source electrode ".In this arranged, this semiconductor body zone of choosing character line both sides was injected with the hot carrier that prevents not choose in the tandem by self-voltage rise to similar voltage class.Alternatively; This control circuit can use " grounded drain " to arrange, and this semiconductor body zone to reference voltage class that chooses the memory cell both sides is to prevent not choose the hot carrier injection in the tandem by first and second change-over switch of opening this more than second memory cell and with bias voltage.

This control circuit can be operated the electric capacity maximization with first semiconductor body zone, and this first semiconductor body zone can be promoted to a self-voltage rise voltage class by many technology.According to a kind of technology, a plurality of memory cells can extend and also comprise one or more extra memory cells along one or more extra character line, and are placed between these a plurality of memory cells and this first change-over switch.In this technology, control circuit apply one through voltage in this extra character line expanding this first semiconductor body area size, therefore the capacitance in this first semiconductor body zone is provided.According to another kind of technology, control circuit is arranged to an end that comprises close these a plurality of memory cells of first group of character line with these many character lines, and the other end of second group of close these a plurality of memory cell of character line.When memory cell is chosen in sequencing one; The decision of this control circuit this to choose the character line be the member at one of this first group or second group; And distribute this this first end of choosing the character line can be by the so far self-voltage rise voltage of self-voltage rise class, it be that end that comprises another group of this first group or second group.In the case, can be used for setting up the size in first semiconductor body zone at least at one of them all character lines of this first group or second group.So, in this tandem all memory cells be used for setting up first semiconductor body zone of self-voltage rise voltage class can be greater than second semiconductor body zone that is used for setting up reference voltage class.

What the present invention also provided a kind of Sheffer stroke gate fast flash memory bank chooses the hot carrier injecting method of memory, comprises to stop that the carrier of choosing between the one second semiconductor body zone of one second side of memory cell between this of one first semiconductor body zone and this Sheffer stroke gate tandem that this of this Sheffer stroke gate tandem chosen one first side of memory cell is mobile; By capacitive couplings with the self-voltage rise voltage of this first semiconductor body self-voltage rise in zone; This second semiconductor body zone is biased into a reference voltage class; Apply greater than a sequencing current potential of hot carrier injection energy barrier class and choose memory cell to this; And the activation carrier is chosen memory cell to cause the generation of hot carrier from this second semiconductor body zone flows to this.

By technique scheme, the hot carrier injecting method of memory of choosing of memory cell of the present invention and Sheffer stroke gate fast flash memory bank has advantage and beneficial effect at least:

The present invention can press down the process interference because of low operating voltage.New sequencing according to the hot carrier injection of using the lifting node potential to reach can be used than low operating voltage.Because than the result of low operating voltage, the driving circuit in this integrated circuit can only use a kind of metal-oxide half field effect transistor technology to execute work, and does not need extra high voltage metal-oxide half field effect transistor technology.

The present invention is with because compare than traditional channel hot electron injection operation, and this bit line voltage need not overcome injection of hot electrons energy barrier height.Therefore, bit line voltage can be VCC or the lower voltage of other more traditional channel hot electron injection (CHE) sequencing voltage.In addition, the bit line can be when channel hot electron not be injected consumed dc current.So the method for programming that this kind is new should be reached low power consumption.

In addition, the character line voltage of this method for programming also is that to be lower than traditional Sheffer stroke gate fast flash memory bank FN programming operations required.Therefore do not need very high-tension drive unit.In addition, also required through the vertical electric field of tunnel oxide in this Sheffer stroke gate fast flash memory bank less than the FN injection.Because the result of low electrical field requirements, reliability that can lifting gear.

Furthermore; The present invention can cause reducing the dielectric voltage between the character line because of low sequencing and the Vpass voltage required than traditional F N programming operations, and therefore reduces because dwindle the dielectric crash issue between the character line that is produced between the distance between the character line.

In sum; The invention relates to a kind of memory cell and Sheffer stroke gate fast flash memory bank choose the memory hot carrier injecting method; Can low sequencing and the Vpass voltage required cause reducing the dielectric voltage between the character line, and therefore reduce because dwindle the dielectric crash issue between the character line that is produced between the distance between the character line than traditional F N programming operations.The present invention has obvious improvement technically, and has tangible good effect, really is the new design of a novelty, progress, practicality.

Above-mentioned explanation only is the general introduction of technical scheme of the present invention; Understand technological means of the present invention in order can more to know; And can implement according to the content of instructions; And for allow above-mentioned and other purposes of the present invention, feature and advantage can be more obviously understandable; The following special preferred embodiment of lifting; And conjunction with figs., describe in detail as follows.

Description of drawings

Figure 1A and Figure 1B are the sectional views that shows existing known techniques Sheffer stroke gate (NAND) structural flash memory body.

Fig. 2 A and Fig. 2 B show that drain two stages of self-voltage rise, hot carrier sequencing of a sequencing interval according to the embodiment of the invention choose two stage sectional views of Sheffer stroke gate (NAND) tandem.

Fig. 3 shows a sequential chart of choosing the interval voltage waveform of two phase sequencings of bit line in Fig. 2 A and Fig. 2 B.

Fig. 4 is that demonstration one Sheffer stroke gate tandem is not chosen the sequential chart of bit line in the interval voltage waveform of sequencing, and this does not choose the bit line is to share the character line with selected Sheffer stroke gate tandem.

Fig. 5 A and Fig. 5 B show a bias voltage diagrammatic cross-section in two stages of not choosing the sequencing of Sheffer stroke gate tandem, and it is to share the character line with selected Sheffer stroke gate tandem under the situation of bias voltage hot carrier sequencing with lifting-node of Fig. 4 demonstration in a Sheffer stroke gate tandem.

Fig. 6 is the synoptic diagram that shows a common source polar form attitude Sheffer stroke gate memory array that uses sequencing biased operation described herein.

Fig. 7 shows the synoptic diagram that uses a common source polar form attitude Sheffer stroke gate memory array of sequencing biased operation described herein according to an alternate embodiment.

Fig. 8 is the synoptic diagram that shows a virtual ground Sheffer stroke gate array that uses sequencing biased operation described herein.

Fig. 9 shows the synoptic diagram that substitutes a virtual ground Sheffer stroke gate array of implementing use sequencing biased operation described herein according to.

Figure 10 shows the synoptic diagram that substitutes a virtual ground Sheffer stroke gate array of implementing use sequencing biased operation described herein according to, and it comprises that surpassing one switches memory cell.

Figure 11 shows one to choose the bit line and promoting-the concise and to the point diagrammatic cross-section of the interval phase one bias voltage of two phase sequencings of the hot carrier sequencing of node that wherein the target memory born of the same parents are the tail ends near the Sheffer stroke gate tandem.

Figure 12 shows one to choose the bit line and promoting-the concise and to the point diagrammatic cross-section of the interval phase one bias voltage of two phase sequencings of the hot carrier sequencing of node that wherein the Sheffer stroke gate tandem is to extend by false character line.

Figure 13 shows to have the simplified topology synoptic diagram of false character line in abutting connection with the extreme Sheffer stroke gate array of the common source of Sheffer stroke gate tandem.

Figure 14 shows to have false character line is selected a Sheffer stroke gate array of line end in abutting connection with the tandem of Sheffer stroke gate tandem simplified topology synoptic diagram.

Figure 15 is the simplified topology synoptic diagram that shows the Sheffer stroke gate array do not have false character line, wherein shows one first group of simplified topology synoptic diagram with second group of character line logic arrangement, and making one, to choose the virtual drain electrode end of memory cell always extreme greater than virtual source.

Figure 16 shows to have the simplified topology synoptic diagram of false character line in abutting connection with a Sheffer stroke gate array at Sheffer stroke gate tandem two ends.

Figure 17 is that interval the use to bring out one of the hot carrier injection of lifting node described herein of display routineization substitutes the scheduling synoptic diagram.

Figure 18 is that the interval use of display routineization is to bring out another alternative scheduling synoptic diagram of the hot carrier injection of lifting node described herein.

Figure 19 is the rough schematic view that shows integrated circuit, and it uses the Sheffer stroke gate fast flash memory bank of the virtual drain electrode of self-voltage rise described herein, hot carrier injecting programization.

7,8: gate dielectric layer 9: the charge-trapping structure

10: semiconductor body 11,19: contact

12-18: node 21: ground connection selection wire GSL

22-27: character line 28: tandem selection wire SSL

30,105: common source line CS31: the bit line

32: do not choose the bit line

40,100,157,180,300,320: the target memory born of the same parents

41,113,155,156,181,304,324: switch memory cell

42,43: change-over switch 50,51: area of isolation

52: vague and general regional 54: hot carrier

62: self-voltage rise zone

101,102,103,104,201-207: Sheffer stroke gate tandem

111: ground connection is selected transistor 112: tandem is selected transistor

301,302,321,322: switching transistor 401,402: false character line

500-503: source/drain electrode tandem 810: integrated circuit

812: Sheffer stroke gate fast-flash memory volume array 814: character line (row) demoder and driver

816: character line 818: bit line demoder

820: bit line 822,826: bus-bar

824: sensing amplifier/data input structure 830: other circuit

834: (hot carrier injecting programization and FN wipe) controller

836: bias voltage adjustment supply voltage 828: data input line

832: the data output line

Embodiment

Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention; Below in conjunction with accompanying drawing and preferred embodiment; To the memory cell that proposes according to the present invention and Sheffer stroke gate fast flash memory bank choose hot its embodiment of carrier injecting method of memory, structure, method, step, characteristic and effect thereof, describe in detail as after.

Relevant aforementioned and other technology contents, characteristics and effect of the present invention can be known to appear in the following detailed description that cooperates with reference to graphic preferred embodiment.Through the explanation of embodiment, when can being to reach technological means that predetermined purpose takes and effect to obtain one more deeply and concrete understanding to the present invention, yet the appended graphic usefulness that only provides reference and explanation be not to be used for the present invention is limited.

Figure 1A and Figure 1B are the sectional views that shows existing known techniques Sheffer stroke gate (NAND) structural flash memory body, show that wherein a plurality of dielectric charge trapping flash memory cell series connection arrangements supply FN to wear the usefulness of tunnel sequencing to form Sheffer stroke gate tandem and bias voltage.Figure 1A shows the bias voltage of a Sheffer stroke gate tandem, and it comprises the target memory born of the same parents that choose on the bit line, and Figure 1B shows the bias voltage that is not selected the bit line on the Sheffer stroke gate tandem.Use energy gap engineering SONOS charge-trapping technology can consult No. the 7315474th, the United States Patent (USP) of Lue with a technology of implementing the Sheffer stroke gate fast flash memory bank, it draws at this and is reference.The Sheffer stroke gate tandem can use many configuration with different to implement, and comprises fin-shaped field-effect transistor technology, shallow trench isolation technology, vertical Sheffer stroke gate technology or the like.The example of some vertical Sheffer stroke gate structure sees also people's title such as Kim and is No. 2048709, the European patent EP of " Non-volatile memory device, method of operating same andmethod of fabricating the same ".

See also shown in Figure 1A, this memory cell shows and is formed on the semiconductor main body 10.For n passage memory cell, semiconductor body 10 can be a p well of isolating, and it is positioned at the dark n wellblock of semiconductor wafer.Alternatively, this semiconductor body 10 can be isolated by dielectric layer or other materials.Also can use p passage memory cell among some embodiment, wherein the dopant material of semiconductor body is the n type.

A plurality of flash memory cells can be arranged to the tandem of arranging with the bit line direction of character line direction quadrature along.Character line 22-27 is along stretching through some parallel Sheffer stroke gate tandems.Node 12-18 is by the n type in semiconductor body zone (as far as the n lane device), and as the source/drain region of memory cell.First change-over switch that is formed by the metal oxide semitransistor has a grid in ground connection selection wire GSL 21, its be connected in corresponding memory cell with first character line 22 and the contact 11 that forms by the zone of the n type in the semiconductor body 10 between.This contact 11 is connected with common source line CS30.Second change-over switch that is formed by the metal oxide semitransistor has a grid in tandem selection wire SSL 28, its be connected in corresponding memory cell with last character line 27 and the contact 19 that forms by the zone of the n type in the semiconductor body 10 between.This contact 19 is connected with bit line BL 31.First and second change-over switch in this illustrative embodiments is the metal oxide semitransistor, has the gate dielectric layer of silicon dioxide in this example.

In this illustration, have six memory cells for simplicity in this tandem.In typical configuration, Sheffer stroke gate tandem can comprise 16,32 or the series connection of more a plurality of memory cell arrange.The pairing character line of these memory cells 22-27 has charge-trapping structure 9 in character line and semiconductor body 10 between the passage area.Charge-trapping structure 9 in this memory cell can be dielectric charge capturing structure, floating grid charge-trapping structure or other are suitable for using technology described herein to come the fast-flash memory body structure of sequencing.In addition, developed the form that does not connect face among the embodiment of Sheffer stroke gate flash structures, node 13-17 wherein, and comprise that optionally node 12 and 18 omits in the structure since then.

Figure 1A is the sectional view that shows existing known techniques Sheffer stroke gate (NAND) structural flash memory body, and it is to bring out FN to wear tunnel with the bias voltage synoptic diagram to carrying out sequencing with character line 24 corresponding memory cells.Bias voltage according to this place demonstration; Ground connection selection wire GSL is biased into and is approximately 0V and common source line ground connection; Make and close with the ground connection selection wire GSL 21 first corresponding change-over switches; And tandem selection wire SSL is biased into about VCC and selected bit line also is a ground connection, makes to open with the tandem selection wire SSL 28 second corresponding change-over switches.Under these conditions, the semiconductor body in the zone 33 relevant with the Sheffer stroke gate tandem is to be precharged to about 0V.This chooses character line 24 and is biased to a high voltage sequencing V-PGM of class, in certain embodiments can be up to 20 volts the order of magnitude.Do not choose character line 22,23,2527 and be biased to one through voltage V-PASS, it is also less than the voltage that can suppress not choose in this tandem the sequencing of cell than V-PGM.Consequently, electrons tunnel gets in the charge-trapping structure of selected memory cell.

Figure 1B is the sectional view that shows existing known techniques Sheffer stroke gate (NAND) structural flash memory body, and it is a bias voltage synoptic diagram of the Sheffer stroke gate tandem of sharing character line 22-27 among Figure 1A not being chosen the bit line.By finding that the ground connection selection wire GSL of all character lines is all identical with the bias voltage shown in Figure 1A with tandem selection wire SSL among the figure.Similarly, common source line 30 also is a ground connection.Yet the bit line of not choosing is biased into the class that is about VCC.So second change-over switch can be closed, it is corresponding with tandem selection wire SSL, and semiconductor body in the zone 35 and bit line BL 32 releasings of not choosing are coupled.Consequently, the semiconductor body in the zone 35 can be by being applied to the capacitive coupling oneself voltage rise that character line 22-27 voltage is produced, and it can prevent to be enough to disturb the electric field of charge-trapping structure in the memory cell of not choosing the Sheffer stroke gate tandem to form.Increasing progressively step-by-step impulse sequencing (ISSP) operation according to capacitive character oneself voltage rise so-called is that industry is known.

Fig. 2 A and Fig. 2 B show that drain two stages of self-voltage rise, hot carrier sequencing of a sequencing interval according to the embodiment of the invention choose two stage sectional views of Sheffer stroke gate (NAND) tandem, and it is to show that the memory cell series connection arranges to form the synoptic diagram that the Sheffer stroke gate tandem is carried out the self-voltage rise of drain electrode described herein, hot carrier sequencing.For n passage memory cell, hot carrier comprises electronics.For p passage memory cell, can use similar techniques to bring out hot carrier injection, wherein hot carrier comprises electric hole.Sequencing example described herein is to be that embodiment illustrates with n passage memory cell, but be called " the hot carrier injection of self-voltage rise node " also can be alternatively with p passage memory cell as embodiment.

In Fig. 2 A, show the phase one, wherein common source line 30 is a ground connection, and selected bit line 31 also is coupled to and is approximately 0V.Ground connection selection wire GSL 21 is biased into and is approximately 0V the change-over switch 42 of winning is closed, and semiconductor body is removed coupling from common source line CS 30.Tandem selection wire SSL is biased into about VCC and opens second change-over switch 43, and semiconductor body and selected bit line 31 are coupled.Receive sequencing pulse V-PGM with target memory born of the same parents 40 corresponding character lines.The target memory born of the same parents 40 contiguous character lines that are positioned at bit line 31 ends receive one or two stage switched voltage V-SW; Its sequencing in the phase one is in low-voltage when interval; The feasible pathway closure that switches memory cell 41, and as the area of isolation in the semiconductor body 50 and 51.Under the bias condition when this sequencing is interval, the zone 50 in the semiconductor body 10 is responded to virtual drain voltage Vd by self-voltage rise by capacitive couplings passes through voltage V-PASS (drain electrode end) on target character line that receives V-PGM and the character line between first change-over switch 42.Zone 51 in the semiconductor body 10 is biased into the bit line 31 that is approximately 0V and is precharged to virtual source pole tension Vs with substrate by coupling.This voltage V-PASS (source terminal) is coupled on the character line that switches between the memory cell 41 and second change-over switch 43.V-PASS (source terminal) can be and the identical voltage of V-PASS (drain electrode end), or different voltages with different, a visual application-specific or the required decision of sequencing condition.Self-voltage rise voltage class and the reference voltage class in zone 51 in zone 50 are because vague and general regional 52 isolation under this switching memory cell in the sequencing interval of this phase one.

In this example, all example Sheffer stroke gate tandems shown here, first and second change-over switch (42,43) are to utilize the field-effect transistor of memory cell series connection in the tandem therewith to implement.In the example shown in Fig. 2 A, the gate dielectric layer of this field-effect transistor is a single layer structure, and generally includes the monox or the monox of nitrogen doping.In other embodiment, the gate dielectric layer of this field-effect transistor is a single layer structure, and generally includes the monox or the monox of nitrogen doping.The field-effect transistor of change-over switch in this tandem (for example 42,43) can use the multi-layer gate dielectric layer, comprise in the tandem therewith the useful identical gate dielectric layer of charge-trapping structure.This scheme can be simplified the manufacture craft of memory cell.In embodiment so, first and second change-over switch can be turned to " memory cell " by characteristic.Having needs, can be longer than the passage length of memory cell as the passage length of the field-effect transistor of change-over switch.

The interval subordinate phase of display routineization in Fig. 2 B wherein changes switched voltage V-SW to open the switching memory cell 41 of adjacent objects memory cell 40.When conversion, be enough in target memory born of the same parents' passage, bring out hot carrier 54 between the difference between Vd and the Vs.Be enough to for hot carrier overcomes the energy barrier height corresponding to the voltage V-PGM on target memory born of the same parents' the character line, and cause bringing out hot carrier injecting programization.One programming operations can comprise that a series of sequencing described in Fig. 2 A and Fig. 2 B are interval, has staggered sequencing verification step, to reach target critical value efficiently.Also can use this technology to come in each memory cell, to store in an embodiment above a bit to carry out multistage sequencing.

Fig. 3 shows a sequential chart of choosing the interval voltage waveform of two phase sequencings of bit line in Fig. 2 A and Fig. 2 B.Between bit line setting area, tandem selection wire SSL bias voltage increases to a class that is about VCC.In between this setting area, the Vs of voltage class of the Vd of voltage class of virtual drain region 50 and virtual source region 51 all is maintained at about and is 0V.In a sequencing interval, voltage V-PGM is as the before described class that is enough to overcome for hot carrier injection energy barrier height by pulse to.In addition, in interval phase one of this sequencing, it can be called VDS the stage is set, through voltage V-PASS by pulse to the voltage that can suppress in this tandem do not choose memory cell sequencing also littler than V-PGM.In certain embodiments, this voltage V-PASS can be extreme than lower at virtual drain electrode end in virtual source.In the phase one in this sequencing interval, voltage V-SW remains on a low-voltage to close memory cell 41.In this example, virtual drain region 50 makes virtual drain voltage Vd promote by capacitive couplings oneself voltage rise to surpass Vcc class, and virtual source pole tension Vs still is maintained at about and is 0V.With after allowing for the target memory born of the same parents and source voltage VDS promote being arrived the class that can bring out hot carrier injection, begin to carry out the interval subordinate phase of this sequencing in one section time enough interval, it can be called the sequencing stage.In the subordinate phase in this sequencing interval, voltage V-SW is switched voltage by pulse to, has in this embodiment not to be higher than V-PASS.By at least one phase one in the interval of shadow region 90 representatives the time, drain pole tension VDS is maintained at and is enough to bring out hot carrier, and hot carrier injection can take place with sequencing target memory born of the same parents.After this sequencing descended interval latter stage in sequencing stage, this tandem selection wire SSL bias voltage can maintain class's a period of time of VCC at V-PASS and V-PGM, and this moment, semiconductor body can be through the discharge of bit line.

Fig. 4 is that demonstration one Sheffer stroke gate tandem is not chosen the sequential chart of bit line in the interval voltage waveform of sequencing, and this does not choose the bit line is to share the character line with selected Sheffer stroke gate tandem.In this Sheffer stroke gate tandem, do not choose the bit line; Self-voltage rise to the first class between voltage class first line on the throne setting area of semiconductor body; And in interval first and second stages oneself voltage rise of sequencing, make that the voltage of virtual drain electrode and virtual source electrode is equal or almost equal when the subordinate phase when the sequencing interval begins by character line voltage.Consequently, hot carrier can not produce choosing on the bit line of Sheffer stroke gate tandem, and this memory cell can not disturbed.

Fig. 5 A and Fig. 5 B show a bias voltage diagrammatic cross-section in two stages of not choosing the sequencing of Sheffer stroke gate tandem, and it is to share the character line with selected Sheffer stroke gate tandem under the situation of bias voltage hot carrier sequencing with lifting-node of Fig. 4 demonstration in a Sheffer stroke gate tandem.In Fig. 5 A, show the phase one, wherein common source line 30 is a ground connection, and the bit line of not choosing 32 is biased into the class that is about VCC, rather than as the bit line chosen be biased into and be about 0V.Ground connection selection wire GSL 21 is coupled to and is about 0V to close the first change-over switch 42u, semiconductor body is removed coupling from common source line CS 30.Tandem selection wire SSL 28 is coupled to and is about VCC, and it can not open the second change-over switch 43u, therefore semiconductor body is removed coupling from the bit line of not choosing 32.Receive sequencing pulse V-PGM with the pairing character line of the target memory born of the same parents 40u that does not choose.Receive a switching voltage V-SW with the character line of the target memory born of the same parents 40u bit line end adjacency of not choosing, it remains on a low-voltage in the phase one in sequencing interval, make to switch memory cell 41u as the zone in the isolation of semiconductor main body 50 and 60.Under the bias condition when interval phase one of this sequencing, the zone 50 in the semiconductor body 10 is responded to virtual drain voltage Vd by self-voltage rise by capacitive couplings passes through voltage V-PASS (drain electrode end) on target character line that receives V-PGM and the character line between the first change-over switch 42u.Do not choose in the semiconductor body 10 of bit line zone 60 also by capacitive couplings by self-voltage rise and reach one and respond through voltage V-PASS (source terminal) near the virtual source pole tension Vs of virtual drain voltage Vd.Self-voltage rise voltage class in the zone 50 and the reference voltage class in the zone 60 are close, isolate but still switch vague and general regional 61 under the memory cell 41u thus.

In Fig. 5 B, show the subordinate phase that this sequencing is interval, wherein change switched voltage V-SW and switch memory cell 41u to open, zone 50 and 60 is coupled in together to form self-voltage rise zone 62.Difference when conversion between Vd and Vs is zero, or a too low class can't bring out hot carrier in the memory cell passage of corresponding this target character line.Also be not enough in zone 63, to bring out FN corresponding to the voltage V-PGM on the character line of not choosing target memory born of the same parents 40u and wear tunnel, and make that so the not alternative line memory cell 40 of not choosing the bit line can not be disturbed.

The bias voltage class of representational sequencing and erase operation is shown in the following table.

	Sequencing	Wipe
			Do not choose the character line	6-12V	-8V
Choose the character line	10-16V	-8V
			Switch character line (subordinate phase)	4-12V	-8V
Do not choose the bit line	VCC	Suspension joint
			Choose the bit line	0V	Suspension joint
PW	0V	12V
			SSL	VCC	Suspension joint/VCC
GSL	0V	Suspension joint/VCC
			CS	0V	Suspension joint

Fig. 6 is the synoptic diagram that shows a common source polar form attitude Sheffer stroke gate memory array that uses sequencing biased operation described herein; It shows the layout of four Sheffer stroke gate tandems 101,102,103,104, and it selects transistor (as 112) to couple to BL-4 and a common source line CS 105 with separately bit line BL-1 with ground connection selection transistor (as 111) via tandem respectively.For illustrative purposes, bias voltage shown here is the target memory born of the same parents 100 of this Sheffer stroke gate tandem of sequencing 101 corresponding character line WL (i).The first change-over switch transistor 111 is coupled so that the Sheffer stroke gate tandem is removed from common source line CS 105 by the ground bias voltage on the ground connection selection wire GSL.The second change-over switch transistor 112 by tandem selection wire SSL bias voltage so that Sheffer stroke gate tandem and selected bit line BL-1 are coupled.The switching memory cell 113 of corresponding character line WL (i-1) is in abutting connection with target memory born of the same parents 100.Therefore, character line WL (i-1) receives V-SW to support this two-stage processization interval.In the interval phase one of this sequencing, the zone in the semiconductor body 120 is biased to the 0V that is about of virtual source pole tension Vs, and the zone in the semiconductor body 121 is biased to virtual drain voltage Vd by capacitive coupling.On the bit line of not choosing, zone 122,123 is by the also extremely relative high voltage of capacitive coupling.Therefore, the subordinate phase interval when this sequencing begins, and can hot carrier injection take place target memory born of the same parents 100, and other memory cells in this array can not be interfered.Be noted that and work as memory cell at the first character line WL (0), this tandem selection wire SSL can be used for applying switched voltage V-SW to switching transistor 112, allows the bit line of this Sheffer stroke gate tandem to be operating as virtual source electrode.

Fig. 7 shows the synoptic diagram that uses a common source polar form attitude Sheffer stroke gate memory array of sequencing biased operation described herein according to an alternate embodiment.It shows that switching transistor 113 is adjacent to the bias condition of this tandem target memory born of the same parents 100 common source sides.Therefore, Fig. 7 is a circuit diagram that shows four Sheffer stroke gate tandem 101,102,103,104 layouts, and it selects transistor to couple to BL-4 and a common source line CS105 with separately bit line BL-1 with ground connection selection transistor via tandem respectively.Bias voltage shown here is the target memory born of the same parents 100 of this Sheffer stroke gate tandem of sequencing 101 corresponding character line WL (i).The first change-over switch transistor 111 by the VCC bias voltage on the ground connection selection wire GSL so that Sheffer stroke gate tandem and common source line CS 105 are coupled.The second change-over switch transistor 112 is coupled so that this Sheffer stroke gate tandem and selected bit line BL-1 are removed by tandem selection wire SSL and the VCC bias voltage of choosing bit line BL-1.The switching memory cell 113 of corresponding character line WL (i+1) is in abutting connection with target memory born of the same parents 100.Therefore, character line WL (i+1) receives V-SW to support this two-stage processization interval.In the interval phase one of this sequencing, the zone in the semiconductor body 150 is biased to virtual drain voltage Vd by capacitive coupling.Zone 151 in the semiconductor body is biased to virtual source pole tension Vs via common source line CS.On the bit line of not choosing, itself and 0V couple, and zone 152 is biased to ground and regional 153 also is biased to ground via common source line CS to BL-4 via the bit line BL-2 that does not choose.Therefore, the subordinate phase interval when this sequencing begins, and can hot carrier injection take place target memory born of the same parents 100, and other memory cells in this array can not be interfered.

Fig. 6 and Fig. 7 have shown the possibility of two bias voltage directions, the top and the bottom of tandem since then in single array configuration.So can obtain to guarantee semiconductor body as virtual drain electrode partly have enough electric capacity with keep reasonable sequencing speed the advantage of hot carrier injection electric current of palpus.For example, this programmed controller can be used for this array of bias voltage and makes this target memory born of the same parents' virtual drain side have the half character line in this tandem at least.

Fig. 8 shows the layout that is arranged to seven Sheffer stroke gate tandem 201-207 in the virtual ground Sheffer stroke gate framework.In the described herein virtual ground Sheffer stroke gate framework, the conduct simultaneously of bit line reaches the reference line that couples with reference voltage source with the bit line that sensing amplifier couples, and is the line position that depends on institute's access.This Sheffer stroke gate tandem is by top bit line options transistor BLT and end bit line options transistor BLB and couple to BL-8 with one group of corresponding bit line BL-1.For the purpose of illustrating, the bias voltage shown in the figure is the bias voltage with target memory born of the same parents 300 sequencing corresponding with character line WL (i) in the Sheffer stroke gate tandem 204.So that Sheffer stroke gate tandem 204 is coupled with BL-5, BL-5 is a ground connection to the first change-over switch transistor 301 by the VCC on the end bit line options transistor BLB.The second change-over switch transistor 302 is coupled so that Sheffer stroke gate tandem 204 is removed from BL-4 by the VCC on the bit line options transistor BLT of top, and BL-4 is biased into VCC.All bit line BL-1 in Sheffer stroke gate tandem 204 left sides all are biased to VCC to BL-3.All bit line BL-6 on Sheffer stroke gate tandem 204 right sides all are biased to ground to BL-8.The switching memory cell 304 of corresponding character line WL (i+1) is in abutting connection with target memory born of the same parents 300.Therefore, character line WL (i+1) receives V-SW to support this two-stage processization interval.In the interval phase one of this sequencing; Zone in the semiconductor body 311 is biased to the 0V that is about of virtual source pole tension Vs; And the zone in the semiconductor body 310 is biased to virtual drain voltage Vd by capacitive coupling; Therefore be the interval subordinate phase setting of sequencing, wherein hot carrier injection can cause target memory born of the same parents 300 by sequencing.On the bit line of not choosing on the right side, zone 312 and 313 be biased to by bit line BL-5 to BL-8 to avoid the memory cell on this tandem to be interfered.On the bit line of not choosing in the left side, zone 314 with 315 by capacitive coupling by self-voltage rise extremely relative high voltage be interfered to avoid the memory cell on this tandem.Therefore, the subordinate phase interval when this sequencing begins, and can hot carrier injection take place target memory born of the same parents 300, and other memory cells in this array can not be interfered.

Fig. 9 shows the adjustment bias voltage synoptic diagram that is arranged to virtual ground Sheffer stroke gate framework of similar Fig. 8, and wherein switching transistor is at opposite side.This Sheffer stroke gate tandem is by top bit line options transistor BLT and end bit line options transistor BLB and couple to BL-8 with one group of corresponding bit line BL-1.For the purpose of illustrating, the bias voltage shown in the figure is the bias voltage with target memory born of the same parents 320 sequencing corresponding with character line WL (i+1) in the Sheffer stroke gate tandem 204.The first change-over switch transistor 321 is coupled so that Sheffer stroke gate tandem 204 is removed from BL-5 by the VCC on the end bit line options transistor BLB, and BL-5 is biased into VCC.So that Sheffer stroke gate tandem 204 is coupled with BL-4, BL-4 is a ground connection to the second change-over switch transistor 322 by the VCC on the bit line options transistor BLT of top.All bit line BL-1 in Sheffer stroke gate tandem 204 left sides all are biased to ground to BL-3.All bit line BL-6 on Sheffer stroke gate tandem 204 right sides all are biased to VCC to BL-8.The switching memory cell 324 of corresponding character line WL (i) is in abutting connection with target memory born of the same parents 320.Therefore, character line WL (i) receives V-SW to support this two-stage processization interval.In the interval phase one of this sequencing; Zone in the semiconductor body 330 is biased to the 0V that is about of virtual source pole tension Vs; And the zone in the semiconductor body 331 is biased to virtual drain voltage Vd by capacitive coupling; Therefore be the interval subordinate phase setting of sequencing, wherein hot carrier injection can cause target memory born of the same parents 320 by sequencing.On the bit line of not choosing on the right side, zone 332 with 333 by capacitive coupling by self-voltage rise extremely relative high voltage be interfered to avoid the memory cell on this tandem.And on the bit line of not choosing in the left side, zone 334 and 335 be biased to by bit line BL-1 to BL-4 to avoid the memory cell on this tandem to be interfered.Therefore, the subordinate phase interval when this sequencing begins, and can hot carrier injection take place target memory born of the same parents 320, and other memory cells in this array can not be interfered.

Figure 10 shows the bias condition of the Sheffer stroke gate array of similar Fig. 6 and Fig. 7, and wherein two switch memory cell the 155, the 156th, in this tandem common source CS side and target memory born of the same parents 157 adjacency.Figure 10 shows the layout of four Sheffer stroke gate tandems 101,102,103,104, and it selects transistor to couple to BL-4 and a common source line CS 105 with separately bit line BL-1 with ground connection selection transistor via tandem respectively.Bias voltage shown here is the target memory born of the same parents 157 of this Sheffer stroke gate tandem of sequencing 101 corresponding character line WL (i+1).The first change-over switch transistor 111 is coupled so that the Sheffer stroke gate tandem is removed from common source line CS 105 by the ground bias voltage on the ground connection selection wire GSL.The second change-over switch transistor 112 is biased into VCC so that Sheffer stroke gate tandem and selected bit line BL-1 are coupled by tandem selection wire SSL, and it is to be biased into ground.The switching memory cell 155 of corresponding character line WL (i-1) and the switching memory cell 156 of corresponding character line WL (i) are in abutting connection with target memory born of the same parents 157.Therefore, it is interval to support this two-stage processization that character line WL (i-1) and WL (i) receive V-SW, and it can be identical or according to the application of specific embodiment and different.In the interval phase one of this sequencing, the zone in the semiconductor body 160 is biased to the 0V that is about of virtual source pole tension Vs, and the zone in the semiconductor body 161 is biased to virtual drain voltage Vd by capacitive coupling.On the bit line of not choosing, be biased into VCC, therefore the Sheffer stroke gate tandem of correspondence removed coupling from these bit lines, zone 162,163 is by the also extremely relative high voltage of capacitive coupling.Therefore, the subordinate phase interval when this sequencing begins, and can hot carrier injection take place target memory born of the same parents 157, and other memory cells in this array can not be interfered.Use two to switch memory cells 155,156 and isolate the leakage current that virtual drain region 161 and virtual source region 160 can suppress to be included in the subcritical leakage in the interval stage that is provided with of sequencing in the interval phase one of this sequencing.

Figure 11 shows the sectional view of the Sheffer stroke gate tandem of similar Fig. 2 A and Fig. 2 B.The bias voltage that in Figure 11, shows the phase one, wherein target memory born of the same parents 180 are the tail ends near tandem, for example near ground connection selection wire GSL.With this understanding, the phase one common source line 30 interval in sequencing is ground connection, and selected bit line 31 also is coupled to and is approximately 0V.Ground connection selection wire GSL 21 is biased into and is approximately 0V the change-over switch 42 of winning is closed, and semiconductor body is removed coupling from common source line CS 30.Tandem selection wire SSL 28 is biased into about VCC and opens second change-over switch 43, and semiconductor body and selected bit line 31 are coupled.Receive sequencing pulse V-PGM with target memory born of the same parents 180 corresponding character lines.The target memory born of the same parents 180 contiguous character lines that are positioned at bit line 31 ends receive one and switch voltage V-SW to set up switching memory cell 181.Switched voltage V-SW is in low-voltage when the sequencing of phase one is interval, makes to switch the usefulness of memory cell 181 as the zone in the isolation of semiconductor main body 183 and 184.Be in this bias condition in the time of between a sequencing setting area, the zone 184 in the semiconductor body 10 is responded to virtual drain voltage Vd by self-voltage rise by capacitive couplings passes through voltage V-PASS (drain electrode end) on target character line that receives V-PGM and the character line between the GSL line.Zone 183 in the semiconductor body 10 is precharged to virtual source pole tension Vs by coupling bit line 31 with substrate.This voltage V-PASS (source terminal) is coupled on the character line between the switching character line of memory cell 181 and second change-over switch 43.Self-voltage rise voltage class and the reference voltage class in zone 183 in zone 184 are because the vague and general zone under this switching memory cell 181 isolates.Yet in the case, virtual drain region 184 is little, and therefore can have relatively little electric capacity.The hot carrier that little electric capacity can cause the zone 90 among Fig. 3 to produce lesser amt, and reduce the hot carrier injection quantity that in single heavy showing interval, can reach.

Therefore, as shown in Figure 12, its for use one or more false character lines (401,402) between a plurality of memory cells of GSL and this Sheffer stroke gate tandem to improve an alternate embodiment of minimum sequencing efficient.Figure 12 shows the sectional view of the Sheffer stroke gate tandem of similar Figure 11.The bias voltage that in Figure 12, shows the phase one, wherein target memory born of the same parents 480 are the tail ends near tandem, for example near ground connection selection wire GSL.With this understanding, the phase one common source line 30 interval in sequencing is ground connection, and selected bit line 31 also is coupled to and is approximately 0V.Ground connection selection wire GSL 21 is biased into and is approximately 0V the change-over switch 42 of winning is closed, and semiconductor body is removed coupling from common source line CS 30.Tandem selection wire SSL is biased into about VCC and opens second change-over switch 43, and semiconductor body and selected bit line 31 are coupled.Receive sequencing pulse V-PGM with target memory born of the same parents 480 corresponding character lines.The target memory born of the same parents 480 contiguous character lines that are positioned at the bit line end receive one and switch voltage V-SW to set up memory cell 481 as switching memory cell.Switched voltage V-SW is in low-voltage when the sequencing of phase one is interval, makes and switches memory cell 481 as the zone in the isolation of semiconductor main body 483 and 484.When the phase one sequencing is interval is in this bias condition, and the zone 484 in the semiconductor body 10 is responded to virtual drain voltage Vd by self-voltage rise by capacitive couplings passes through voltage V-PASS (drain electrode end) on the target character line that receives V-PGM and character line 482 between the GSL line and false character line 401,402.Zone 483 in the semiconductor body 10 is precharged to virtual source pole tension Vs by coupling bit line 31 with substrate.This voltage V-PASS (source terminal) is coupled on the character line between the switching character line of memory cell 481 and second change-over switch 43.Voltage V-PASS (source terminal) can be and voltage V-PASS (drain electrode end), or different voltages with different, looks closely an application-specific or the sequencing condition is required.Self-voltage rise voltage class and the reference voltage class in zone 483 in zone 484 are because the vague and general zone under this switching memory cell 181 isolates.As shown in the figure, in the case, virtual drain region 484 guarantees to comprise at least two memory cells under the false character line 401,402, and therefore can have an electric capacity that brings out the injection of plurality calorimetric carrier when being enough to the reprogramming interval.Must be noted that the pseudomemory born of the same parents can be used as the switching memory cell of the memory cell of the corresponding character line 482 of sequencing when applying the common source line end as the pattern of virtual source electrode.

Figure 13 shows that one is similar to simplified topology synoptic diagram with false character line DWL1, DWL2 in abutting connection with a Sheffer stroke gate array of GSL line shown in Figure 12, wherein shows character line and source/drain electrode tandem.Therefore, source/drain electrode tandem 500-503 vertically extends along the page.Horizontal wire is on source/drain electrode tandem 500-503.This horizontal wire comprises that SSL line, character line WL0 are to WL (n-1) and false character line DWL1, DWL2.In addition, horizontal wire also comprises ground connection selection wire GSL and common source line CS.

Figure 14 show one be similar to shown in Figure 12 have false character line in the opposite side of array and with the simplified topology synoptic diagram of a Sheffer stroke gate array of SSL line adjacency, wherein show character line and source/drain electrode tandem.Therefore, source/drain electrode tandem 500-503 vertically extends along the page.Horizontal wire is on source/drain electrode tandem 500-503.This horizontal wire comprises that SSL line, false character line DWL1, DWL2 and character line WL0 are to WL (n-1).In addition, horizontal wire also comprises ground connection selection wire GSL and common source line CS.

Figure 15 shows a simplified topology synoptic diagram that is similar to a Sheffer stroke gate array that does not have false character line shown in Figure 12, wherein shows character line and source/drain electrode tandem.Yet, the character line logically be arranged in one group of top character line TWL0 at the bottom of TWL (n-1) (only showing among the figure that TWL (0) is to TWL (4)) and one group character line BWL0 among BTWL (m-1) (only showing among the figure that BWL (M-5) is to TWL (M-1)).Therefore, in target memory born of the same parents fell within top character line, this programming operations was arranged to make virtual drain region to comprise that all are positioned at the semiconductor body zone under the end character line.In the case, can improve the sequencing performance of hot carrier injection.

Figure 16 shows a simplified topology synoptic diagram that is similar to the Sheffer stroke gate array with character line and GSL line adjacency and false character line and SSL line adjacency shown in Figure 12, wherein shows character line and source/drain electrode tandem.Therefore, source/drain electrode tandem 500-503 vertically extends along the page.Horizontal wire is on source/drain electrode tandem 500-503.This horizontal wire comprises that SSL line, top character line TWL1 and TWL2, character line WL0 are to WL (n-1) and end character line BWL1 and BWL2.In addition, horizontal wire also comprises ground connection selection wire GSL and common source line CS.

Figure 17 and Figure 18 display routineization are interval to be used to bring out the alternative scheduling synoptic diagram of the hot carrier injection of lifting node described herein.These comprise in proper order when switched voltage V-SW is low level at least a portion time of interval phase one of this sequencing and are biased into a high levle opening second change-over switch by tandem selection wire SSL, and when switched voltage V-SW is high levle at least a portion time of the subordinate phase in this sequencing interval by tandem selection wire SSL is switched to a low level to close second change-over switch.As shown in Figure 17, interval in a sequencing, selected bit line 31, ground connection selection wire GSL and common source line CS are maintained at earthing potential, and the bit line of not choosing is biased to about VCC.In the time 600 of the interval beginning of this sequencing, tandem selection wire SSL be biased into about VCC and with semiconductor body and couple.Put 610 the blink after tandem selection wire SSL switches to VCC; This target character line receives sequencing pulse V-PGM current potential; The contiguous character line that switches memory cell receives one and switches voltage V-SW; It is can close this to switch memory cell in low-voltage, and receives voltage V-PASS along other character lines of this Sheffer stroke gate tandem.So as virtual source electrode of operated by rotary motion shown in Fig. 2 A and virtual drain region.According to the program among Figure 17, tandem selection wire SSL switches in times 602 and gets back to earth potential rather than continue to maintain VCC as Fig. 3 in the whole procedure interval.This switched voltage V-SW switches to high levle in the time 603, its can with time 602 simultaneously.This sequencing interval finished together to get back to ground when sequencing current potential and other signals in times 604.

As shown in Figure 18, can switch at tandem selection wire SSL and get back to earthy time 602 and switched voltage V-SW and switch between time 605 of high levle and add a time delay 606.As before, interval in a sequencing, selected bit line, ground connection selection wire GSL and common source line CS are maintained at earthing potential, and the bit line of not choosing is biased to about VCC.In the time 600 of the interval beginning of this sequencing, tandem selection wire SSL be biased into about VCC and with semiconductor body and couple.Put 610 the blink after tandem selection wire SSL switches to VCC, and this target character line receives sequencing pulse V-PGM current potential, and receives voltage V-PASS along other character lines of this Sheffer stroke gate tandem.In this order, after earthy one period time delay 606 was got back in tandem selection wire SSL switching, switched voltage V-SW switched to high levle in the time 605.This sequencing interval finished together to get back to ground when sequencing current potential and other signals in times 604.These can be operated the changeover program that ground connection selection wire GSL and tandem selection wire SSL close under low-power.

Figure 19 shows the rough schematic view of integrated circuit, and it uses the Sheffer stroke gate fast flash memory bank of the virtual drain electrode of self-voltage rise described herein, hot carrier injecting programization.This integrated circuit 810 comprises a use charge-trapping or a memory array 812 of floating grid memory cell, and it is formed at for example, on the semiconductor substrate.Character line (row) and tandem select demoder (comprising suitable driver) 814 and many character lines 816, tandem selection wire and ground connection selection wires to couple and electrically link up, and arrange along the column direction of memory array 812.Bit line (OK) demoder and driver 818 are electrically linked up with many bit lines 820 and are arranged along the line direction of memory array 812, read data or write data extremely wherein with the memory cell (not shown) from array 812.Address is to offer character line and tandem selection demoder 814 and bit line demoder 818 by bus-bar 822.Sensing amplifier in the square 824 and data input structure couple via data bus 826 and bit line demoder 818.Data offers data input line 828 by the I/O port on the integrated circuit 810, perhaps by the source of information of integrated circuit 810 other inner/outer, inputs to the data input structure in the square 824.Other circuit 830 are to be contained within the integrated circuit 810, and are for example general with purpose processor or specific purposes application circuit, or the module combination is to provide the SoC of being supported by array function.Data, is provided to integrated circuit 810 via data output line 832 by the sensing amplifier in the square 824, or provides to other End of Data of integrated circuit 810 inner/outer.

Employed in the present embodiment controller 834; Used bias voltage adjustment state machine 836; Controlled the application of bias voltage adjustment supply voltage and current source; For example read, sequencing, wipe, erase-verifying and sequencing confirm that voltage or electric current put on character line or the bit line, and use the access control flow process to control the operation of character line/source electrode line.This controller is also used switching sequence and is brought out the hot carrier sequencing of lifting-node described herein.In alternate embodiment, this controller 834 has comprised general purpose processor, and it can make in same integrated circuit, the operation of control device to carry out a computer program.In another embodiment, this controller 834 is to be combined by specific purposes logical circuit and general purpose processor.

The present invention provides a kind of new method for programming of Sheffer stroke gate fast flash memory bank, and it can press down the process interference because of low operating voltage.New sequencing according to the hot carrier injection of using the lifting node potential to reach can be used than low operating voltage.Because than the result of low operating voltage, the driving circuit in this integrated circuit can only use a kind of metal-oxide half field effect transistor technology to execute work, and does not need extra high voltage metal-oxide half field effect transistor technology.

Channel hot electron injection operation than traditional is compared, and this bit line voltage need not overcome injection of hot electrons energy barrier height.Therefore, bit line voltage can be VCC or the lower voltage of other more traditional channel hot electron injection (CHE) sequencing voltage.In addition, the bit line can be when channel hot electron not be injected consumed dc current.So the method for programming that this kind is new should be reached low power consumption.

Furthermore, low sequencing and the Vpass voltage required than traditional F N programming operations cause reducing the dielectric voltage between the character line, and therefore reduce because dwindle the dielectric crash issue between the character line that is produced between the distance between the character line.

The above; It only is preferred embodiment of the present invention; Be not that the present invention is done any pro forma restriction; Though the present invention discloses as above with preferred embodiment; Yet be not in order to limit the present invention; Anyly be familiar with the professional and technical personnel; In not breaking away from technical scheme scope of the present invention; When the method that can utilize above-mentioned announcement and technology contents are made a little change or be modified to the equivalent embodiment of equivalent variations; In every case be the content that does not break away from technical scheme of the present invention;, all still belong in the scope of technical scheme of the present invention any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.

Claims

1. memory cell is characterized in that comprising:

A plurality of memory cells are series in the semiconductor main body,

Many character lines, the character line in these many character lines couples with memory cell in these corresponding a plurality of memory cells; And

Control circuit couples with these many bit lines, with the following step one in these corresponding a plurality of memory cells of one selected character line is chosen memory cell and carries out sequencing:

When a sequencing is interval, apply a character line that passes through one first side of voltage to this selected character line;

By capacitive couplings with the self-voltage rise voltage of the self-voltage rise in one first semiconductor body zone;

When this sequencing is interval, apply a sequencing voltage to this selected character line;

When this sequencing is interval, be biased in one second semiconductor body zone to a reference voltage of one second side of this selected character line; And

Apply one and switch voltage to the one character line adjacent with this selected character line; This switched voltage has a phase one and a subordinate phase when this sequencing is interval; With will be corresponding in this phase one with this selected character line this choose memory cell and this reference voltage and isolate, and this is chosen memory cell and this reference voltage couples in this subordinate phase.

2. memory cell according to claim 1 is characterized in that wherein corresponding with this selected character line this choose memory cell and when this subordinate phase, be biased to this switched voltage to carry out the hot carrier sequencing of passage.

3. memory cell according to claim 1 is characterized in that wherein said switched voltage is less than this sequencing voltage when this subordinate phase.

4. memory cell according to claim 1 is characterized in that wherein said a plurality of memory cell is arranged to a Sheffer stroke gate tandem.

5. memory cell according to claim 1; It is characterized in that also comprising that one first change-over switch is between one first side of a bit line and these a plurality of memory cells; Reach one second change-over switch between one second side of a reference line and these a plurality of memory cells, and wherein this control circuit opens this first change-over switch and cuts out this second change-over switch in this sequencing interval.

6. memory cell according to claim 5; It is characterized in that also comprising that more than second memory cell and these many character lines couple; And wherein this control circuit applies one second corresponding bit line of more than second memory cell of a voltage to one and this will isolating with semiconductor body region in this corresponding more than second memory cell of this second side of this selected character line, and applies one and produce hot carrier with semiconductor body region to a voltage at this more than second memory cell place of self- voltage rise with the memory cell in this more than second memory cell that suppresses to couple with this selected character line in the corresponding character line of this second side of this selected character line by voltage.

7. memory cell according to claim 5; It is characterized in that also comprising extra memory cell is series in this semiconductor body zone and an extra character line with these a plurality of memory cells; And this extra memory cell is placed between these a plurality of memory cells and this second change-over switch; And pass through voltage in this extra character line when this control circuit applies one in this sequencing interval, therefore the capacitance in this semiconductor body zone of this first side of this selected character line improves.

8. memory cell according to claim 5; It is characterized in that wherein said control circuit opens this second change-over switch in this phase one of the part of this switched voltage, and close this second change-over switch in this subordinate phase of the part of this switched voltage.

9. memory cell according to claim 1; It is characterized in that also comprising that one first change-over switch is between one first side of a bit line and these a plurality of memory cells; Reach one second change-over switch between one second side of a reference line and these a plurality of memory cells, and wherein this control circuit cuts out this first change-over switch and opens this second change-over switch in this sequencing interval.

10. memory cell according to claim 9; It is characterized in that also comprising that more than second memory cell and these many character lines and one second bit line couple; And the one first semiconductor body zone of this control circuit in interval this second bit line of bias voltage of this sequencing makes this more than second memory cell in this first side of this selected character line wherein, and one second semiconductor body zone in this more than second memory cell of this second side of this selected character line is biased to a reference voltage to suppress the generation of hot carrier.

11. memory cell according to claim 9; It is characterized in that also comprising extra memory cell is series in this semiconductor body zone and an extra character line with these a plurality of memory cells; And this extra memory cell is placed between these a plurality of memory cells and this first change-over switch; And pass through voltage in this extra character line when this control circuit applies one in this sequencing interval, therefore the capacitance in this semiconductor body zone of this first side of this selected character line improves.

12. memory cell according to claim 1 is characterized in that wherein said control circuit applies one and switches voltage bar character line at the most when this sequencing is interval.

13. memory cell according to claim 1; It is characterized in that wherein said many character lines comprise the end of first group of character line near these a plurality of memory cells; And the other end of second group of close these a plurality of memory cell of character line; And it is at this first group or second group that this control circuit determines this to choose the character line, and distributes this this first end of choosing the character line for comprising this first group or second group.

14. memory cell according to claim 1; These a plurality of memory cells that it is characterized in that wherein being series in the semiconductor main body are between first and second switching transistor, and these many character lines comprise that one first tandem selection wire and one second tandem selection wire couple with this first and second switching transistor respectively.

15. a memory cell is characterized in that comprising:

One Sheffer stroke gate tandem comprises that a plurality of memory cells are series in the semiconductor main body;

Stop that the carrier of choosing between the one second semiconductor body zone of one second side of memory cell between this of one first semiconductor body zone and this Sheffer stroke gate tandem that this of this Sheffer stroke gate tandem chosen one first side of memory cell is mobile;

By capacitive couplings with the self-voltage rise voltage of this first semiconductor body self-voltage rise in zone;

This second semiconductor body zone is biased into a reference voltage;

Apply greater than a sequencing current potential of a hot carrier injection energy barrier and choose memory cell to this; And

The activation carrier is chosen memory cell to cause the generation of hot carrier from this second semiconductor body zone flows to this.

16. hot carrier injecting method is remembered in choosing of a Sheffer stroke gate fast flash memory bank, it is characterized in that it may further comprise the steps:

This second semiconductor body zone is biased into a reference voltage;

17. hot carrier injecting method is remembered in choosing of Sheffer stroke gate fast flash memory bank according to claim 16; It is characterized in that comprising that adjacent this that applies in two stage switched voltages to this Sheffer stroke gate tandem choose a memory cell of memory cell; Comprise that a phase one closes this memory cell and stop to implement this, and a subordinate phase is opened this memory cell to implement this activation.

18. hot carrier injecting method is remembered in choosing of Sheffer stroke gate fast flash memory bank according to claim 16; It is characterized in that this Sheffer stroke gate tandem in the wherein said Sheffer stroke gate array comprises that one first change-over switch is between one first side and a bit line or a reference line of this Sheffer stroke gate tandem; Reach one second change-over switch between one second side and this reference line or bit line of these a plurality of memory cells, and wherein should oneself's voltage rise comprise:

Close one comprise in this Sheffer stroke gate tandem of choosing memory cell this first change-over switch with this first semiconductor body zone isolation and apply one through voltage in choosing the character line that this first side in the Sheffer stroke gate tandem of memory cell couples with this, and open this second change-over switch and apply a reference voltage to this second semiconductor body zone via this second change-over switch.

19. Sheffer stroke gate fast flash memory bank according to claim 18 choose the hot carrier injecting method of memory, it is characterized in that comprising and close this first and second change-over switch of not choosing in the Sheffer stroke gate tandem.

20. the method for choosing the hot carrier injection of memory cell in the Sheffer stroke gate tandem of bringing out a Sheffer stroke gate array according to claim 18 is characterized in that comprising that unlatching do not choose this first and second change-over switch in the Sheffer stroke gate tandem.

21. hot carrier injecting method is remembered in choosing of NAND gate fast flash memory bank according to claim 16; This NAND gate tandem that it is characterized in that wherein said array comprises one first group M memory cell and one second group N memory cell; And if this to choose memory cell be in this M of first group memory cell; Then this NAND gate tandem of bias voltage makes this first semiconductor body zone comprise this N of second group memory cell at least; And if this to choose memory cell be in this N of second group memory cell, then this NAND gate tandem of bias voltage makes this first semiconductor body zone comprise this M of first group memory cell at least.