CN102339769A - Temporary semiconductor structure bonding methods and related bonded semiconductor structures - Google Patents
Temporary semiconductor structure bonding methods and related bonded semiconductor structures Download PDFInfo
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- CN102339769A CN102339769A CN201110201962XA CN201110201962A CN102339769A CN 102339769 A CN102339769 A CN 102339769A CN 201110201962X A CN201110201962X A CN 201110201962XA CN 201110201962 A CN201110201962 A CN 201110201962A CN 102339769 A CN102339769 A CN 102339769A
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Abstract
The invention relates to temporary semiconductor structure bonding methods and related bonded semiconductor structures. Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods.
Description
Technical field
Present invention relates in general to the intermediate structure of interim semiconductor die useful in forming the 3 D semiconductor structure and/or method of wafer bonding, the interim semiconductor die of use and/or method of wafer bonding formation and semiconductor die that comprises ion implanted region and/or the wafer that in interim semiconductor wafer bonding method, uses.
Background technology
The three-dimensional of two or more semiconductor structures (3D) is integrated can to produce multiple benefit to microelectronic applications.For example, to integrated electrical property that can be improved of the 3D of micromodule and power consumption, reduce the area of device overlay area simultaneously.For example referring to " The Handbook of 3D Integration, " Wiley-VCH (2008) of people such as P.Garrou.
The 3D of semiconductor structure is integrated can be through being attached to semiconductor die one or more other semiconductor die (promptly; Nude film is to nude film (D2D)), semiconductor die is attached to one or more semiconductor wafer (promptly; Nude film is to wafer (D2W)) and semiconductor wafer is attached to one or more other semiconductor wafer (that is wafer to wafer (W2W)) or their combination carries out.
Developed a plurality of processing steps with the integrated semiconductor structure of the convenient 3D of formation, these processing steps for example comprise the electrical connection of independent semiconductor structure, with one or more semiconductor structure thinning and aligning and the bonding etc. of semiconductor structure separately.Specifically, maybe be because a plurality of former thereby to comprising that one or more semiconductor structure in the integrated semiconductor structure of 3D carries out thinning, these reasons for example comprise to be improved heat radiation and reduces resistance.But; The benefit that can produce through one or more semiconductor structure thinning that will constitute the integrated semiconductor structure of 3D also possibly introduced the complicated of technology; For example; Semiconductor structure maybe be owing to attenuation becomes frangible, and thereby possibly during using the processing that has device and material now, be easy to receive fracture, breaks or the influence of other infringements.
A solution that proposes to this problem is that the semiconductor structure such as semiconductor wafer is bonded to the reinforcement substrate like another wafer (for example, bearing wafer), during the processing (for example, thinning) of semiconductor wafer, mechanical strength to be provided.Semiconductor wafer is bonded to the technology of strengthening substrate usually is called as " wafer bonding ".After process semiconductor wafers, strengthen substrate and can separate with semiconductor.
For example, use adhesive material to join semiconductor wafer to the reinforcement substrate temporarily.Adhesive material born during the processing of semiconductor wafer with semiconductor wafer with strengthen the substrate relevant power that keeps together.In addition, adhesive material with strengthen substrate and can serve as mechanical support, being that semiconductor wafer provides structural stability during the processing of semiconductor wafer.Used such as the amorphous polymer of many spin coatings of polyimides, benzocyclobutene (BCB),
and photoresist adhesive material as wafer bonding.
But, under the temperature that improves, the adhesive material potentially unstable, this can limit can carry out the temperature that semiconductor device is made.In addition, at elevated temperatures, can discharge solvent or solvent vapo(u)r from these adhesive materials.This technology usually is called as " degasification ".Degasification can cause in adhesive material, forming bubble or space.Such bubble or space can cause semiconductor wafer and strengthen the inhomogeneous joint between the substrate, and can damage the integrality of joint.After semiconductor wafer processing, use chemistry to remove technology (for example, in solvent, dissolving) and come to remove fully adhesive material.It possibly be consuming time that chemistry is removed technology, and harmful to semiconductor device and the IC-components that on semiconductor wafer, forms.Thereby if use adhesive bond in when semiconductor wafer being joined to the reinforcement substrate temporarily, then adhesive bond possibly be problematic.
During handling,, semiconductor wafer may further comprise the steps: use so-called " directly " wafer bonding technology, together two semiconductor chip Direct Bonding for providing the another kind of method of supporting.Directly wafer bonding technology is used to form semiconductor-on-insulator (SeOI) structure (for example, silicon-on-insulator (SOI) structure) that the manufacturing that receives the integrated senior IC of three-dimensional (3D) device is paid close attention to routinely.In the direct wafer bonding technology of routine, can at least one wafer, form surface oxide layer.Then, surface oxide layer is bonded to silicon materials or another kind of oxide material on another wafer surface.For example, the surface of the oxide material on the semiconductor wafer can contact with the surface of strengthening substrate, and these two structures can be bonded together through atom and/or molecule adhesion.In order to realize two bondings between the semiconductor wafer, semiconductor wafer should have the low surface roughness that conforms to surface chemical property (that is, hydrophily and hydrophobicity), and should not have dust and other fragments at least substantially.
Summary of the invention
In some embodiments, the disclosure comprises the method for making semiconductor structure.On first substrate, form first semiconductor structure of at least a portion of the integrated circuit that comprises.Ion is injected in the bearing wafer in said bearing wafer, to form atenuator region.Said bearing wafer is bonded directly to first side of said first semiconductor structure.When said bearing wafer is attached to said first semiconductor processes, handle said first semiconductor structure, said bearing wafer is used to operate said first semiconductor structure.To comprise that second semiconductor structure of at least a portion of integrated circuit is bonded directly to second side of said first semiconductor structure, said first side by the said bearing wafer of Direct Bonding of said second side and said first semiconductor structure is opposite.Said atenuator region in the said bearing wafer will separate from the material layer of the said bearing wafer remainder with said bearing wafer.
The present invention also comprises other execution mode of the method for making semiconductor structure.Ion is injected first semiconductor structure to form atenuator region at said first semiconductor structure; And the surface of said first semiconductor structure is bonded directly to the surface of said second semiconductor structure, comprises the semiconductor structure of the bonding of said first semiconductor structure and said second semiconductor structure with formation.Utilize said first semiconductor structure to operate the semiconductor structure of said bonding, remove the part of said second semiconductor structure simultaneously and expose at least one conductive structure that extends through said second semiconductor structure at least in part.Said at least one conductive structure that passes said second semiconductor structure and expose is aimed at at least one conductive structure of the 3rd semiconductor structure.Semiconductor structure and the heating of said the 3rd semiconductor structure with said bonding; And, said at least one conductive structure that passes said second semiconductor structure and expose is bonded directly to said at least one conductive structure of said the 3rd semiconductor structure in response to heating to said bonding semiconductor structure and said the 3rd semiconductor structure.In response to heating, can also cut apart first semiconductor structure along said atenuator region and also the part of said first semiconductor structure stayed on said second semiconductor structure said bonding semiconductor structure and said the 3rd semiconductor structure.
Other execution mode of the present invention is included in the semiconductor structure of the bonding that forms during the aforesaid manufacturing semiconductor structure.For example, the semiconductor structure of the bonding carrying nude film or the wafer that can comprise the treated semiconductor structure of a plurality of bondings and be bonded at least one the treated semiconductor structure in the treated semiconductor structure of said a plurality of bondings.Said carrying nude film or wafer can have atenuator region, and said atenuator region comprises that the surface of said at least one the treated semiconductor structure from the treated semiconductor structure that is bonded to said a plurality of bondings of said carrying nude film or wafer begins a plurality of injection ions of the mean depth between 10nm and 1000nm.
Description of drawings
Although specification is reached a conclusion to particularly point out and clearly to require to be considered to the claim of execution mode of the present invention; But when reading in conjunction with accompanying drawing; The advantage of execution mode of the present invention can be more easily definite from the description of particular example of the present invention, in the accompanying drawings:
Fig. 1 is the schematic cross section that comprises the treated semiconductor structure of wafer via interconnection;
Fig. 2 comprises that according to the method for the invention execution mode is bonded directly to the schematic cross section of the bonding semiconductor structure of the treated semiconductor structure among Fig. 1 of another semiconductor structure that comprises bearing wafer;
Fig. 3 is the schematic cross section of the bearing wafer shown in Fig. 2 before being bonded to treated semiconductor structure;
Fig. 4 is that the bonding semiconductor structure of Fig. 2 uses bearing wafer with the schematic cross section after operating treated semiconductor structure after with treated semiconductor structure thinning when utilizing bearing wafer to operate treated semiconductor structure;
Fig. 5 be the bonding semiconductor structure shown in Fig. 4 put upside down and with schematic cross section after another treated semiconductor structure is aimed at, this bonding semiconductor structure can execution mode according to the method for the invention be attached to this another treated semiconductor structure;
Fig. 6 is the schematic cross section of the bonding semiconductor structure that forms that can be bonded together through the semiconductor structure with the aligning shown in Fig. 5, and shows in the separation of back to bearing wafer that semiconductor structure is bonded together;
Fig. 7 is the schematic cross section of the 3 D semiconductor structure that can form according to the embodiment of the present invention; And
Fig. 8 be the schematic cross section of semiconductor structure and being used for illustrate method of the present invention be included in the execution mode that three-dimensional (3D) integrated technique is bonded to independent semiconductor die bigger semiconductor wafer.
Embodiment
For the comprehensive description to execution mode of the present disclosure and realization thereof is provided, following description provides the detail such as material type and treatment conditions.But those of ordinary skill in the art will understand, and execution mode of the present disclosure can be put into practice under the situation of conventional manufacturing technology not adopting these details and combine.In addition, the description that provides here is not formed for making the complete technological process of semiconductor device or system.Here only describe in detail in order to understand necessary those technological actions of execution mode of the present invention and structure.Material described herein can (for example be formed by any proper technique; Deposition or growth), such technology includes but not limited to that spin coating, roller coat (blanket coating), Bridgeman and Czochralski technology, chemical vapour deposition (CVD) (" CVD "), plasma enhanced chemical vapor deposition (" PECVD "), ald (" ALD "), plasma strengthen ALD and physical vapour deposition (PVD) (" PVD ").Although the material of describing here and illustrating can form layer, material is not limited to layer, and can form with other three-dimensional structures.
As used herein; Word " level " and " vertical " define element or structure with respect to the primary flat of wafer or substrate or the relative position on surface; Orientation independent with wafer or substrate; And word " level " and " vertical " are the orthogonal dimensions of explaining to the direction of described structure, as when describing this structure with reference to accompanying drawing shown.As used herein; Word " vertically " representes and comprises and dimension that the first type surface of substrate that illustrates or wafer is vertical substantially, and the first type surface dimension parallel substantially and that between the left and right sides of scheming, extend with substrate that illustrates or wafer represented in word " level ".As used herein, such as " on ", the preposition of " top ", " top " and D score is and the corresponding correlation word of the vertical direction of the structure of describing.
Like what use among this paper, any structure that in forming the semiconductor device process, uses is represented and comprised to term " semiconductor structure ".For example, semiconductor structure comprises nude film and wafer (for example, carrying substrates and device substrate) and comprises three-dimensional each other two or more nude films that integrate and/or the sub-assembly or the composite construction of wafer.Semiconductor structure also comprises makes semiconductor device of accomplishing and the intermediate structure that during the manufacturing of semiconductor device, forms fully.Semiconductor structure can comprise conductor material, semi-conducting material and/or non-conductive material.
Like what use among this paper, any semiconductor structure with one or more device architecture that partly forms is represented and comprised to term " treated semiconductor structure ".Treated semiconductor structure is the subclass of semiconductor structure, and all treated semiconductor structures all are semiconductor structures.
Like what use among this paper, term " semiconductor structure of bonding " is represented and is comprised having any structure that is attached at two or more semiconductor structures together.The semiconductor structure of bonding is the subclass of semiconductor structure, and the semiconductor structure of all bondings all is semiconductor structures.In addition, the semiconductor structure that comprises the bonding of the semiconductor structure that one or more is treated also is treated semiconductor structure.
Like what use among this paper; Any part of treated semiconductor structure is represented and comprised to term " device architecture "; That is, comprise or define will be on the semiconductor structure or at least a portion of the active or passive block of the semiconductor device that in semiconductor structure, forms.For example, device architecture comprises the active or passive block of integrated circuit, such as transistor, transducer, resistor, lead, conductive through hole and conduction contact pad.
Like what use among this paper; Term " wafer via interconnection (through wafer interconnect " or " TWI " represent and comprise any conductive through hole of at least a portion that extends through first semiconductor structure, and it provides structural interconnection and/or electrical interconnection with being used to stride across interface between first semiconductor structure and second semiconductor structure between first semiconductor structure and second semiconductor structure.Wafer via is interconnected in the art also with other term, such as " silicon through hole " or " abbreviation of these terms of substrate through-hole (TSV) and " wafer via " or " TWV ".TWI is usually along extending through semiconductor structure with the smooth vertical direction (for example, the edge direction parallel with the Z axle) of first type surface of the cardinal principle of semiconductor device generally.
Like what use among this paper; When using with treated semiconductor structure relatedly; The first type surface that exposes of treated semiconductor structure is represented and comprised to term " significant surface ", or will the first type surface that exposes at treated semiconductor structure in and/or above one or more device architecture of formation.
Like what use among this paper; When using with treated semiconductor structure, the first type surface that exposes of the treated semiconductor structure on the opposition side of treated semiconductor structure and significant surface semiconductor structure is represented and comprised to term " back side " relatedly.
As used herein, term " III-V type semiconductor material " is represented and is comprised mainly by from one or more element (B, Al, Ga, In and Tl) of subgroup IIIA and any material of forming from one or more element (N, P, As, Sb and Bi) of subgroup VA.
With reference to Fig. 1, show the treated semiconductor structure 100 that comprises device area 102, device area 102 can extend in the substrate 106 and extend on the surface of substrate 106 and/or above.Treated semiconductor structure 100 comprises the significant surface 104 and the opposite back side 108.Significant surface 104 comprises the first type surface that exposes of the device area 102 of treated semiconductor structure 100, and the back side 108 comprises the first type surface that exposes of substrate 106.Substrate 106 for example can comprise the semi-conducting material such as silicon (Si), germanium (Ge), III-V semi-conducting material etc.In addition, substrate 106 can comprise the semi-conducting material of single-crystal semiconductor material or one or more epitaxial loayer on bottom substrate.In other embodiments, substrate 106 can comprise a kind of or more kinds of dielectric material, such as oxide (for example, silicon dioxide (SiO
2) or aluminium oxide (Al
2O
3)), nitride (for example, silicon nitride (Si
3N
4), boron nitride (BN) or aluminium nitride (AlN)) etc.
Owing to a plurality of reasons, possibly not hope in direct wafer bonding technology, to use have high warpage, the semiconductor chip of arc and total thickness variations.For example, during direct wafer bonding technology, high warpage, arc and total thickness variations level can cause the inhomogeneous contact between the semiconductor chip of bonding.Thermal change and division when inhomogeneous contact like this can cause molecule to adhere to during direct wafer bonding technology.In addition, because the stress that when wafer is adhered to vacuum chuck, produced, high warpage and arc value can increase the risk that semiconductor chip breaks during the device manufacturing.Therefore, the silicon wafer with low arc, warpage and total thickness variations can be used as substrate 106, thinks that wafer bonding technology provides sufficient uniformity and smooth.As non-restrictive example, substrate 106 can be have warpage less than about 30 microns (30 μ m), less than the arc of about 10 microns (10 μ m) with less than the high quality silicon wafer of the total thickness variations of about 1 micron (1 μ m).
After forming device area 102, can on the first type surface of treated semiconductor structure 100, form bonding material 118 shown in broken lines alternatively.Bonding material 118 can be formed by the material that in Direct Bonding technology, shows with the good adhesion of another kind of material.For example, bonding material 118 can comprise such as oxide (for example, silicon dioxide (SiO
2)), oxynitride (for example silicon oxynitride ((SiON)) or nitride (for example, silicon nitride (Si
3N
4) dielectric material.Bonding material 118 can have the for example thickness between about 100 nanometers (100nm) and about two microns (2 μ m).For example use chemical vapor deposition (CVD), physical vapor deposition (PVD), ald (ALD) or plasma enhanced chemical vapor deposition (PECVD), can bonding material 118 be deposited on the significant surface 104 on the device area 102.For example can be with bonding material 118 planarizations, to reduce the surface topography of bonding material 118.Can utilize a kind of or more kinds of in for example etching, grinding and the chemico-mechanical polishing to come planarization bonding material 118.
As shown in Figure 2, in the execution mode of describing with reference to Fig. 2, can put upside down the treated semiconductor structure 100 shown in Fig. 1 and it is bonded to another semiconductor structure that comprises bearing wafer 200.The first type surface of dielectric material 114 or bonding material 118 (if existence) closely contacts with the first type surface of bearing wafer 200.
In this article to as described in the substrate 106, bearing wafer 200 can comprise the wafer with low arc, warpage and total thickness variations, thinks that wafer bonding technology provides sufficient uniformity and smooth like the front.As non-restrictive example, bearing wafer 200 can be have warpage less than about 30 microns (30 μ m), less than the arc of about ten microns (10 μ m) with less than the high quality silicon wafer of the total thickness variations of about a micron (1 μ m).
With before the surface of bearing wafer 200 contacts, can carry out conventional surface cleaning process alternatively on the surface of the bonding material that makes treated semiconductor structure 100 118 to remove surface patches and to form at least one water-wetted surface.As non-limiting example, can the exposing surface of the dielectric material 114 of treated semiconductor structure 100 or bonding material 118 (if existence) and bearing wafer 200 be put into the water (H of the ratio that comprises 5: 1: 1 respectively
2O), ammonium hydroxide (NH
4OH) and hydrogen peroxide (H
2O
2) the solvent of mixture in, give the dielectric material 114 of treated semiconductor structure 100 or the exposing surface of bonding material 118 (if existence) and bearing wafer 200 with cleaning and with hydrophily.
Can also be alternatively at least one side in the exposing surface of the dielectric material 114 of treated semiconductor structure 100 or bonding material 118 (if existence) and bearing wafer 200 execution be called as the conventional cleaning of " RCA cleaning " in the art, possibly hinder organic pollution, ionic contamination and the metal pollutant of surface bond with removal.Can be before bonding in the water of deionization (DI) dielectric material 114 of the treated semiconductor structure 100 of rinsing or the surface of bonding material 118 (if existence) and bearing wafer 200 times without number, to prevent surface particles and to keep hydrophily.The technology of utilization such as thermal bonding, hot compression bonding or hot supersonic bonding can be bonded to bearing wafer 200 with the dielectric material 114 or the bonding material 118 (if existence) of treated semiconductor structure 100.
In some embodiments, treated semiconductor structure 100 can be directly bonded to bearing wafer 200, between them, does not use the adhesive material of any centre.The treated semiconductor structure 100 and the character of atom between the bearing wafer 200 or molecular linkage will depend on each side's in treated semiconductor structure 100 and the bearing wafer 200 material composition.Thereby, according to some execution modes, for example between at least one at least one in silica and silicon nitride and silicon, silica and the silicon nitride direct atom or molecular linkage are provided.
With reference to Fig. 3; Before as illustrated in fig. 2 treated semiconductor structure 100 being bonded to bearing wafer 200; Can bearing wafer 200 be manufactured and comprise the semi-conducting material 202 with transition range 204, transition range 204 is limited the injection region that is represented by dotted lines 206.Semi-conducting material 202 through ion component being injected bearing wafer 200 can form transition range 204 to form injection region 206.For example, ion component can be hydrogen ion, inert gas ion or fluorine ion.Can ion component be injected in the bearing wafer 200 and form injection region 206 with zone along ion peak concentration with bearing wafer 200.Ion injects and can in bearing wafer 200, form atenuator region, the temperature that is raise when bearing wafer 200 or when being applied in the mechanical force such as shearing, and along this atenuator region, the influence that bearing wafer 200 is ruptured easily or separates.Can adjust the ion injection parameter to prevent bearing wafer 200 206 separation or fracture (Fig. 2) along the injection region during treated semiconductor structure 100 is bonded to bearing wafer 200.This make it possible to as will as described in during the processing of later phases, bearing wafer 200 is divided into two independent parts.
As non-restrictive example, ion component can comprise a kind of or more kinds of in hydrogen ion, helium ion or the boron ion.Can be according to about 10
16Ion/cm
2With 2 * 10
17Ion/cm
2Between or 1 * 10
16Ion/cm
2With 1 * 10
17Ion/cm
2Between dosage inject a kind of or more kinds of ion component.Can inject a kind of or more kinds of ion component with the energy between about ten kilo electron volts (10KeV) and 150 kilo electron volts (150KeV).It at least partly is the function that ion injects the energy of bearing wafer 200 with the degree of depth that forms injection zone 206 that ion injects bearing wafer 200.Thereby, inject energy of ions through optionally controlling, can form injection region 206 at the desired depth place in the bearing wafer 200.Describe in further detail as following, the depth D 1 of the injection region 206 in the bearing wafer 200 can be corresponding to the expectation thickness and/or the amount of the layer of the semi-conducting material 202 that can transfer to treated semiconductor structure 100 subsequently.As non-limiting example; Can utilize the energy of selection that atomic composition is injected in the bearing wafer 200; With according to the depth D 1 between about ten nanometers (10nm) and about 1,000 nanometers (1000nm) (that is, approximately
to approximately
) to form injection region 206.
Another kind of bonding material 218 can be formed on the first type surface near injection region 206 of bearing wafer 200 alternatively, and can before forming injection region 206, be formed on the first type surface of bearing wafer 200.Bonding material 218 can have the adhering material of good molecule by dielectric material 114 that shows and cover treated semiconductor structure 100 (Fig. 1 and Fig. 2) or bonding material 118 (if existence) and form.Bonding material 218 can be by such as silicon dioxide (SiO
2), silicon oxynitride (SiO
xN
y) or silicon nitride (Si
3N
4) a kind of or more kinds of dielectric material form.Bonding material 218 can have the thickness between about 100 nanometers (100nm) and about two microns (2 μ m).As non-limiting example, bearing wafer 200 can be formed by silicon materials, and comprises silicon dioxide (SiO through carrying out conventional thermal oxidation technology, can on bearing wafer 200, forming
2) bonding material 218.Bonding material 218 can also for example utilize chemical vapor deposition (CVD), physical vapor deposition (PVD), ald (ALD) or plasma enhanced chemical vapor deposition (PECVD) to deposit.
Refer again to Fig. 2; Through (promptly with the exposing surface of bearing wafer 200; The exposing surface of semi-conducting material 202 or bonding material 218 (if exist)) (promptly near the exposing surface of treated semiconductor structure 100; Dielectric material 114 or bonding material 118 (if existence)), can bearing wafer 200 be bonded to treated semiconductor structure 100 to form the semiconductor structure 300 of bonding.In the temperature of room temperature or rising (for example; At least more than 100 degrees centigrade (100 ℃)) and enough for a long time under the pressure; Can bearing wafer 200 be bonded to semiconductor structure 100, so that bonding material 118 and semi-conducting material 202 or bonding material 218 (if existence) bonding are got up.As non-limiting example; Temperature through treated semiconductor structure 100 and bearing wafer 200 are exposed between about 100 degrees centigrade (100 ℃) and about 400 degrees centigrade (400 ℃) reaches the time between about 30 minutes and 120 minutes; Can carry out annealing in process, so that bearing wafer 200 and treated semiconductor structure 100 bondings are got up.In some embodiments, can not use adhesive material ground that treated semiconductor structure 100 is bonded to bearing wafer 200, this can reduce or eliminate the temperature and pressure restriction to further processing action of using this adhesive to cause.
With reference to Fig. 4; With bearing wafer 200 and treated semiconductor structure 100 bondings with the semiconductor structure 300 that forms bonding after; Can be (for example from treated semiconductor structure 100 first type surfaces; The back side 108) part of removal substrate 106 is to expose the surface of the wafer via interconnection 116 of passing substrate 106.For example, can use grinding technics, conventional CMP process, anisotropic etch process or their combination to remove the part of substrate 106.In some embodiments, substrate 106 can comprise etch stop material shown in broken lines 120 alternatively, like oxide material.Etch stop material 120 can be arranged on the diverse location place in the substrate 106 vertically.For example, etch stop material 120 can be positioned at substrate 106, and is positioned at the top, following or perpendicular of wafer via interconnects 116.
As non-restrictive example; Be fixed on the exposing surface of pushing substrate 106 on the vacuum chuck and against the polishing plate of rotation through for example bearing wafer 200; Chemically and/or physically effectively (promptly simultaneously; Grinding agent) slurry is removed the material of substrate 106, can carry out grinding and chemical mechanical polish process to remove the part of substrate 106 with respect to wafer via interconnects 116 and etch stop material 120 (if existence).
As another non-limiting example; Be injected into the exposing surface of substrate 106 through the solvent that will comprise potassium hydroxide (KOH) or TMAH (TMAH), can carry out wet corrosion technology with respect to the part of wafer via interconnection 116 with etch stop material (if existence) removal substrate 106.Bearing wafer 200 is used to operate treated semiconductor structure 100, and during thinning substrate 106 is with the surface of exposing wafer via interconnection 116, the supporting to treated semiconductor structure 100 is provided.The remainder of substrate 106 can have the thickness D2 from about 1/2nd microns (0.5 μ m) to about 100 microns (100 μ m).
As shown in Figure 5, as represented, can put upside down the semiconductor structure 300 of bonding through directional arrow, the planar semiconductor structure 400 that itself and another is treated is aimed at and is contacted.For example, the exposing surface of the wafer via of semiconductor structure 300 interconnection 116 can contact also bonding with the conductive welding disk that exposes 420 on the significant surface 404 of treated semiconductor structure 400.
Be similar to treated semiconductor structure 100, treated semiconductor structure 400 can comprise device area 402, and this device area 402 comprises device architecture 410.Device area 402 can extend in the substrate 406 on the surface with substrate 406 and/or above.Substrate 406 can comprise the substrate that front contact substrate 106 is described.Equally, the device architecture 410 of device area 402 can comprise the device architecture that the device architecture 110 of front contact Fig. 1 is described.In some embodiments, the device area 402 of treated semiconductor structure 400 can have the structure identical at least substantially with the device area 102 of treated semiconductor structure 100.
Behind the device area 402 that forms treated semiconductor structure 400, can on device area 402, form one or more conductive structure like conductive welding disk 420.Conductive welding disk 420 can comprise a kind of or more kinds of electric conducting material, such as a kind of or more kinds of metal (for example, copper (Cu), aluminium (Al) or tungsten (W), polysilicon and/or gold (Au)).For example, conductive welding disk 420 can be formed on the treated semiconductor structure 400 in the operation of rear end (BEOL).In some embodiments, conductive welding disk 420 can and use photoetching technique that the electric conducting material composition is formed through deposits conductive material (not shown) on dielectric material 414.In other embodiments, conductive welding disk 420 can form with the part (being commonly referred to " Damascus technics (Damascene Process) ") that covers on the opening of removing electric conducting material through electric conducting material being deposited in a plurality of opening (not shown) in the dielectric material 414 and carrying out chemico-mechanical polishing (CMP) technology.Through the interconnection 116 of the wafer via of treated semiconductor structure 100 is aimed at also bonding with the conductive welding disk 420 of treated semiconductor structure 400, the semiconductor structure 300 of bonding structurally is connected with treated semiconductor structure 400 each other and is electrically connected.
With reference to Fig. 6; Treated semiconductor structure 100 can be bonded to the semiconductor structure 500 of treated semiconductor structure 400 to form another bonding; In the semiconductor structure 500 of bonding, be connected on conductive welding disk 420 structures of the wafer via of treated semiconductor structure 100 interconnection 116 and treated semiconductor structure 400 and be electrically connected.In some embodiments, use direct metal such as hot compression bonding technology, non-hot compression bonding or eutectic bonding technology, can wafer via be interconnected and 116 be bonded directly to conductive welding disk 420 to metal bonding technology.For example; Wafer via interconnects 116 can all be formed by copper with conductive welding disk 420; And through be used for wafer via interconnects 116 and conductive welding disk each other the semiconductor structure 300 and the treated semiconductor structure 400 that get up in the time enough bonding of bonding be exposed to the temperature between about 100 degrees centigrade (100 ℃) and about 400 degrees centigrade (400 ℃), can carry out the bonding technology of the copper of low temperature to copper.
In other embodiments; Utilize direct wafer bonding technology, can be with the significant surface 108 and 404 (Fig. 5) of corresponding treated semiconductor structure 100 and 400 bonding each other, wherein; Significant surface 108 and 404 (for example can comprise conduction; Metal) zone and non-conductive (for example, dielectric) zone, and directly wafer bonding technology is bonded to dielectric material with metal bonding to metal and with dielectric material simultaneously.
On one or more significant surface 108 and 404, can form optional bonding material.As by shown in the non-limiting example of Fig. 5, optional dielectric bonding material shown in broken lines (for example, comprises silicon dioxide (SiO
2) material 122) can utilize the oxidate technology like the low temperature plasma depositing operation to be formed on alternatively on the substrate 106.Optional bonding material 122 can also be flattened to expose conductive welding disk 420; Such planarization for example can be carried out through CMP process.
The oxide that utilizes as describe with reference to Fig. 4 is to the oxide bonding technology, and earth silicon material 122 can be bonded to the dielectric material 414 of treated semiconductor structure 400.For example, earth silicon material 122 can at room temperature or under the temperature (for example, at least more than 100 degrees centigrade (100 ℃)) that raises be bonded to dielectric material 414.Metal can be at low temperature (promptly to the oxide bonding technology to metal bonding technology and oxide; Be lower than the temperature of about 400 degrees centigrade (400 ℃)) carry out down, and thereby avoid the device area 102 of treated semiconductor structure 100 and 400 and 402 infringement.According to method of the present disclosure; The treated semiconductor structure 100 and 400 that after the operation of execution rear end (BEOL), vertically piles up makes it possible at the conductive interconnection (for example, wafer via interconnection 116 and conductive welding disk 420 is connected) that forms during the bonding technology between the treated semiconductor structure 100 and 400.
During bonding semiconductor structure 100 and 400 or after the bonding completion; The material 202 of carrying substrates 200 (Fig. 5) ' a part can separate (promptly with the semiconductor structure 500 of bonding; Separately), thus with material 202 " transfer layer stay on the treated semiconductor structure 100.The material 202 of carrying substrates 200 ' the separation of part can carry out through various chemical technologies, thermal process or mechanical technology, such as carrying out through grinding technics, etching technics, glossing or stripping technology.For example, can carry out single annealing process with bonding semiconductor structure 100 each other with 400 and separates the material 202 of (that is, separately) carrying substrates 200 ' simultaneously with formation material 202 " transfer layer.First type surface through making treated semiconductor structure 100 (promptly; The exposing surface of the first type surface that exposes of substrate 106 and via plug (via plug) 110) first type surface that contacts treated semiconductor structure 400 (promptly; The first type surface that exposes of dielectric material 406 and the exposing surface of conductive welding disk 420) and the temperature between about 200 degrees centigrade (200 ℃) and about 400 degrees centigrade (400 ℃) anneal, can carry out annealing process.Annealing process is bonding semiconductor structure 100 and 400 (that is, wafer via interconnection 116 being bonded to conductive welding disk 420) and the semiconductor layer 202 from shifting side by side " separate the material 202 of carrying substrates 200 ' part.
As non-limiting example, in this area like SMART-CUT
TMAlready known processes can be used for from material 202 " transfer layer separate or separately material 202 ' part.For example, authorizing the United States Patent(USP) No. RE39 of Bruel, 484, authorize the United States Patent(USP) No. 5,374 of Aspar etc.; 564, authorize Aspar etc. United States Patent(USP) No. 6,303,468, authorize the United States Patent(USP) No. 6 of Aspar etc.; 335,258, authorize the United States Patent(USP) No. 6,756 of Moriceau etc.; 286, the United States Patent(USP) No. 6,809,044 of authorizing Aspar etc. and the United States Patent(USP) No. 6 of authorizing Aspar etc.; Described this technology in 946,365 in detail, the disclosure of each all is incorporated herein with them by reference.
In other embodiments; Can one or more other treated semiconductor structure (as via bonding technology) be bonded to the semiconductor structure 500 of bonding; One of them or more a plurality of other treated semiconductor structures can utilize above-described method to form; And can with material 202 " transfer layer in and/or the additional devices structure of top formation be electrically connected, and be electrically connected with the device architecture of treated semiconductor structure 100 and treated semiconductor structure 400.
In other embodiments, after handling, utilize anisotropic etch process, CMP process or their combination, can remove materials 202 from the semiconductor structure 500 of bonding " transfer layer.The transfer layer of " the surface roughness of transfer layer, and material 202 " can form very thin layer in such execution mode, can not consider material 202.For example, material 202 " the thickness D2 of transfer layer can be between about ten nanometers (10nm) and about 600 nanometers (600nm).
The material 202 of separated bearing wafer 200 ' remainder can in other processing, circulate and reuse.
Can use known equipment to adopt disclosed method, and thereby can in the manufacturing in enormous quantities (HVM) of semiconductor structure, adopt disclosed method.Thereby disclosed method can enable on more and more thinner semiconductor structure, to make electronic device, and the interconnection of enabled device structure during making three-dimensional integrated semiconductor device.
Execution mode of the present invention can use in the semiconductor structure of any kind three-dimensional integrated, comprise that nude film is integrated to nude film (D2D), nude film to wafer (D2W), wafer to wafer (W 2W) is integrated or the combination of these integrated techniques.
For example, shown in Figure 7, can the semiconductor wafer that comprise a plurality of independent semiconductor dies 602 600 be cut into single, to form independent nude film 602.Can utilize such as saw, carve and fracture or the technology of laser ablation is come cutting semiconductor chip 600.Can from a plurality of semiconductor dies 602, identify the known good nude film.
The known good nude film that from a plurality of semiconductor dies 602, identifies can be individually and individually is attached to the carrying nude film and is processed (for example, thinning), and the method for describing according to front among this paper simultaneously utilizes the carrying nude film to operate the known good nude film.
With reference to Fig. 8, according to the method that front among this paper is described, the known good nude film then can structurally be connected to another wafer 800 and be electrically connected with this wafer 800.Wafer 800 can comprise a plurality of nude films of making at least partially on it.For example, the wafer via of known good semiconductor die 602 interconnection 610 can be aimed at also bonding with the conductive welding disk 820 of nude film on the wafer 800.Describe with reference to Fig. 6 like the front; Can carry out annealing process with along carry atenuator region in the nude film opened in 604 minutes the part 602 of carrying nude film ', simultaneously in the wafer via interconnection 610 of known good nude film 602 with forming metal to metal bonding between the conductive welding disk 820 of the nude film that forms of part at least on the wafer 800.In some embodiments, carry nude film 602 " remainder can use etching technics or CMP process to remove.In other embodiments, carry nude film 602 " remainder can be as the basal layer of making other device architecture.In some embodiments; A plurality of known good nude films 602 that nude film was attached to can structurally be connected to wafer 800 and be electrically connected with wafer 800; On wafer 800, constructing the wafer of the wafer 600 shown in similar Fig. 7 at least substantially again, and can side by side in one technology, separately carry substantially 602 of nude film '.Again construct wafer as semiconductor wafer 600 and can comprise and utilize the known good nude film to constitute wafer that deposition oxide material and planarization subsequently forms continuous surface to utilize the known good nude film in the embed oxide material.
Other non-limiting example execution mode of the present invention is described below.
Execution mode 1: a kind of method of making semiconductor structure, this method may further comprise the steps: first semiconductor structure that on first substrate, forms at least a portion that comprises integrated circuit; Ion is injected bearing wafer in bearing wafer, to form atenuator region; Bearing wafer is bonded directly to first side of first semiconductor structure; Bearing wafer had been attached to the first semi-conductive while, is utilizing bearing wafer to operate first semiconductor structure to handle first semiconductor structure; To comprise that second semiconductor structure of at least a portion of integrated circuit is bonded directly to second side of first semiconductor structure, this second side and first semiconductor structure by Direct Bonding first side of bearing wafer opposite; And will separate from the remainder of the material layer that carries wafer with bearing wafer along the atenuator region in the bearing wafer.
Execution mode 2: according to the method for execution mode 1, this method is further comprising the steps of: form at least one wafer via interconnection (TWI) of at least partly passing first substrate.
Execution mode 3: according to the method for execution mode 1 or execution mode 2; Wherein, The step of handling first semiconductor structure may further comprise the steps: remove the part of first substrate from second side of first semiconductor structure, and expose at least one conductive structure of at least a portion of the integrated circuit of first semiconductor structure.
Execution mode 4: according to the method for execution mode 3, wherein, the step of at least one conductive structure of at least a portion of exposing the integrated circuit of first semiconductor structure may further comprise the steps: expose the wafer via interconnection (TWI) in first semiconductor structure.
Execution mode 5: according to the method for execution mode 4; Wherein, the step that second semiconductor structure is bonded directly to second side of first semiconductor structure may further comprise the steps: at least one conducting element that the wafer via interconnection of first semiconductor structure is bonded directly to second semiconductor structure.
Execution mode 6: according to each method in the execution mode 1 to 5; Wherein, the step that second semiconductor structure is bonded directly to second side of first semiconductor structure may further comprise the steps: the metal that the direct bonded metal of at least one conducting element of first semiconductor structure is incorporated at least one conducting element of second semiconductor structure.
Execution mode 7: according to each method in the execution mode 1 to 6; Wherein, the step that second semiconductor structure is bonded directly to second side of first semiconductor structure may further comprise the steps: semi-conducting material that the semi-conducting material and at least one side in the oxide material of second semiconductor structure is bonded directly to first semiconductor structure and at least one side in the oxide material.
Execution mode 8: according to each method in the execution mode 1 to 7; Wherein, The step that to separate from the remainder of the material layer that carries wafer and bearing wafer along the atenuator region in the bearing wafer may further comprise the steps: under at least 100 ℃ temperature, bearing wafer is annealed, and the part of the covering atenuator region of bearing wafer another part that still is attached to first semiconductor structure with this bearing wafer is separated.
Execution mode 9: according to each method in the execution mode 1 to 8; Wherein, the step that will separate from the remainder of the material layer that carries wafer and bearing wafer along the atenuator region in the bearing wafer may further comprise the steps: make the thickness of said carrying substrates still be attached to said first semiconductor structure at about 10nm to the material layer between about 1000nm.
Execution mode 10: according to each method in the execution mode 1 to 9, wherein, second semiconductor structure causes along the atenuator region in the bearing wafer from the bearing wafer separating layers of material to the Direct Bonding of second side of first semiconductor structure.
Execution mode 11: according to the method for execution mode 10; Wherein, The step that bearing wafer is bonded directly to first side of first semiconductor structure may further comprise the steps: along this bearing wafer of the reduction of the atenuator region in the bearing wafer, but do not separate this bearing wafer along the atenuator region in the bearing wafer.
Execution mode 12: a kind of method of making semiconductor structure, this method may further comprise the steps: ion is injected first semiconductor structure and forms atenuator region at first semiconductor structure; The surface that the surface of first semiconductor structure is bonded directly to second semiconductor structure comprises the semiconductor structure of the bonding of first semiconductor structure and second semiconductor structure with formation; Utilize first semiconductor structure to operate the semiconductor structure of bonding, remove the part of second semiconductor structure simultaneously and expose at least one conductive structure that extends through second semiconductor structure at least in part; At least one conductive structure that passes second semiconductor structure and expose is aimed at at least one conductive structure of the 3rd semiconductor structure; The semiconductor structure of para-linkage and the 3rd semiconductor structure heat; In response to the heating of the semiconductor structure and the 3rd semiconductor structure of para-linkage, at least one conductive structure that passes second semiconductor structure and expose is bonded directly at least one conductive structure of the 3rd semiconductor structure; In response to the heating of the semiconductor structure and the 3rd semiconductor structure of para-linkage, cut apart first semiconductor structure along atenuator region, and on second semiconductor structure, stay the part of first semiconductor structure.
Execution mode 13: according to the method for execution mode 12, this method is further comprising the steps of: form at least one conductive structure that passes second semiconductor structure and expose, to comprise wafer via interconnection (TWI).
Execution mode 14: according to the method for execution mode 12 or execution mode 13, wherein, the step of ion being injected first semiconductor structure may further comprise the steps: make the surface of semiconductor wafer be exposed to 10
16Ion/cm
2With 2 * 10
17Ion/cm
2Between dosage and the ion of the energy between 10KeV and the 150KeV.
Execution mode 15: according to each method in the execution mode 12 to 14; Wherein, the step of ion being injected first semiconductor structure may further comprise the steps: ion is injected bearing wafer and in bearing wafer, begins to form atenuator region between about 10nm to the about degree of depth of 1000nm according to the planar major surface from this bearing wafer.
Execution mode 16: according to each method in the execution mode 12 to 15; Wherein, the surface that the surface of first semiconductor structure is bonded directly to second semiconductor structure may further comprise the steps with the step of the semiconductor structure that forms bonding: with the surface bond of the silicon bearing wafer surface to the silicon or the earth silicon material of second semiconductor structure.
Execution mode 17: according to each method in the execution mode 12 to 16; Wherein, the surface that the surface of first semiconductor structure is bonded directly to second semiconductor structure may further comprise the steps with the step of the semiconductor structure that forms bonding: with the surface bond of the earth silicon material on the silicon bearing wafer to the silicon of said second semiconductor structure or the surface of earth silicon material.
Execution mode 18: according to each method in the execution mode 12 to 17; Wherein, at least one conductive structure that exposes passing second semiconductor structure may further comprise the steps with the step that at least one conductive structure of the 3rd semiconductor structure is aimed at: will pass second semiconductor structure and at least one wafer copper vias interconnection (TWI) of exposing is aimed at at least one copper bonding welding pad of the 3rd semiconductor structure.
Execution mode 19: according to the method for execution mode 18; Wherein, the step that heats of the semiconductor structure of para-linkage and the 3rd semiconductor structure may further comprise the steps: the semiconductor structure and the 3rd semiconductor structure of bonding are heated to the temperature between about 100 ℃ and about 400 ℃.
Execution mode 20: according to each method in the execution mode 12 to 19; This method is further comprising the steps of: cutting apart first semiconductor structure and being arranged on the part on second semiconductor structure or after this part forms at least one device architecture, handling the part on second semiconductor structure that is positioned at of first semiconductor structure at first semiconductor structure along atenuator region.
Execution mode 21: according to each method in the execution mode 12 to 19, this method is further comprising the steps of: after cutting apart first semiconductor structure along atenuator region, remove the part of first semiconductor structure from second semiconductor structure.
Execution mode 22: a kind of semiconductor structure of bonding, the semiconductor structure of this bonding comprises: the treated semiconductor structure of a plurality of bondings; And carrying nude film or wafer; It is bonded at least one the treated semiconductor structure in the treated semiconductor structure of a plurality of bondings; Carry nude film or wafer and have atenuator region, atenuator region comprises that the surface according at least one the treated semiconductor structure from the treated semiconductor structure that is bonded to a plurality of bondings that carries nude film or wafer begins a plurality of injection ions in the mean depth between about 10nm and 1000nm.
Execution mode 23: according to the semiconductor structure of the bonding of execution mode 22, wherein, the treated semiconductor structure of a plurality of bondings structurally links together at least in part and is electrically connected through the wafer via interconnection.
Execution mode 24: according to the semiconductor structure of the bonding of execution mode 22 or 23, wherein, the treated semiconductor structure of a plurality of bondings does not use under the situation of adhesive material Direct Bonding together between them.
Execution mode 25:, wherein, carry nude film or direct wafer bonding at least one treated semiconductor structure in the treated semiconductor structure of a plurality of bondings according to the semiconductor structure of each bonding in the execution mode 22 to 24.
Although used particular example to describe execution mode of the present invention among this paper, those of ordinary skills will be familiar with and understand, and the invention is not restricted to the details of example embodiment.On the contrary, below not departing from, under the situation of desired scope of the present invention, can make many interpolations, deletion and modification.For example, the characteristic of an execution mode can with the characteristics combination of other execution modes, and still be included in by in the desired scope of the present invention of the inventor.
Claims (15)
1. method of making semiconductor structure, this method may further comprise the steps:
On first substrate, form first semiconductor structure of at least a portion that comprises integrated circuit;
Ion is injected bearing wafer in said bearing wafer, to form atenuator region;
Said bearing wafer is bonded directly to first side of said first semiconductor structure;
When said bearing wafer is attached to said first semiconductor structure, utilize said bearing wafer to operate said first semiconductor structure to handle said first semiconductor structure;
To comprise that second semiconductor structure of at least a portion of integrated circuit is bonded directly to second side of said first semiconductor structure, this second side and said first semiconductor structure by Direct Bonding said first side of said bearing wafer opposite; And
Said atenuator region in said bearing wafer makes the material layer from said bearing wafer separate with the remainder of said bearing wafer.
2. method according to claim 1, this method is further comprising the steps of: form at least one wafer via interconnection that at least partly extends through said first substrate.
3. method according to claim 1; Wherein, The step of said first semiconductor structure of said processing may further comprise the steps: remove the part of said first substrate from said second side of said first semiconductor structure, and expose at least one conductive structure of said at least a portion of the said integrated circuit of said first semiconductor structure.
4. method according to claim 3; Wherein, the step of at least one conductive structure of said at least a portion of the said said integrated circuit that exposes said first semiconductor structure may further comprise the steps: expose the wafer via interconnection in said first semiconductor structure.
5. method according to claim 4; Wherein, the said step that said second semiconductor structure is bonded directly to second side of said first semiconductor structure may further comprise the steps: at least one conducting element that the said wafer via interconnection of said first semiconductor structure is bonded directly to said second semiconductor structure.
6. method according to claim 1; Wherein, the said step that said second semiconductor structure is bonded directly to second side of said first semiconductor structure may further comprise the steps: the metal that the direct bonded metal of at least one conducting element of said first semiconductor structure is incorporated at least one conducting element of said second semiconductor structure.
7. method according to claim 1; Wherein, the said step that said second semiconductor structure is bonded directly to second side of said first semiconductor structure may further comprise the steps: semi-conducting material that the semi-conducting material and at least one side in the oxide material of said second semiconductor structure is bonded directly to said first semiconductor structure and at least one side in the oxide material.
8. method according to claim 1; Wherein, Said atenuator region in the said bearing wafer in said edge may further comprise the steps the remainder separation steps from the material layer of said bearing wafer and said bearing wafer: at least 100 ℃ temperature said bearing wafer is annealed, and the part of the said atenuator region of covering of said bearing wafer another part that still is attached to said first semiconductor structure with said bearing wafer is separated.
9. method according to claim 1; Wherein, the said atenuator region in the said bearing wafer in said edge makes from the material layer of said bearing wafer and the remainder separation steps of said bearing wafer and may further comprise the steps: make the thickness of said carrying substrates still be attached to said first semiconductor structure at about 10nm to the material layer between about 1000nm.
10. method according to claim 1, wherein, said second semiconductor structure causes separating said material layer along the said atenuator region in the said bearing wafer from said bearing wafer to the Direct Bonding of said second side of said first semiconductor structure.
11. method according to claim 10; Wherein, The said step that said bearing wafer is bonded directly to said first side of said first semiconductor structure may further comprise the steps: along the said bearing wafer that weakens of the said atenuator region in the said bearing wafer, but do not cut apart said bearing wafer along the said atenuator region in the said bearing wafer.
12. the semiconductor structure of a bonding, the semiconductor structure of this bonding comprises:
The treated semiconductor structure of a plurality of bondings; And
Carry nude film or wafer; It is bonded at least one the treated semiconductor structure in the treated semiconductor structure of said a plurality of bondings; Said carrying nude film or wafer have atenuator region, and said atenuator region comprises that the surface of said at least one the treated semiconductor structure from the treated semiconductor structure that is bonded to said a plurality of bondings of said carrying nude film or wafer begins a plurality of injection ions of the mean depth between about 10nm and 1000nm.
13. the semiconductor structure of bonding according to claim 12, wherein, the treated semiconductor structure of said a plurality of bondings structurally links together and is electrically connected through the wafer via interconnection at least in part.
14. the semiconductor structure of bonding according to claim 12, wherein, the treated semiconductor structure of said a plurality of bondings does not use under the situation of adhesive material Direct Bonding together between them.
15. the semiconductor structure of bonding according to claim 14, wherein, said carrying nude film or direct wafer bonding said at least one treated semiconductor structure in the treated semiconductor structure of said a plurality of bondings.
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|---|---|---|---|
| CN201510873777.3A CN105489512B (en) | 2010-07-19 | 2011-07-19 | Interim semiconductor structure bonding method and related bonding semiconductor structure |
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|---|---|---|---|
| US12/839,203 | 2010-07-19 | ||
| US12/839,203 US8461017B2 (en) | 2010-07-19 | 2010-07-19 | Methods of forming bonded semiconductor structures using a temporary carrier having a weakened ion implant region for subsequent separation along the weakened region |
| FR1056122 | 2010-07-26 | ||
| FR1056122A FR2963162B1 (en) | 2010-07-26 | 2010-07-26 | TEMPORARY SEMICONDUCTOR STRUCTURE BONDING METHODS AND CORRESPONDING BONDED SEMICONDUCTOR STRUCTURES |
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| CN102903610A (en) * | 2011-07-28 | 2013-01-30 | 索泰克公司 | Process for manufacturing a semiconductor structure comprising a functionalized layer on a support substrate |
| CN107017197A (en) * | 2015-12-31 | 2017-08-04 | 台湾积体电路制造股份有限公司 | Semiconductor structure and its manufacture method |
| CN108573882A (en) * | 2017-03-13 | 2018-09-25 | 库利克和索夫工业公司 | System and method for being bonded to semiconductor element |
| CN109449137A (en) * | 2018-11-15 | 2019-03-08 | 德淮半导体有限公司 | Semiconductor device and its manufacturing method |
| CN110164978A (en) * | 2018-02-14 | 2019-08-23 | 联华电子股份有限公司 | Semiconductor device with and preparation method thereof |
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| WO2018157937A1 (en) | 2017-03-02 | 2018-09-07 | Ev Group E. Thallner Gmbh | Method and device for bonding chips |
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Also Published As
| Publication number | Publication date |
|---|---|
| TW201205688A (en) | 2012-02-01 |
| KR20120010120A (en) | 2012-02-02 |
| TWI445101B (en) | 2014-07-11 |
| KR101311332B1 (en) | 2013-09-27 |
| SG177817A1 (en) | 2012-02-28 |
| CN105489512A (en) | 2016-04-13 |
| CN105489512B (en) | 2018-01-30 |
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