CN102280497A - Accumulation metal oxide semiconductor (A-MOS) varactor and making process thereof - Google Patents
Accumulation metal oxide semiconductor (A-MOS) varactor and making process thereof Download PDFInfo
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- CN102280497A CN102280497A CN2011102573536A CN201110257353A CN102280497A CN 102280497 A CN102280497 A CN 102280497A CN 2011102573536 A CN2011102573536 A CN 2011102573536A CN 201110257353 A CN201110257353 A CN 201110257353A CN 102280497 A CN102280497 A CN 102280497A
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Abstract
The invention provides an accumulation metal oxide semiconductor (A-MOS) varactor and a making process thereof, and aims to expand the capacitance adjustment range of the varactor. The varactor comprises a pit structure, a source end, a drain end and a gate end, wherein the pit structure is a low-threshold pit or a deep pit. The making process of the varactor comprises the following steps of: providing a substrate; forming an insulating layer on the substrate; photoetching the insulating layer on the basis of a pit photomask template to form a pit doping region; injecting impurity ions into the pit doping region to form the low-threshold pit or the deep pit; and completing the making of a gate structure, a source structure and a drain structure by subsequent conventional processes.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to accumulation type field effect transistor (A-MOS, Accumulation MOS) variable capacitance and manufacturing process thereof.
Background technology
Fig. 1 is the structural representation of existing P type substrate A-MOS variable capacitance (Varactor), and diagram A-MOS variable capacitance comprises P type substrate (P-substrate) 10, N trap (N-well) 11, is used as N type doped region 13, gate insulation layer 15 and the polysilicon gate 14 of source electrode and drain electrode.With the electromotive force on the N type doped region 13 is the zero potential position, and then when the gate voltage Vg change added on the polysilicon gate 14, the electric capacity of A-MOS is change thereupon also.Concrete principle is as follows:
When Vg is negative voltage, polysilicon gate 14 electromotive forces are lower than N trap 11 electromotive forces, free electron in the polysilicon gate 14 will be attracted the contact-making surface that gathers with gate insulation layer 15, and N trap 11 constitutes positively charged depletion layer with the contact-making surface of gate insulation layer 15, reaches electric potential balancing.Because the N type doping content of N trap 11 is lower, therefore need the positively charged depletion layer thickness of gathering very high, and free electron thickness can be ignored, therefore when Vg is negative voltage, the electric capacity of A-MOS variable capacitance depends primarily on the depletion layer thickness and the gate insulation layer thickness of N trap 11, because electric capacity and thickness are inversely proportional to, therefore the electric capacity of A-MOS variable capacitance is C1 than hanging down at this moment.
When Vg was positive voltage, polysilicon gate 14 electromotive forces were higher than N trap 11 electromotive forces, formed positively charged depletion layer at the contact-making surface of polysilicon gate 14 and gate insulation layer 15, and the free electron of N trap 11 is attracted the contact-making surface that is focused to gate insulation layer 15, reaches electric potential balancing.Because electrical thickness ignores, therefore this moment the A-MOS variable capacitance electric capacity depend primarily on the depletion layer thickness and the gate insulation layer thickness of polysilicon gate 14.Polysilicon gate 14 is heavy doping, its dopant ion concentration is far above the concentration in the N trap 11, only need less exhausting just that the positive charge that balances each other with the substrate free electron can be provided, the depletion layer of N trap 11 is compared when therefore being negative voltage with Vg, the depletion layer thickness of polysilicon gate 14 is lower, and the electric capacity of A-MOS variable capacitance is higher at this moment is C2.Wherein the ratio of C2 and C1 is the capacitance adjustment scope of this A-MOS variable capacitance.
Along with the various range of application expansions of variable capacitance, the capacitance adjustment scope of above-mentioned A-MOS variable capacitance can't satisfy actual needs, therefore needs further expansion badly.
Summary of the invention
The invention provides A-MOS variable capacitor structure and manufacturing process, to improve the capacitance adjustment scope of A-MOS variable capacitance.
Analyze according to the inventor, the capacitance adjustment scope of P type substrate A-MOS variable capacitance shown in Figure 1 is mainly by C1 and C2 decision, because polysilicon gate 14 is heavy doping, therefore only the thickness with gate oxide 15 is relevant with technology is irrelevant substantially for C2, C1 is mainly by N trap 11 doping contents and consistency decision thereof, the doping content of N trap 11 is low more, the depletion layer thickness that forms in it is big more, then the value of C1 is more little, the consistency of N trap 11 is good more in addition, depletion layer can be thick more under same voltage, and the value of C1 is also more little, and its adjustable extent C2/C1 is also just big more.Therefore technical scheme core thinking provided by the invention is not increase under the situation of processing step and adopts the lower or better well structure of consistency of doping content, so that further reduce the value of C1, improves the capacitance adjustment scope C2/C1 of A-MOS variable capacitance.
A kind of A-MOS variable capacitance provided by the invention adopts low threshold value (Low-Vt) N trap to substitute conventional N trap as well structure, low threshold value N trap is a kind of technical term of semiconductor applications, mean a kind of trap that surface doping concentration is lower than conventional N trap surface doping concentration, the N-MOS device that provides threshold voltage lower is provided low threshold value N trap.
Another kind of A-MOS variable capacitance provided by the invention adopts dark N trap (DNW) as well structure, dark N trap also is a kind of technical term, its consistency (Uniform) is far above the consistency of conventional trap, dark N trap is mainly used in existing technology isolates P trap and P substrate, therefore dark N trap all is to be injected into P trap below, when dark N trap is directly injected the P substrate, because the concentration of P substrate is very low, therefore dark N trap can allow P substrate transoid and become the very light N type trap of doping content, the extraordinary N type of this very light while consistency trap can allow C1 approach 0, therefore adopts above-mentioned structure and method can allow the value of this A-MOS variable capacitance C1 reduce significantly.
The present invention also provides a kind of A-MOS variable capacitance, the trap that adopts the acquisition of VTP technology is as well structure, it is a kind of technical term of semiconductor applications that the VTP ion injects, meaning the independent ion of adjusting the P-MOS threshold voltage injects, be that the lower N type of doping content mixes, usually the direct zone of injecting of VTP is the N well area is adjusted the N well area with secondary a concentration, when directly being carried out the VTP ion to P type substrate, injects VTP, P type substrate can transoid become N type trap, it is lower that the trap that adopts VTP technology to make is compared conventional N-well process doping content, thereby reduced the C1 value of A-MOS variable capacitance, and then improved the capacitance adjustment scope.
Above-mentioned A-MOS variable capacitance manufacturing process provided by the invention usually can with existing manufacturing process compatibility, and can obviously not increase existing A-MOS variable capacitance cost of manufacture.
Because above-mentioned A-MOS variable capacitance provided by the invention mainly is to have adopted other doping content or the better trap of consistency, therefore A-MOS variable capacitance manufacturing process core provided by the invention is that well structure making related process improves, and mainly is to adopt the technology or the VTP technology of making Low-Vt trap, dark N trap to substitute the trap manufacturing process that has the A-MOS variable capacitance now.According to the core thinking, the invention provides following A-MOS variable capacitance manufacturing process.
A kind of A-MOS variable capacitance manufacturing process provided by the invention adopts and makes Low-Vt trap, dark N-well process or VTP technology making well structure.
A kind of A-MOS variable capacitance manufacturing process provided by the invention comprises step: substrate is provided; On substrate, form insulating barrier; Based on the trap photomask, the photoetching insulating barrier forms the trap doped region; The trap doped region is carried out foreign ion inject, form low threshold value trap or deep trap; And, finish the making of grid, source electrode and drain electrode structure by follow-up common process.
The invention provides another kind of A-MOS variable capacitance manufacturing process, comprise step: provide substrate; On substrate, form insulating barrier; Based on the trap photomask, the photoetching insulating barrier forms the trap doped region; Adopt VTP technology to form well structure; And, finish the making of grid, source electrode and drain electrode structure by follow-up common process.
Description of drawings
Fig. 1 is the structural representation of existing P type substrate A-MOS variable capacitance (Varactor);
Fig. 2～Fig. 6 is each stage structures schematic diagram in the manufacturing process of P type substrate A-MOS variable capacitance in the embodiment of the invention;
Fig. 7 is that variable capacitance is made schematic flow sheet in the second embodiment of the invention.
Embodiment
P type substrate A-MOS is provided three embodiment of variable capacitance below, and for the enforcement of N type substrate A-MOS variable capacitance, persons skilled in the art are released execution mode according to these three embodiment easily, repeat no more.
The P type substrate A-MOS variable capacitance of embodiment one, the low threshold value N trap of employing.
The main difference of the structure of low threshold value N trap and N well structure is that doping content is lower, parameters such as other size are identical, therefore adopt the cross-section structure of the P type substrate A-MOS variable capacitance that hangs down threshold value N trap also identical with structure shown in Figure 1, the surface doping concentration of low threshold value N trap normally about half of N trap doping content, is embodied in doping process parameter difference in following manufacturing process.
With reference to Fig. 2～Fig. 6, the manufacturing process of this P type substrate A-MOS variable capacitance comprises in the present embodiment:
Step a1 as Fig. 2, provides P type substrate 20, the about 7E14 of impurity concentration/cm-3;
Step a2 as Fig. 3, forms insulating barrier 21 on substrate 20, the about 100A of thickness, and material can be a silicon dioxide etc.
Step a3, as Fig. 4, based on the trap lay photoetching mask plate, photoetching insulating barrier 21 forms trap doped region 22;
Step a3 as Fig. 5, carries out foreign ion and injects, and pushes away trap and form low threshold value N trap 23, and wherein injecting ion can be As or Ph, and implantation dosage is 1E12cm
-2～1E13cm
-2, the injection energy is 20Kev～400Kev, the about 1E17cm of dopant ion concentration of the low threshold value N trap of formation
-3～6E17cm
-3
Step a4 as Fig. 6, finishes the making of grid, source electrode and drain electrode structure by follow-up common process, obtains P type substrate A-MOS variable capacitance 24.
The P type substrate A-MOS variable capacitance of embodiment two, the dark N trap of employing (DNW).
Dark N trap is used in substrate isolation device, high tension apparatus and the BCD technology at present usually, and what carry out is shallow doping, and its consistency is far above the N trap, so the minimum capacitance value C1 of this variable capacitance is just very low, has improved the capacitance adjustment scope of variable capacitance.This A-MOS variable capacitance manufacturing process that present embodiment provides comprises as follows, with reference to Fig. 7.
Step b1 provides P type substrate, the about 7E14 of impurity concentration/cm
-3
Step b2 forms insulating barrier on this substrate, the about 100A of thickness, and material can be a silicon dioxide;
Step b3, based on the trap lay photoetching mask plate, the photoetching insulating barrier forms the trap doped region;
Step b4 injects P type substrate with dark N trap by the trap doped region, makes the P type substrate of injection zone become weak N type, and wherein injecting ion can be Ph, and implantation dosage is 1E12cm
-2～2E13cm
-2, the injection energy is 20Kev～2000Kev, the about 4E16cm of dopant ion concentration of the dark N trap of formation
-3～4E17cm
-3
Step b5 finishes the making of grid, source electrode and drain electrode structure by follow-up common process, obtains P type substrate A-MOS variable capacitance
Embodiment three, employing VTP technology are made the P type substrate A-MOS variable capacitance of well structure.
The well structure doping content of making by VTP technology is extremely low, thereby improves the C1 value of A-MOS variable capacitance, and then improves the capacitance adjustment scope.
In the present embodiment, A-MOS variable capacitance manufacturing process comprises:
Step c1 provides P type substrate, the about 7E14 of impurity concentration/cm
-3
Step c2 forms insulating barrier on this substrate, the about 100A of thickness, and material can be a silicon dioxide;
Step c3, based on the trap lay photoetching mask plate, the photoetching insulating barrier forms the trap doped region;
Step c4 injects VTP ion (doping of n type) to the trap doped region, and described VTP ion can be As or Ph, and implantation dosage is 1E12cm
-2～1E13cm
-2, the injection energy is 20Kev～130Kev, the about 1E16cm of the doping content of the well structure of formation
-3～2E17cm
-3
Step c5 finishes the making of grid, source electrode and drain electrode structure by follow-up common process, obtains P type substrate A-MOS variable capacitance.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (11)
1. an accumulation type field effect transistor variable capacitance comprises well structure, source end, drain terminal and grid end, it is characterized in that, described well structure is low threshold value trap or deep trap.
2. variable capacitance as claimed in claim 1 is characterized in that, the doping content of described low threshold value trap is 4E16cm
-3～6E17cm
-3, and the degree of depth of described deep trap is 0.5 micron～2 microns, the doping content of described deep trap is 4E16cm
-3～4E17cm
-3
3. an accumulation type field effect transistor variable capacitance comprises well structure, source end, drain terminal and grid end, it is characterized in that, described well structure adopts the P-MOS threshold voltage to adjust ion implantation technology and forms.
4. variable capacitance as claimed in claim 3 is characterized in that, the well structure doping content that described employing P-MOS threshold voltage is adjusted ion implantation technology formation is 1E16cm
-3～2E17cm
-3
5. accumulation type field effect transistor variable capacitance manufacturing process, described variable capacitance comprises well structure, source end, drain terminal and grid end, it is characterized in that, this technology comprises step:
Substrate is provided;
On substrate, form insulating barrier;
Based on the trap photomask, the photoetching insulating barrier forms the trap doped region;
The trap doped region is carried out foreign ion inject, form low threshold value trap or dark N trap;
By follow-up common process, finish the making of grid, source electrode and drain electrode structure.
6. manufacturing process as claimed in claim 5 is characterized in that, the doping content of described low threshold value trap is 4E16cm
-3～6E17cm
-3, and the degree of depth of described deep trap is 0.2 micron～1 micron, the doping content of described deep trap is 4E16cm
-3～4E17cm
-3
7. manufacturing process as claimed in claim 6 is characterized in that, described foreign ion is As or Ph, and implantation dosage is 1E12cm
-2～1E13cm
-2, the injection energy is 20Kev～400Kev.
8. manufacturing process as claimed in claim 6 is characterized in that, described foreign ion Ph, implantation dosage are 1E12cm
-2～2E13cm
-2, the injection energy is 20Kev～2000Kev.
9. accumulation type field effect transistor variable capacitance manufacturing process, described variable capacitance comprises well structure, source end, drain terminal and grid end, it is characterized in that, this technology comprises step:
Substrate is provided;
On substrate, form insulating barrier;
Based on the trap photomask, the photoetching insulating barrier forms the trap doped region;
Adopt the P-MOS threshold voltage to adjust ion implantation technology and form well structure;
By follow-up common process, finish the making of grid, source electrode and drain electrode structure.
10. manufacturing process as claimed in claim 9 is characterized in that, the ion that described ion implantation technology is injected is As or Ph, and implantation dosage is 1E12cm
-2～1E13cm
-2, the injection energy is 20Kev～130Kev.
11. manufacturing process as claimed in claim 9 is characterized in that, the doping content of described well structure is 1E16cm
-3～2E17cm
-3
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104576765A (en) * | 2014-12-26 | 2015-04-29 | 上海集成电路研发中心有限公司 | Light-leakage preventing storage capacitor structure and preparation method thereof |
| CN111200026A (en) * | 2019-01-09 | 2020-05-26 | 合肥晶合集成电路有限公司 | Method for manufacturing semiconductor element |
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| US20100226166A1 (en) * | 2009-03-03 | 2010-09-09 | Sang-Hee Jung | MOS capacitor and charge pump with MOS capacitor |
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| CN1564456A (en) * | 2004-03-18 | 2005-01-12 | 上海迪申电子科技有限责任公司 | LC voltage-controlled oscillator gain model based on reinforced variable capacitance large single analysis |
| US20070210364A1 (en) * | 2004-04-28 | 2007-09-13 | Semiconductor Energy Laboratory Co., Ltd | Mos Capacitor And Semiconductor Device |
| US7276746B1 (en) * | 2005-06-27 | 2007-10-02 | Altera Corporation | Metal-oxide-semiconductor varactors |
| US20070145435A1 (en) * | 2005-12-28 | 2007-06-28 | San Hong Kim | Mos varactor |
| US20100226166A1 (en) * | 2009-03-03 | 2010-09-09 | Sang-Hee Jung | MOS capacitor and charge pump with MOS capacitor |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104576765A (en) * | 2014-12-26 | 2015-04-29 | 上海集成电路研发中心有限公司 | Light-leakage preventing storage capacitor structure and preparation method thereof |
| CN104576765B (en) * | 2014-12-26 | 2018-01-26 | 上海集成电路研发中心有限公司 | Light leakage storage capacitor construction and preparation method thereof |
| CN111200026A (en) * | 2019-01-09 | 2020-05-26 | 合肥晶合集成电路有限公司 | Method for manufacturing semiconductor element |
| CN111200026B (en) * | 2019-01-09 | 2020-10-16 | 合肥晶合集成电路有限公司 | Method for manufacturing semiconductor element |
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Application publication date: 20111214 |