CN102244061A - Low-k芯片封装结构 - Google Patents

Low-k芯片封装结构 Download PDF

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Publication number
CN102244061A
CN102244061A CN2011102002120A CN201110200212A CN102244061A CN 102244061 A CN102244061 A CN 102244061A CN 2011102002120 A CN2011102002120 A CN 2011102002120A CN 201110200212 A CN201110200212 A CN 201110200212A CN 102244061 A CN102244061 A CN 102244061A
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China
Prior art keywords
chip
metal
low
thin layer
layer
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Pending
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CN2011102002120A
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English (en)
Inventor
张黎
赖志明
陈锦辉
陈栋
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Jiangyin Changdian Advanced Packaging Co Ltd
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Jiangyin Changdian Advanced Packaging Co Ltd
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Application filed by Jiangyin Changdian Advanced Packaging Co Ltd filed Critical Jiangyin Changdian Advanced Packaging Co Ltd
Priority to CN2011102002120A priority Critical patent/CN102244061A/zh
Priority to US14/233,461 priority patent/US8987055B2/en
Priority to US14/233,596 priority patent/US20140191379A1/en
Priority to PCT/CN2011/081112 priority patent/WO2013010352A1/zh
Priority to PCT/CN2011/081113 priority patent/WO2013010353A1/zh
Publication of CN102244061A publication Critical patent/CN102244061A/zh
Pending legal-status Critical Current

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Abstract

本发明涉及一种Low-k芯片封装结构，属于芯片封装技术领域。它包括芯片本体I（2-1）、芯片电极（2-2）和芯片表面钝化层（2-3），芯片本体I（2-1）外包覆有薄膜层I（2-4），薄膜层I（2-4）背面设置有支撑圆片（2-5），芯片电极（2-2）经由再布线金属走线（2-6）转移至芯片周边外的薄膜层I（2-4）上，再布线金属走线（2-6）的终端设置有金属柱（2-7），金属柱（2-7）外包覆有薄膜层II（2-8），金属柱（2-7）顶端露出薄膜层II（2-8），在露出的金属柱（2-7）顶端设置有金属层（2-9），金属层（2-9）上设置有焊球（2-10）。本发明一种Low-k芯片封装结构解决了芯片封装过程应力集中导致Low-k芯片失效的问题，而且封装成本低，产品可靠性高。

Description

Low-k芯片封装结构
技术领域
本发明涉及一种Low-k芯片封装结构，属于芯片封装技术领域。
背景技术
在半导体制造行业，摩尔定律一直是鞭策行业向前发展的动力，其中Intel在此方面功不可没。芯片线宽节点主要分为几个阶段：0.18μm阶段，为MOS管开始风靡的时候，为半导体制程的初级阶段，制造的芯片的尺寸相对较大；0.13μm阶段，人们对半导体制程信心十足，寄希望通过减小特征尺寸来缩小芯片面积和成本；这两个阶段为我们常说的微米制程阶段。随着纳米技术的发展，人们的目光远不止于微米技术，开始将半导体制程向纳米尺度进阶，最初出现的纳米是90nm的支撑，但随着单位面积上管芯数量按照摩尔定律的指数增长，相继出现了65纳米、45纳米、32纳米和目前的22纳米技术，这种特征尺寸的急剧缩减，导致介电材料追求低介电损耗常数（通常称为Low-k），以减小电路结构的寄生电阻、电容和电感，同时保证线路具有良好的绝缘性能。通常，低k材料的选择为多孔材料，这导致材料相对较脆，在外加应力的情况下容易碎裂，造成线路失效。
由于低K材料易碎裂的特性，芯片的封装工艺和结构需要做相应的提升以适应产品应用的需求，目前针对低k产品的封装采用还是通常的倒装结构或引线键合方式，造成封装良率损失较多，失效分析的结构都指向键合电极（引线键合和倒装键合）下的介电层碎裂。目前通常的解决方式是将引线键合封装用倒装键合封装，同时在倒装键合前在基板上点上非流动性的底填料胶，其芯片封装结构如图1所示，该底填料胶既有普通底填料胶的性质，也有回流焊剂的性质，因而焊球和基板焊垫之间能形成润湿，该方法的好处是改良了通常的倒装工艺回流时焊球应力导致芯片内部介电层损伤的问题，通过非流动性底填料胶将回流的应力重新分配，不会因为应力集中而导致芯片内层介电层受到损伤。但该方式的最大缺点是因底填料胶的存在导致焊剂的润湿作用不强，而无法保证每个焊球与焊盘结合良好，且因焊剂的存在和回流工艺容易导致底填料胶在固化过程中出现空洞。
综上所述，在Low-k芯片的封装过程中，目前存在的主要有两个方面的问题：
1、采用引线键合和常规倒装工艺，因为工艺过程应力导致芯片电极处应力集中，进而破会易碎裂的Low-K介电层，导致芯片失效；
2、采用非流动性底填料方式倒装工艺存在焊接不良和固化后胶体空洞缺陷，导致产品可靠性低。
发明内容
本发明的目的在于克服上述不足，提供一种Low-k芯片封装结构和封装方法，能够解决芯片封装过程应力集中导致Low-k芯片失效问题，为Low-K芯片的封装提供低成本的封装解决方案。
本发明的目的是这样实现的：一种Low-k芯片封装结构，它包括芯片本体I、芯片电极和芯片表面钝化层，所述芯片本体I外包覆有薄膜层I，所述薄膜层I背面设置有支撑圆片，所述芯片电极经由再布线金属走线转移至芯片周边外的薄膜层I上，再布线金属走线的终端设置有金属柱，所述金属柱外包覆有薄膜层II，金属柱顶端露出薄膜层II，在露出的金属柱顶端设置有金属层，所述金属层上设置有焊球。
所述金属柱采用铜、镍等导电金属，其高度在50μm~100μm之间。
所述金属层为多层金属，其结构为Ni/Au或者Ni/Pd/Au，金属层的厚度不超过5μm。
所述薄膜层I内还嵌置有芯片本体II。
所述再布线金属走线由金属布线层I和金属布线层II组成。
所述薄膜层I和薄膜层II采用非光敏性材料。
所述支撑圆片为硅片或金属片。
所述载体原片采用硅基材或者玻璃基材。
与现有技术相比，本发明的有益效果是：
1、将芯片直接倒装在载体圆片上，不经历回流过程，无应力集中经历，解决了目前Low-k芯片BGA封装中倒装工艺过程应力集中导致芯片失效的问题；
2、利用了圆片级的工艺将芯片电极通过再布线外延至非芯片区，将BGA结构贴装过程产生的应力转移，芯片区域处于不受力状态；
3、利用金属柱技术和结构，实现高功率的载流和电流均匀分配，同时利用铜柱的高度，缓冲来自BGA焊球的应力，使其不到达再布线层。
4、结合圆片级封装工艺和金属柱工艺，在实现Low-k芯片高可靠性封装的同时，还可以实现封装的低成本化；
5、利用薄膜贴膜技术代替现有的包封技术，降低了封装工艺对设备的要求；
6、整合了凸点工艺、倒装工艺和基板工艺，实现了BGA封装的晶圆制造工艺。
附图说明
图1为目前Low-k芯片封装结构的示意图。
图2为本发明Low-k芯片封装结构实施例一的示意图。
图3为本发明Low-k芯片封装结构实施例二的示意图。
图4为本发明Low-k芯片封装结构实施例三的示意图。
其中：
芯片本体1-1
芯片电极1-2
表面钝化层1-3
凸点下金属层1-4
焊球凸点1-5
基板1-6
基板焊盘I1-7
低填料胶1-8
基板焊盘II1-9
BGA焊球1-10
芯片本体I2-1
芯片电极2-2
芯片表面钝化层2-3
薄膜层I2-4
支撑圆片2-5
再布线金属走线2-6
金属柱2-7
薄膜层II2-8
金属层2-9
焊球2-10
芯片本体II2-11
介电层2-12
金属布线层I2-6-1
金属布线层II2-6-2。
具体实施方式
参见图2，本发明一种Low-k芯片封装结构，它包括芯片本体I2-1、芯片电极2-2和芯片表面钝化层2-3，所述芯片本体I2-1外包覆有薄膜层I2-4，所述薄膜层I2-4背面键合设置有支撑圆片2-5，所述芯片电极2-2经由再布线金属走线2-6转移至芯片周边外的薄膜层I2-4上，在再布线金属走线2-6的终端设置有金属柱2-7，所述金属柱2-7外包覆有薄膜层II2-8，金属柱2-7顶端露出薄膜层II2-8，在露出的金属柱2-7顶端设置有金属层2-9，所述金属层2-9上设置有焊球2-10。
参见图3，所述薄膜层I2-4内还嵌置有芯片本体II2-11。
参见图4，所述再布线金属走线2-6由金属布线层I2-6-1和金属布线层II2-6-2组成。
本发明Low-k芯片封装结构的实现过程如下：
步骤一、取一Low-k圆片，将该Low-k圆片切割成单颗芯片。
步骤二、准备一片载体圆片，在载体圆片上通过光刻方式形成对位标志，完成载体圆片上的图形布局。
所述载体圆片可选用硅基材或者玻璃基材，形成对位标志的目的时方便后续芯片倒装，使芯片能保证在理想的位置。
步骤三、在载体圆片上贴上一层临时剥离膜，将步骤一切割成的单颗芯片一一倒装在贴有临时剥离膜的载体圆片上。
所述临时剥离膜双面都具有粘性，可以与载体圆片和后续倒装的芯片形成较好的连接，该剥离膜是热剥离属性或者UV光剥离属性，如果为UV光剥离属性，需要使用玻璃基材或石英基材的载体圆片，因UV光剥离需要使用UV进行照射，因此需选用透明基材以实现UV光的透过。
芯片选用倒装有两个目的，一方面是为了保证不同厚度芯片在后续的工艺中芯片正面在同一平面上，另一方面是芯片正面在重构晶圆上无胶覆盖，以方便进行后续的工艺。
步骤四、在完成芯片倒装的载体圆片上贴上薄膜层I2-4进行包封，在包封过程中将支撑圆片2-5键合到薄膜层I2-4上，然后固化薄膜层I2-4，形成由芯片、薄膜层I2-4和支撑圆片2-5组成的重构晶圆。
所述支撑圆片2-5为硅片或金属片，包封时利用薄膜层I2-4在加热情况下良好的流动性，保证了圆片表面的平整性。
步骤五、利用UV照射或者热剥离的方式将上述重构晶圆与载体圆片进行剥离，并将重构晶圆的芯片表面清洗干净，露出芯片电极2-2。
步骤六、通过圆片级工艺的光刻、溅射或电镀等方式在薄膜层I2-4和芯片表面完成单层或多层再布线金属走线2-6，通过再布线金属走线2-6将芯片电极2-2引导至芯片周边区域（不含芯片区域）。
步骤七、在完成的再布线金属走线2-6的终端通过光刻或电镀的方式形成金属柱2-7。
所述金属柱2-7为铜、镍等导电金属，金属柱2-7的高度可按照结构需求进行调节，高度应不低于50μm，通常在50μm~100μm之间。金属柱2-7在此有两方面的作用，一是减小电流拥挤效应，即可将电流均匀分布，从而减小电迁移现象的发生；另一方面，利用金属柱2-7的高度缓冲来自焊球2-10的应力，从而保护Low-k芯片。
步骤八：在形成金属柱2-7的重构晶圆表面贴上薄膜层II2-8进行包封并固化，然后利用激光烧蚀的方式将金属柱顶端的薄膜材料刻蚀掉，形成金属柱2-7的完整或部分开口，使金属柱顶端露出薄膜层II2-8。
所述薄膜层I2-4和薄膜层II2-8为非光敏性树脂绝缘类材料。
步骤九、在露出薄膜层II2-8的金属柱2-7顶端镀上金属层2-9。
所述金属层2-9为单层或多层金属，通常的结构为Ni/Au或者Ni/Pd/Au，金属层2-9的厚度不宜超过5μm，其目的时阻挡焊料中的锡和铜之间的相互扩散，提升产品的可靠性。
步骤十、通过印刷或者植球的方式在所述金属层2-9上形成BGA焊球2-10，最后将形成BGA焊球的重构晶圆切割成单颗BGA封装体。

Claims (8)

1. 一种Low-k芯片封装结构，其特征在于：它包括芯片本体I（2-1）、芯片电极（2-2）和芯片表面钝化层（2-3），所述芯片本体I（2-1）外包覆有薄膜层I（2-4），所述薄膜层I（2-4）背面设置有支撑圆片（2-5），所述芯片电极（2-2）经由再布线金属走线（2-6）转移至芯片周边外的薄膜层I（2-4）上，再布线金属走线（2-6）的终端设置有金属柱（2-7），所述金属柱（2-7）外包覆有薄膜层II（2-8），金属柱（2-7）顶端露出薄膜层II（2-8），在露出的金属柱（2-7）顶端设置有金属层（2-9），所述金属层（2-9）上设置有焊球（2-10）。
2.根据权利要求1所述的一种Low-k芯片封装结构，其特征在于：所述金属柱（2-7）采用铜、铜/镍等导电金属，其高度在50μm~100μm之间。
3.根据权利要求1或2所述的一种Low-k芯片封装结构，其特征在于：所述金属层（2-9）为多层金属，其结构为Ni/Au或者Ni/Pd/Au，金属层（2-9）的厚度不超过5μm。
4.根据权利要求1或2所述的一种Low-k芯片封装结构，其特征在于：所述薄膜层I（2-4）内还嵌置有芯片本体II（2-11）。
5.根据权利要求1或2所述的一种Low-k芯片封装结构，其特征在于：所述再布线金属走线（2-6）由金属布线层I（2-6-1）和金属布线层II（2-6-2）组成。
6.根据权利要求1或2所述的一种Low-k芯片封装结构，其特征在于：所述薄膜层I（2-4）和薄膜层II（2-8）采用非光敏性材料。
7.根据权利要求1或2所述的一种Low-k芯片封装结构，其特征在于：所述支撑圆片（2-5）为硅片或金属片。
8.根据权利要求1或2所述的一种Low-k芯片封装结构，其特征在于：所述载体原片采用硅基材或者玻璃基材。
CN2011102002120A 2011-07-18 2011-07-18 Low-k芯片封装结构 Pending CN102244061A (zh)

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