CN102208964A - System and method for realizing log likelihood ratio in digital system - Google Patents

System and method for realizing log likelihood ratio in digital system Download PDF

Info

Publication number
CN102208964A
CN102208964A CN2011101373231A CN201110137323A CN102208964A CN 102208964 A CN102208964 A CN 102208964A CN 2011101373231 A CN2011101373231 A CN 2011101373231A CN 201110137323 A CN201110137323 A CN 201110137323A CN 102208964 A CN102208964 A CN 102208964A
Authority
CN
China
Prior art keywords
prime
llr
centerdot
sign
median
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2011101373231A
Other languages
Chinese (zh)
Inventor
姜奇渊
翟春华
卢海涛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen ZTE Microelectronics Technology Co Ltd
Original Assignee
ZTE Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ZTE Corp filed Critical ZTE Corp
Priority to CN2011101373231A priority Critical patent/CN102208964A/en
Publication of CN102208964A publication Critical patent/CN102208964A/en
Pending legal-status Critical Current

Links

Images

Landscapes

  • Error Detection And Correction (AREA)

Abstract

The invention discloses a system for realizing a log likelihood ratio in a digital system. In the system, a log likelihood ratio (LLR) core processing unit is used for obtaining corresponding LLR intermediate values under different modulation modes according to ZN and a computational formula for the LLR intermediate values under the different modulation modes, and outputting the LLR intermediate values to a noise normalization unit; and the noise normalization unit is used for obtaining a final LLR value according to the LLR intermediate values. The invention also discloses a method for realizing the log likelihood radio in the digital system. The method comprises that: the LLR core processing unit obtains the corresponding LLR intermediate values under the different modulation modes according to the ZN and the computational formula for the LLR intermediate values under the different modulation modes, and outputs the LLR intermediate values to the noise normalization unit; and the noise normalization unit obtains the final LLR value according to the LLR intermediate values. By the system and the method provided by the invention, not only the bit error rate of signal reception and demodulation can be reduced, but also the problems of LLR computational complexity and demodulation performance can be combined.

Description

The realization system and method for log-likelihood ratio in a kind of digital system
Technical field
The present invention is mainly used in digital communicating field, relates in particular in a kind of digital system z=Ax+N oSignal is asked the realization system and method for log-likelihood ratio (LLR).
Background technology
Radio digital communication to broadband, high speed development, can not satisfy the demand by basic low-order-modulated mode.In order to improve spectrum efficiency, satisfy the business demand of high power system capacity and high data rate, increasing communication system adopts high-order modulating.But exponent number is high more, and high more for the receptivity requirement of receiver, the error rate is also just high more.
Because the influence of channel circumstance can make the reception constellation point with respect to the standard constellation point certain phase place rotation and expansion be arranged; The noise can make the position that receives constellation point uncertain.Suppose that received signal is y=hx+n o, then receiving system generally all can be earlier according to following formula z=h *Y=h *Hx+h *N o=Ax+N oEliminate the influence of the rotation of phase place, wherein, y represents the signal that receives, and h represents channel impulse response, and x represents the data that send, n oExpression sends the noise of introducing in the data procedures, h *The conjugate transpose of expression h, A represents h *With the product of h, the A that occurs in the follow-up formula of this paper also is the implication here, N oExpression h *And n oProduct; And then carry out the calculating of LLR value, to reduce the error rate of signal receiving demodulation.Though yet this scheme can reduce the error rate of signal receiving demodulation to a certain extent, can not take into account the problem of LLR computation complexity and demodulation performance two aspects.
Summary of the invention
In view of this, main purpose of the present invention is to provide the realization system and method for log-likelihood ratio in a kind of digital system, can not only reduce the error rate of signal receiving demodulation, and can take into account the problem of LLR computation complexity and demodulation performance two aspects.
For achieving the above object, technical scheme of the present invention is achieved in that
The realization system of log-likelihood ratio in a kind of digital system, this system comprises: LLR pretreatment unit, LLR core processing unit and noise normalized unit; Wherein,
Described LLR pretreatment unit is used for the Z signal of input is carried out obtaining Z after the preliminary treatment N, the formula of employing is z N=cz=c (Re{z}+Im{z}); Wherein, z=Ax+N o, Re{z} represents the real part of plural Z, and Im{z} represents the imaginary part of plural Z, and c is the normalization coefficient of the constellation point of different modulating pattern;
Described LLR core processing unit is used for according to Z NWith the computing formula of LLR median under the different modulating pattern, obtain LLR median corresponding under the different modulating pattern and export to noise normalization unit, described LLR median be LLR (Re, i) or LLR (Im, i);
Described noise normalization unit is used for obtaining final LLR value according to the LLR median, the computing formula of final LLR value be LLR=S * LLR (Re, i) or LLR=S * LLR (Im, i).
Wherein, described LLR pretreatment unit, be further used for adopting parallel-to-serial converter to obtain the Z median to the real part of Z signal and the imaginary part of input, for the Z median according to different modulating pattern corresponding selection square root numerical value after, adopt the displacement equivalent electric circuit that Z is exported in the square root numerical value of Z median and the corresponding selection back of multiplying each other NGive the LLR core processing unit.
Wherein, described LLR core processing unit is further used for adopting the displacement equivalent electric circuit to realize multiply operation, adopts the addition/subtraction circuit to realize compare operation, the corresponding data of computing formula corresponding selection according to LLR median under the different modulating pattern are exported, and obtain the LLR median.
Wherein, described LLR pretreatment unit, the square root numerical value that is further used for corresponding selection is specially:
Figure BDA0000063744310000021
With
Figure BDA0000063744310000022
Wherein,
2 = 2 0 + 2 - 2 + 2 - 3 + 2 - 5 ;
10 = 2 1 + 2 0 + 2 - 3 + 2 - 5 ;
42 = 2 2 + 2 1 + 2 - 1 + 2 - 5 .
Wherein, described LLR core processing unit, the computing formula that is further used for LLR median under the different modulating pattern comprises:
Make z N=cz=c (Re{z}+Im{z}), then:
A, for the BPSK modulating mode:
Make z '=Re{z N, LLR (Re, 0)=Sz ' then;
B, for the QPSK modulating mode:
Make z '=Re{z N, LLR (Re, 0)=Sz ' is then arranged;
Make z '=Im{z N, LLR (Im, 0)=z ' is then arranged;
C, for the 16QAM modulating mode:
If make z '=Re{z N, then have:
LLR ( Re , 0 ) = S · z ′ | z ′ | ≤ 2 A S · sign ( z ′ ) 2 ( | z ′ | - A ) | z ′ | > 2 A ;
LLR(Re,1)=S·(2A-|z′|);
If make z ' Im{z N, then have:
LLR ( Im , 0 ) = S · z ′ | z ′ | ≤ 2 A S · sign ( z ′ ) 2 ( | z ′ | - A ) | z ′ | > 2 A ;
LLR(Im,1)=S·(2A-|z′|);
D, for the 64QAM modulating mode:
If make z '=Re{z N, then have
LLR ( Re , 0 ) = S &CenterDot; sign ( z &prime; ) | z &prime; | | z &prime; | < 2 A S &CenterDot; sign ( z &prime; ) 2 ( | z &prime; | - A ) 2 A < | z &prime; | < 4 A S &CenterDot; sign ( z &prime; ) 3 ( | z &prime; | - 2 A ) 4 A < | z &prime; | < 6 A S &CenterDot; sign ( z &prime; ) 4 ( | z &prime; | - 3 A ) | z &prime; | > 6 A ;
If make z "=4A-|z ' |, then have:
LLR ( Re , 1 ) = S &CenterDot; z &prime; &prime; | z &prime; &prime; | &le; 2 A S &CenterDot; sign ( z &prime; &prime; ) 2 ( | z &prime; &prime; | - A ) | z &prime; &prime; | > 2 A ;
LLR(Re,2)=S·(2A-|z″|);
If make z '=Im{z N, then have
LLR ( Im , 0 ) = S &CenterDot; sign ( z &prime; ) | z &prime; | | z &prime; | < 2 A S &CenterDot; sign ( z &prime; ) 2 ( | z &prime; | - A ) 2 A < | z &prime; | < 4 A S &CenterDot; sign ( z &prime; ) 3 ( | z &prime; | - 2 A ) 4 A < | z &prime; | < 6 A S &CenterDot; sign ( z &prime; ) 4 ( | z &prime; | - 3 A ) | z &prime; | > 6 A ;
Make z "=4A-|z ' |, then have:
LLR ( Im , 1 ) = S &CenterDot; z &prime; &prime; | z &prime; &prime; | &le; 2 A S &CenterDot; &Phi; ( z &prime; &prime; ) 2 ( | z &prime; &prime; | - A ) | z &prime; &prime; | > 2 A ;
LLR(Im,2)=S·(2A-|z″|)。
The implementation method of log-likelihood ratio in a kind of digital system, this method comprises:
The LLR pretreatment unit carries out obtaining Z after the preliminary treatment to the Z signal of input N, the formula of employing is z N=cz=c (Re{z}+Im{z}) is with Z NExport to the LLR core processing unit; Described z=Ax+N o, described Re{z} represents the real part of plural Z, and described Im{z} represents the imaginary part of plural Z, and described c is the normalization coefficient of the constellation point of different modulating pattern;
The LLR core processing unit is according to Z NWith the computing formula of LLR median under the different modulating pattern, obtain LLR median corresponding under the different modulating pattern and export to noise normalization unit, described LLR median be LLR (Re, i) or LLR (Im, i);
Noise normalization unit obtains final LLR value according to the LLR median, the computing formula of final LLR value be LLR=S * LLR (Re, i) or LLR=S * LLR (Im, i).
Wherein, described Z signal to input carries out obtaining Z after the preliminary treatment NSpecifically comprise: the real part of Z signal and imaginary part to input adopt parallel-to-serial converter to obtain the Z median, for the Z median according to different modulating pattern corresponding selection square root numerical value after, adopt the displacement equivalent electric circuit that Z is exported in the square root numerical value of Z median and the corresponding selection back of multiplying each other N
Wherein, the square root numerical value of corresponding selection is specially:
Figure BDA0000063744310000043
With Wherein,
2 = 2 0 + 2 - 2 + 2 - 3 + 2 - 5 ;
10 = 2 1 + 2 0 + 2 - 3 + 2 - 5 ;
42 = 2 2 + 2 1 + 2 - 1 + 2 - 5 .
Wherein, the computing formula of LLR median comprises under the different modulating pattern:
Make z N=cz=c (Re{z}+Im{z}), then:
A, for the BPSK modulating mode:
Make z '=Re{z N, LLR (Re, 0)=Sz ' then;
B, for the QPSK modulating mode:
Make z '=Re{z N, LLR (Re, 0)=Sz ' is then arranged;
Make z '=Im{z N, LLR (Im, 0)=z ' is then arranged;
C, for the 16QAM modulating mode:
If make z '=Re{z N, then have:
LLR ( Re , 0 ) = S &CenterDot; z &prime; | z &prime; | &le; 2 A S &CenterDot; sign ( z &prime; ) 2 ( | z &prime; | - A ) | z &prime; | > 2 A ;
LLR(Re,1)=S·(2A-|z′|);
If make z ' Im{z N, then have:
LLR ( Im , 0 ) = S &CenterDot; z &prime; | z &prime; | &le; 2 A S &CenterDot; sign ( z &prime; ) 2 ( | z &prime; | - A ) | z &prime; | > 2 A ;
LLR(Im,1)=S·(2A-|z′|);
D, for the 64QAM modulating mode:
If make z '=Re{z N, then have
LLR ( Re , 0 ) = S &CenterDot; sign ( z &prime; ) | z &prime; | | z &prime; | < 2 A S &CenterDot; sign ( z &prime; ) 2 ( | z &prime; | - A ) 2 A < | z &prime; | < 4 A S &CenterDot; sign ( z &prime; ) 3 ( | z &prime; | - 2 A ) 4 A < | z &prime; | < 6 A S &CenterDot; sign ( z &prime; ) 4 ( | z &prime; | - 3 A ) | z &prime; | > 6 A ;
If make z "=4A-|z ' |, then have:
LLR ( Re , 1 ) = S &CenterDot; z &prime; &prime; | z &prime; &prime; | &le; 2 A S &CenterDot; sign ( z &prime; &prime; ) 2 ( | z &prime; &prime; | - A ) | z &prime; &prime; | > 2 A ;
LLR(Re,2)=S·(2A-|z″|);
If make z '=Im{z N, then have
LLR ( Im , 0 ) = S &CenterDot; sign ( z &prime; ) | z &prime; | | z &prime; | < 2 A S &CenterDot; sign ( z &prime; ) 2 ( | z &prime; | - A ) 2 A < | z &prime; | < 4 A S &CenterDot; sign ( z &prime; ) 3 ( | z &prime; | - 2 A ) 4 A < | z &prime; | < 6 A S &CenterDot; sign ( z &prime; ) 4 ( | z &prime; | - 3 A ) | z &prime; | > 6 A ;
Make z "=4A-|z ' |, then have:
LLR ( Im , 1 ) = S &CenterDot; z &prime; &prime; | z &prime; &prime; | &le; 2 A S &CenterDot; &Phi; ( z &prime; &prime; ) 2 ( | z &prime; &prime; | - A ) | z &prime; &prime; | > 2 A ;
LLR(Im,2)=S·(2A-|z″|)。
LLR pretreatment unit of the present invention is used for the Z signal of input is carried out obtaining Z after the preliminary treatment N, the formula of employing is z N=cz=c (Re{z}+Im{z}); Wherein, z=Ax+N o, Re{z} represents the real part of plural Z, and Im{z} represents the imaginary part of plural Z, and c is the normalization coefficient of the constellation point of different modulating pattern; The LLR core processing unit is used for according to Z NWith the computing formula of LLR median under the different modulating pattern, obtain LLR median corresponding under the different modulating pattern and export to noise normalization unit, described LLR median be LLR (Re, i) or LLR (Im, i); Noise normalization unit is used for obtaining final LLR value according to the LLR median, the computing formula of final LLR value be LLR=S * LLR (Re, i) or LLR=S * LLR (Im, i).
Adopt of the present invention to z=Ax+N oSignal is asked the scheme of LLR value, simplified the calculating of LLR value, and be applicable to the communication system of multiple modulating mode BPSK/QPSK/16QAM/64QAM, can not only reduce the error rate of signal receiving demodulation, and can take into account the problem of LLR computation complexity and demodulation performance two aspects, that is to say, not only reduced the error rate of Data Receiving demodulation in the digital communication, and simplifying the demodulation performance that has improved system on the LLR value complexity calculating basis.
Description of drawings
Fig. 1 realizes the system configuration schematic diagram of system for LLR of the present invention;
Fig. 2 realizes the electrical block diagram of LLR pretreatment unit one example of system for LLR of the present invention;
Fig. 3 realizes the electrical block diagram of LLR core processing unit one example of system for LLR of the present invention.
Embodiment
Basic thought of the present invention is: the LLR pretreatment unit is used for the Z signal of input is carried out obtaining Z after the preliminary treatment N, the formula of employing is z N=cz=c (Re{z}+Im{z}); Wherein, z=Ax+N o, Re{z} represents the real part of plural Z, and Im{z} represents the imaginary part of plural Z, and c is the normalization coefficient of the constellation point of different modulating pattern; The LLR core processing unit is used for according to Z NWith the computing formula of LLR median under the different modulating pattern, obtain LLR median corresponding under the different modulating pattern and export to noise normalization unit, described LLR median be LLR (Re, i) or LLR (Im, i); Noise normalization unit is used for obtaining final LLR value according to the LLR median, the computing formula of final LLR value be LLR=S * LLR (Re, i) or LLR=S * LLR (Im, i).
Be described in further detail below in conjunction with the enforcement of accompanying drawing technical scheme.
The realization system of log-likelihood ratio in a kind of digital system mainly comprises following content:
As shown in Figure 1, this system comprises: LLR pretreatment unit, LLR core processing unit and noise normalized unit.Wherein, the LLR pretreatment unit is used for the Z signal of input is carried out obtaining Z after the preliminary treatment N, the formula of employing is z N=cz=c (Re{z}+Im{z}); Wherein, z=Ax+N o, Re{z} represents the real part of plural Z, and Im{z} represents the imaginary part of plural Z, and c is the normalization coefficient of the constellation point of different modulating pattern.Here, the Re in the literary composition is meant real part, and the Im in the literary composition is meant imaginary part, give an example at the relation of real part and imaginary part and plural Z, and such as plural z=a+bi, Re (z)=a, Im (z)=b.
The LLR core processing unit is used for according to Z NWith the computing formula of LLR median under the different modulating pattern, obtain LLR median corresponding under the different modulating pattern and export to noise normalization unit, here, LLR median LLRi_temp be LLR (Re, i) or LLR (Im, i), i=0,1,2,3,4,5.
Noise normalization unit is used for obtaining final LLR value according to the LLR median, the computing formula of final LLR value be LLR=S * LLR (Re, i) or LLR=S * LLR (Im, i).
Further, the LLR pretreatment unit, be used for adopting parallel-to-serial converter to obtain the Z median to the real part of Z signal and the imaginary part of input, for the Z median according to different modulating pattern corresponding selection square root numerical value after, adopt the displacement equivalent electric circuit that Z is exported in the square root numerical value of Z median and the corresponding selection back of multiplying each other NGive the LLR core processing unit.
Here it is to be noted: prior art is the computing of deciding coefficient to the normalization operation of input data, and the present invention all will import the shifting function that data conversion is data in order to simplify arithmetic logic.
Further, the LLR core processing unit is used for adopting earlier the displacement equivalent electric circuit to realize multiply operation, adopts the addition/subtraction circuit to realize compare operation then, exports according to the corresponding data of different modulating pattern corresponding selection at last, obtains the LLR median.
The implementation method of log-likelihood ratio in a kind of digital system, this method mainly comprises following content:
The LLR pretreatment unit carries out obtaining Z after the preliminary treatment to the Z signal of input N, the formula of employing is z N=cz=c (Re{z}+Im{z}); Wherein, z=Ax+N o, Re{z} represents the real part of plural Z, and Im{z} represents the imaginary part of plural Z, and c is the normalization coefficient of the constellation point of different modulating pattern;
The LLR core processing unit is according to Z NWith the computing formula of LLR median under the different modulating pattern, obtain LLR median corresponding under the different modulating pattern and export to noise normalization unit, here, LLR median LLR_temp be LLR (Re, i) or LLR (Im, i), i=0,1,2,3,4,5;
Noise normalization unit is used for obtaining final LLR value according to the LLR median, the computing formula of final LLR value be LLR=S * LLR (Re, i) or LLR=S * LLR (Im, i).
In sum, adopt the present invention, this to z=Ax+N oSignal is asked the scheme of LLR value, has reduced the error rate of Data Receiving demodulation in the digital communication, has improved the demodulation performance joint; By variation, make the LLR that is applicable to multiple modulating mode BPSK/QPSK/16QAM/64QAM realize that the hardware implementation structure of system is more unified to the LLR computing formula.
Below to the present invention's elaboration of giving an example.
Fig. 2 realizes the electrical block diagram of LLR pretreatment unit one example of system for LLR of the present invention, and the LLR pretreatment unit at first adopts parallel-to-serial converter to obtain Z median z_temp value to real part and the imaginary part of z, to carry out resource multiplex; Then the z_temp value is multiplied by respectively
Figure BDA0000063744310000081
With
Figure BDA0000063744310000082
Wherein multiply operation adopts the displacement equivalent electric circuit to realize; Select wherein one the tunnel to export according to modulating mode at last, obtain z N=cz exports to the LLR core processing unit.Wherein,
Figure BDA0000063744310000083
With
Figure BDA0000063744310000084
Quantification as shown in the following Table 1.
Table 1
Fig. 3 realizes the electrical block diagram of LLR core processing unit one example of system for LLR of the present invention, the LLR core processing unit at first adopts the displacement equivalent electric circuit to realize multiply operation, the addition/subtraction circuit is realized compare operation then, export according to the corresponding data of the different choice of modulation system at last, obtain the median LLRi_temp value under the LLR different modulating pattern.The computing formula of the median under the different modulating pattern is as follows:
Make z N=cz=c (Re{z}+Im{z}), then:
1, for the BPSK modulating mode:
Make z '=Re{z N, LLR (Re, 0)=Sz ' then;
2, for the QPSK modulating mode:
Make z '=Re{z N, LLR (Re, 0)=Sz ' is then arranged;
Make z '=Im{z N, LLR (Im, 0)=z ' is then arranged;
3, for the 16QAM modulating mode:
If make z '=Re{z N, then have:
LLR ( Re , 0 ) = S &CenterDot; z &prime; | z &prime; | &le; 2 A S &CenterDot; sign ( z &prime; ) 2 ( | z &prime; | - A ) | z &prime; | > 2 A ;
LLR(Re,1)=S·(2A-|z′|);
If make z '=Im{z N, then have:
LLR ( Im , 0 ) = S &CenterDot; z &prime; | z &prime; | &le; 2 A S &CenterDot; sign ( z &prime; ) 2 ( | z &prime; | - A ) | z &prime; | > 2 A ;
LLR(Im,1)=S·(2A-|z′|);
4, for the 64QAM modulating mode:
If make z '=Re{z N, then have
LLR ( Re , 0 ) = S &CenterDot; sign ( z &prime; ) | z &prime; | | z &prime; | < 2 A S &CenterDot; sign ( z &prime; ) 2 ( | z &prime; | - A ) 2 A < | z &prime; | < 4 A S &CenterDot; sign ( z &prime; ) 3 ( | z &prime; | - 2 A ) 4 A < | z &prime; | < 6 A S &CenterDot; sign ( z &prime; ) 4 ( | z &prime; | - 3 A ) | z &prime; | > 6 A ;
If make z "=4A-|z ' |, then have:
LLR ( Re , 1 ) = S &CenterDot; z &prime; &prime; | z &prime; &prime; | &le; 2 A S &CenterDot; sign ( z &prime; &prime; ) 2 ( | z &prime; &prime; | - A ) | z &prime; &prime; | > 2 A ;
LLR(Re,2)=S·(2A-|z″|);
If make z '=Im{z N, then have
LLR ( Im , 0 ) = S &CenterDot; sign ( z &prime; ) | z &prime; | | z &prime; | < 2 A S &CenterDot; sign ( z &prime; ) 2 ( | z &prime; | - A ) 2 A < | z &prime; | < 4 A S &CenterDot; sign ( z &prime; ) 3 ( | z &prime; | - 2 A ) 4 A < | z &prime; | < 6 A S &CenterDot; sign ( z &prime; ) 4 ( | z &prime; | - 3 A ) | z &prime; | > 6 A ;
Make z "=4A-|z ' |, then have:
LLR ( Im , 1 ) = S &CenterDot; z &prime; &prime; | z &prime; &prime; | &le; 2 A S &CenterDot; &Phi; ( z &prime; &prime; ) 2 ( | z &prime; &prime; | - A ) | z &prime; &prime; | > 2 A ;
LLR(Im,2)=S·(2A-|z″|)。
Among Fig. 3, corresponding implication is as shown in the following Table 2 under the different modulating pattern for LLR0_temp, LLR1_temp and LLR2_temp:
Figure BDA0000063744310000105
Also need calculate at the LLR core processing unit:
Figure BDA0000063744310000106
S is a variable that defines in the computational process, and the S that adopts in the noise normalized unit refers to is exactly the S here.
If LLR pretreatment unit, LLR core processing unit adopt above-mentioned as Fig. 2, specific implementation shown in Figure 3 respectively, then Dui Ying noise normalized unit mainly adopts division circuit to realize following function:
LLR(0)=S×LLR(Re,0)
LLR(1)=S×LLR(Im,0)
LLR(2)=S×LLR(Re,1)
LLR(3)=S×LLR(Im,1)
LLR(4)=S×LLR(Re,2)
LLR(5)=S×LLR(Im,2)
Wherein S = 4 c 2 N o .
Here it is to be noted: for z=Ax+N oSignal also obtains one of them bit b by following formula kThe LLR value:
LLR k = ln P ( b k = 1 | z ) P ( b k = 0 | z )
= ln P ( b k = 1 ) P ( z | b k = 1 ) P ( b k = 0 ) P ( z | b k = 0 )
= ln P ( z | b k = 1 ) P ( z | b k = 0 )
= ln &Sigma; x &Element; C &OverBar; k 1 P ( z | x ) &Sigma; x &Element; C &OverBar; k 0 P ( z | x )
= ln &Sigma; x &Element; C &OverBar; k 1 P ( z | x ) - ln &Sigma; x &Element; C &OverBar; k 0 P ( z | x )
&ap; ln max x &Element; C &OverBar; k 1 { P ( z | x ) } - ln max x &Element; C &OverBar; k 0 { P ( z | x ) }
&ap; 1 N 0 min x &Element; C &OverBar; k 0 ( z - x ) 2 - 1 N 0 min x &Element; C &OverBar; k 1 ( z - x ) 2
Wherein
Figure BDA0000063744310000119
Be that all k positions are the set of 0 constellation point; Be that all k positions are the set of 1 constellation point.X (data that representative sends) is distributed on the integer lattice, can determine the expression formula of each interval LLR value according to the input of z (data that representative receives).The above-mentioned a series of formula mentioned of the present invention are equivalent result of formula here, do not do and give unnecessary details.
The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.

Claims (9)

1. the realization system of log-likelihood ratio in the digital system is characterized in that this system comprises: LLR pretreatment unit, LLR core processing unit and noise normalized unit; Wherein,
Described LLR pretreatment unit is used for the Z signal of input is carried out obtaining Z after the preliminary treatment N, the formula of employing is z N=cz=c (Re{z}+Im{z}); Wherein, z=Ax+N o, Re{z} represents the real part of plural Z, and Im{z} represents the imaginary part of plural Z, and c is the normalization coefficient of the constellation point of different modulating pattern;
Described LLR core processing unit is used for according to Z NWith the computing formula of LLR median under the different modulating pattern, obtain LLR median corresponding under the different modulating pattern and export to noise normalization unit, described LLR median be LLR (Re, i) or LLR (Im, i);
Described noise normalization unit is used for obtaining final LLR value according to the LLR median, the computing formula of final LLR value be LLR=S * LLR (Re, i) or LLR=S * LLR (Im, i).
2. system according to claim 1, it is characterized in that, described LLR pretreatment unit, be further used for adopting parallel-to-serial converter to obtain the Z median to the real part of Z signal and the imaginary part of input, for the Z median according to different modulating pattern corresponding selection square root numerical value after, adopt the displacement equivalent electric circuit that Z is exported in the square root numerical value of Z median and the corresponding selection back of multiplying each other NGive the LLR core processing unit.
3. system according to claim 1, it is characterized in that, described LLR core processing unit, be further used for adopting the displacement equivalent electric circuit to realize multiply operation, adopt the addition/subtraction circuit to realize compare operation, the corresponding data of computing formula corresponding selection according to LLR median under the different modulating pattern are exported, and obtain the LLR median.
4. system according to claim 2 is characterized in that, described LLR pretreatment unit, and the square root numerical value that is further used for corresponding selection is specially:
Figure FDA0000063744300000011
With
Figure FDA0000063744300000012
Wherein,
2 = 2 0 + 2 - 2 + 2 - 3 + 2 - 5 ;
10 = 2 1 + 2 0 + 2 - 3 + 2 - 5 ;
42 = 2 2 + 2 1 + 2 - 1 + 2 - 5 .
5. system according to claim 3 is characterized in that, described LLR core processing unit, and the computing formula that is further used for LLR median under the different modulating pattern comprises:
Make z N=cz=c (Re{z}+Im{z}), then:
A, for the BPSK modulating mode:
Make z '=Re{z N, LLR (Re, 0)=Sz ' then;
B, for the QPSK modulating mode:
Make z '=Re{z N, LLR (Re, 0)=Sz ' is then arranged;
Make z '=Im{z N, LLR (Im, 0)=z ' is then arranged;
C, for the 16QAM modulating mode:
If make z '=Re{z N, then have:
LLR ( Re , 0 ) = S &CenterDot; z &prime; | z &prime; | &le; 2 A S &CenterDot; sign ( z &prime; ) 2 ( | z &prime; | - A ) | z &prime; | > 2 A ;
LLR(Re,1)=S·(2A-|z′|);
If make z ' Im{z N, then have:
LLR ( Im , 0 ) = S &CenterDot; z &prime; | z &prime; | &le; 2 A S &CenterDot; sign ( z &prime; ) 2 ( | z &prime; | - A ) | z &prime; | > 2 A ;
LLR(Im,1)=S·(2A-|z′|);
D, for the 64QAM modulating mode:
If make z '=Re{z N, then have
LLR ( Re , 0 ) = S &CenterDot; sign ( z &prime; ) | z &prime; | | z &prime; | < 2 A S &CenterDot; sign ( z &prime; ) 2 ( | z &prime; | - A ) 2 A < | z &prime; | < 4 A S &CenterDot; sign ( z &prime; ) 3 ( | z &prime; | - 2 A ) 4 A < | z &prime; | < 6 A S &CenterDot; sign ( z &prime; ) 4 ( | z &prime; | - 3 A ) | z &prime; | > 6 A ;
If make z "=4A-|z ' |, then have:
LLR ( Re , 1 ) = S &CenterDot; z &prime; &prime; | z &prime; &prime; | &le; 2 A S &CenterDot; sign ( z &prime; &prime; ) 2 ( | z &prime; &prime; | - A ) | z &prime; &prime; | > 2 A ;
LLR(Re,2)=S·(2A-|z″|);
If make z '=Im{z N, then have
LLR ( Im , 0 ) = S &CenterDot; sign ( z &prime; ) | z &prime; | | z &prime; | < 2 A S &CenterDot; sign ( z &prime; ) 2 ( | z &prime; | - A ) 2 A < | z &prime; | < 4 A S &CenterDot; sign ( z &prime; ) 3 ( | z &prime; | - 2 A ) 4 A < | z &prime; | < 6 A S &CenterDot; sign ( z &prime; ) 4 ( | z &prime; | - 3 A ) | z &prime; | > 6 A ;
Make z "=4A-|z ' |, then have:
LLR ( Im , 1 ) = S &CenterDot; z &prime; &prime; | z &prime; &prime; | &le; 2 A S &CenterDot; &Phi; ( z &prime; &prime; ) 2 ( | z &prime; &prime; | - A ) | z &prime; &prime; | > 2 A ;
LLR(Im,2)=S·(2A-|z″|)。
6. the implementation method of log-likelihood ratio in the digital system is characterized in that this method comprises:
The LLR pretreatment unit carries out obtaining Z after the preliminary treatment to the Z signal of input N, the formula of employing is z N=cz=c (Re{z}+Im{z}) is with Z NExport to the LLR core processing unit; Described z=Ax+N o, described Re{z} represents the real part of plural Z, and described Im{z} represents the imaginary part of plural Z, and described c is the normalization coefficient of the constellation point of different modulating pattern;
The LLR core processing unit is according to Z NWith the computing formula of LLR median under the different modulating pattern, obtain LLR median corresponding under the different modulating pattern and export to noise normalization unit, described LLR median be LLR (Re, i) or LLR (Im, i);
Noise normalization unit obtains final LLR value according to the LLR median, the computing formula of final LLR value be LLR=S * LLR (Re, i) or LLR=S * LLR (Im, i).
7. method according to claim 6 is characterized in that, described Z signal to input carries out obtaining Z after the preliminary treatment NSpecifically comprise: the real part of Z signal and imaginary part to input adopt parallel-to-serial converter to obtain the Z median, for the Z median according to different modulating pattern corresponding selection square root numerical value after, adopt the displacement equivalent electric circuit that Z is exported in the square root numerical value of Z median and the corresponding selection back of multiplying each other N
8. method according to claim 7 is characterized in that, the square root numerical value of corresponding selection is specially:
Figure FDA0000063744300000033
With
Figure FDA0000063744300000034
Wherein,
2 = 2 0 + 2 - 2 + 2 - 3 + 2 - 5 ;
10 = 2 1 + 2 0 + 2 - 3 + 2 - 5 ;
42 = 2 2 + 2 1 + 2 - 1 + 2 - 5 .
9. according to each described method in the claim 6 to 8, it is characterized in that the computing formula of LLR median comprises under the different modulating pattern:
Make z N=cz=c (Re{z}+Im{z}), then:
A, for the BPSK modulating mode:
Make z '=Re{z N, LLR (Re, 0)=Sz ' then;
B, for the QPSK modulating mode:
Make z '=Re{z N, LLR (Re, 0)=Sz ' is then arranged;
Make z '=Im{z N, LLR (Im, 0)=z ' is then arranged;
C, for the 16QAM modulating mode:
If make z '=Re{z N, then have:
LLR ( Re , 0 ) = S &CenterDot; z &prime; | z &prime; | &le; 2 A S &CenterDot; sign ( z &prime; ) 2 ( | z &prime; | - A ) | z &prime; | > 2 A ;
LLR(Re,1)=S·(2A-|z′|);
If make z ' Im{z N, then have:
LLR ( Im , 0 ) = S &CenterDot; z &prime; | z &prime; | &le; 2 A S &CenterDot; sign ( z &prime; ) 2 ( | z &prime; | - A ) | z &prime; | > 2 A ;
LLR(Im,1)=S·(2A-|z′|);
D, for the 64QAM modulating mode:
If make z '=Re{z N, then have
LLR ( Re , 0 ) = S &CenterDot; sign ( z &prime; ) | z &prime; | | z &prime; | < 2 A S &CenterDot; sign ( z &prime; ) 2 ( | z &prime; | - A ) 2 A < | z &prime; | < 4 A S &CenterDot; sign ( z &prime; ) 3 ( | z &prime; | - 2 A ) 4 A < | z &prime; | < 6 A S &CenterDot; sign ( z &prime; ) 4 ( | z &prime; | - 3 A ) | z &prime; | > 6 A ;
If make z "=4A-|z ' |, then have:
LLR ( Re , 1 ) = S &CenterDot; z &prime; &prime; | z &prime; &prime; | &le; 2 A S &CenterDot; sign ( z &prime; &prime; ) 2 ( | z &prime; &prime; | - A ) | z &prime; &prime; | > 2 A ;
LLR(Re,2)=S·(2A-|z″|);
If make z '=Im{z N, then have
LLR ( Im , 0 ) = S &CenterDot; sign ( z &prime; ) | z &prime; | | z &prime; | < 2 A S &CenterDot; sign ( z &prime; ) 2 ( | z &prime; | - A ) 2 A < | z &prime; | < 4 A S &CenterDot; sign ( z &prime; ) 3 ( | z &prime; | - 2 A ) 4 A < | z &prime; | < 6 A S &CenterDot; sign ( z &prime; ) 4 ( | z &prime; | - 3 A ) | z &prime; | > 6 A ;
Make z "=4A-|z ' |, then have:
LLR ( Im , 1 ) = S &CenterDot; z &prime; &prime; | z &prime; &prime; | &le; 2 A S &CenterDot; &Phi; ( z &prime; &prime; ) 2 ( | z &prime; &prime; | - A ) | z &prime; &prime; | > 2 A ;
LLR(Im,2)=S·(2A-|z″|)。
CN2011101373231A 2011-05-25 2011-05-25 System and method for realizing log likelihood ratio in digital system Pending CN102208964A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2011101373231A CN102208964A (en) 2011-05-25 2011-05-25 System and method for realizing log likelihood ratio in digital system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2011101373231A CN102208964A (en) 2011-05-25 2011-05-25 System and method for realizing log likelihood ratio in digital system

Publications (1)

Publication Number Publication Date
CN102208964A true CN102208964A (en) 2011-10-05

Family

ID=44697640

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2011101373231A Pending CN102208964A (en) 2011-05-25 2011-05-25 System and method for realizing log likelihood ratio in digital system

Country Status (1)

Country Link
CN (1) CN102208964A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107294645A (en) * 2016-03-31 2017-10-24 展讯通信(上海)有限公司 Obtain the method and its device, maximum likelihood detection method of equivalent received signals
CN107809402A (en) * 2016-09-09 2018-03-16 电信科学技术研究院 A kind of method and apparatus being demodulated

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101305575A (en) * 2005-11-11 2008-11-12 三星电子株式会社 Method and apparatus for normalizing input metric to a channel decoder in a wireless communication system
US20090231028A1 (en) * 2008-03-12 2009-09-17 Nec Laboratories America, Inc. Two-stage low-complexity max-log bit-level llr calculator and method
CN101540752A (en) * 2008-03-18 2009-09-23 卓胜微电子(上海)有限公司 Method for softly demodulating QAM
CN101883063A (en) * 2009-05-08 2010-11-10 中兴通讯股份有限公司 Iterative detecting method and device
CN101960806A (en) * 2008-03-28 2011-01-26 高通股份有限公司 Be used for approaching the system and method for log-likelihood ratio in communication system

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101305575A (en) * 2005-11-11 2008-11-12 三星电子株式会社 Method and apparatus for normalizing input metric to a channel decoder in a wireless communication system
US20090231028A1 (en) * 2008-03-12 2009-09-17 Nec Laboratories America, Inc. Two-stage low-complexity max-log bit-level llr calculator and method
CN101540752A (en) * 2008-03-18 2009-09-23 卓胜微电子(上海)有限公司 Method for softly demodulating QAM
CN101960806A (en) * 2008-03-28 2011-01-26 高通股份有限公司 Be used for approaching the system and method for log-likelihood ratio in communication system
CN101883063A (en) * 2009-05-08 2010-11-10 中兴通讯股份有限公司 Iterative detecting method and device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107294645A (en) * 2016-03-31 2017-10-24 展讯通信(上海)有限公司 Obtain the method and its device, maximum likelihood detection method of equivalent received signals
CN107294645B (en) * 2016-03-31 2019-11-01 展讯通信(上海)有限公司 Obtain method and device thereof, the maximum likelihood detection method of equivalent received signals
CN107809402A (en) * 2016-09-09 2018-03-16 电信科学技术研究院 A kind of method and apparatus being demodulated
CN107809402B (en) * 2016-09-09 2021-05-18 电信科学技术研究院 Method and equipment for demodulating

Similar Documents

Publication Publication Date Title
CN101674160B (en) Signal detection method and device for multiple-input-multiple-output wireless communication system
CN101783781B (en) Information transmission method for lowering peak to average power ratio of OFDM system signal
CN101827060B (en) Adaptive modulation-demodulation method base on fractional order Fourier transform
US20170170928A1 (en) Signal detecting method and device
CN103297373A (en) Constant envelope orthogonal frequency division multiplexing modulation method
CN102497350A (en) OFDM (Orthogonal Frequency Division Multiplexing) peak-to-average power ratio lowering method based on constellation linear expansion
CN101309243A (en) Novel OFDM parameterized channel estimator
CN101854329B (en) Fast demodulation method
CN113630151B (en) Time-frequency joint extension transmission method
CN102664862A (en) Soft demodulating method for multi-system quadrature amplitude modulation signal without equalizer
CN101764773A (en) Realization method of Gray code M-QAM modulating parallel soft bit information computation
CN101599930B (en) High-speed parallel equalizer and equalizing method thereof
CN102208964A (en) System and method for realizing log likelihood ratio in digital system
CN110290083A (en) Multicarrier difference chaotic Demodulation Systems method based on low-rank matrix estimation
CN101938333B (en) Gray code pi/ M-MPSK modulating soft bit information calculation method
CN101312443B (en) System and method for equalization and demodulation of orthogonal frequency division multiplexing communication
CN106656879B (en) A kind of high-speed and High-order variable-step self-adaptive equalization methods
CN102739576A (en) Soft bit digital demodulating method and device of planisphere based on complex number space
CN104682996A (en) Self-interference elimination method of full duplex system
CN103856298A (en) Low-complexity minimum-distance message receiving and sending end coding and decoding construction method
EP2642706B1 (en) Methods and devices for estimating channel quality
CN100414851C (en) Space hour encoding method based on rotary planisphere
CN105553614A (en) Integration device based on signal detection algorithm
CN102857323A (en) Amplification and transmission coordination based network coding method
CN101895511B (en) High-order quadrature amplitude modulation signal frequency deviation estimation method and device

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20151030

Address after: Dameisha Yantian District of Shenzhen City, Guangdong province 518085 Building No. 1

Applicant after: SHENZHEN ZTE MICROELECTRONICS TECHNOLOGY CO., LTD.

Address before: 518057 Nanshan District Guangdong high tech Industrial Park, South Road, science and technology, ZTE building, Ministry of Justice

Applicant before: ZTE Corporation

RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20111005