CN102208414A - Super-junction channel metal oxide semiconductor field effect transistor and manufacturing method thereof - Google Patents
Super-junction channel metal oxide semiconductor field effect transistor and manufacturing method thereof Download PDFInfo
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- CN102208414A CN102208414A CN2010101583860A CN201010158386A CN102208414A CN 102208414 A CN102208414 A CN 102208414A CN 2010101583860 A CN2010101583860 A CN 2010101583860A CN 201010158386 A CN201010158386 A CN 201010158386A CN 102208414 A CN102208414 A CN 102208414A
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Abstract
The invention discloses an improved super-junction channel metal oxide semiconductor field effect transistor and a manufacturing method thereof. The device effectively avoids the influence of imbalanced charge distribution, trapped charge and the like on device performance in the prior art, so that the device has higher performance characteristics. Meanwhile, the manufacturing cost of the device is effectively saved.
Description
Technical field
The present invention relates to a kind of device configuration and manufacture method of semiconductor power device.Be particularly related to the device configuration and the manufacture method of super knot (super-junction) the groove metal oxide semiconductor field effect pipe (MOSFET) of a kind of RSO of having (Resurf Stepped Oxide) structure.
Background technology
In field of semiconductor, because super knot groove MOSFET device has higher puncture voltage and lower leakage-source resistance (Rds), so it has more advantage than common groove MOSFET device in application.Yet super knot groove MOSFET also exists not enough in making and using.As everyone knows, the basic structure of super knot groove MOSFET device is that the method for injecting with ion on heavily doped substrate forms P type and the N type column doped structure that replaces at interval, its two mutually near and be parallel to each other.But, in manufacturing process, this structure very easily is affected, for example in thermal environment subsequently, factors such as trapped charge in diffusion motion and the column doped region can take place once more in the foreign ion between described P type and the N type column doped structure, these factors all can cause the CHARGE DISTRIBUTION imbalance in the super knot groove MOSFET device, thereby super knot groove MOSFET device performance is caused destructive influence.Especially, when voltage is lower than 200V, along with the narrowed width of column doped region, above-mentioned factor effect will be more obvious.
At U.S. Patent number 7,601, disclosed a kind of method in 597 and can avoid effectively that the problem of diffusion once more takes place foreign ion in above-mentioned P type and the N type column doped region.Concrete method is: after all diffusion processes (for example form sacrificial oxide layer behind the etching groove, form grid oxic horizon, form P type tagma and form n+ source region etc.) finish, carry out the formation of P type column doped region again.The super knot groove MOSFET that adopts this method formation is shown in Figure 1A.
Yet above-mentioned the deficiencies in the prior art part is that the cost of super knot groove MOSFET is too high.At first, after the etching of carrying out groove, P type column doped region will obtain by the method for the extra P type epitaxial loayer of growth; Secondly, behind the growing P-type epitaxial loayer, need to carry out of the planarization of extra chemico-mechanical polishing (CMP) process to realize that it is surperficial; Once more, need carry out twice groove etching (etching forms the groove of trench gate, another time etching form P type column doped region than deep trench).And these above-mentioned processes can roll up manufacturing cost and not be suitable for volume production.In addition, the trapped charge factor in the column doped region causes that the unbalanced problem of CHARGE DISTRIBUTION still is not resolved.
In people's such as people's such as M.A.Gajda article " Industrialization of Resurf SteppedOxide Technology for Power Transistors " and Xin Yang article " Tunable Oxide-Bypassed Trench Gate MOSFET Breaking the IdealSuper-junction MOSFET Performance Line at Equal Column Width ", disclosed the structure of the limitation that is used to solve super knot groove MOSFET respectively, shown in Figure 1B and Fig. 1 C.Except technical name was had any different, Figure 1B was very similar with two kinds of structures shown in Fig. 1 C, all was to have adopted greater than the majority carrier concentration in the conventional MOS FET epitaxial loayer to have lower Rds and higher puncture voltage in its epitaxial loayer.Meanwhile, Figure 1B and trench gate in the structure shown in Fig. 1 C all extend into the drift region and all are lined with the thicker grid oxic horizon of relative general super knot groove MOSFET at the sidewall of trench gate with the bottom.Both unique differences are, has only an epitaxial loayer in the structure shown in Figure 1B, and have two epitaxial loayers in the structure shown in Fig. 1 C, be epitaxial loayer 1 and epitaxial loayer 2, wherein epitaxial loayer 1 is positioned at heavily doped substrate top, epitaxial loayer 2 is positioned at the top of epitaxial loayer 1, and near channel region, the majority carrier concentration of epitaxial loayer 1 is lower than epitaxial loayer 2.Owing to does not have the mutual of P type and N type column doped region, thereby just do not have the unbalanced problem of CHARGE DISTRIBUTION in two kinds of structures shown in Figure 1B and Fig. 1 C, thereby the technology that has solved in the super knot groove MOSFET device is limited to.Yet two kinds of structures shown in Figure 1B and Fig. 1 C only just can demonstrate the characteristic that is superior to super knot groove MOSFET at voltage under less than the condition of 200V.That is to say that when bias voltage surpassed 200V, traditional super knot groove MOSFET device had than the lower Rds value of above-mentioned two kinds of structures, the advantage of so above-mentioned both structures will not exist when bias voltage surpasses 200V.
Therefore, in field of semiconductor, especially in the design and manufacturing field of super knot groove MOSFET device, need to propose a kind of device configuration of novelty to solve above-mentioned difficulty and design limitation.
Summary of the invention
The present invention has overcome the shortcoming that exists in the prior art, and a kind of improved semiconductor power device is provided, thereby has effectively improved the CHARGE DISTRIBUTION imbalance problem of device, has effectively reduced the production cost of device.
According to embodiments of the invention, the super knot groove metal oxide semiconductor field effect pipe (MOSFET) with a kind of RSO structure is provided, comprising:
(a) substrate of first conduction type;
(b) epitaxial loayer of first conduction type, this epitaxial loayer is positioned at the upper surface of described substrate, and the majority carrier concentration of this epitaxial loayer is lower than described substrate;
(c) a plurality of grooves are positioned at described epitaxial loayer, and extend down into described epitaxial loayer from the upper surface of described epitaxial loayer;
(d) first insulating barrier covers the inner surface of described groove lower part;
(e) multiple source region electrode, each described source region electrode are filled in the lower part and close described first insulating barrier of each described groove;
(f) second insulating barrier covers the inner surface on described groove top, and covers the top of described first insulating barrier and described source region electrode, and the thickness of this second insulating barrier is less than the thickness of described first insulating barrier;
(g) a plurality of gate electrodes, each described gate electrode are filled in the top and close described second insulating barrier of each described groove;
(h) the first column doped region of a plurality of first conduction types is positioned at described epitaxial loayer, and the partial sidewall of close described groove and the degree of depth of this first column doped region in described epitaxial loayer are less than the degree of depth of described groove in described epitaxial loayer;
(i) the second column doped region of a plurality of second conduction types is positioned at described epitaxial loayer, near and surround the described first column doped region, and the described second column doped region is parallel to the described first column doped region;
(j) tagma of a plurality of second conduction types is positioned at described epitaxial loayer, near the partial sidewall of described groove and cover the upper surface of described first column doped region and the described second column doped region;
(k) source region of a plurality of first conduction types is positioned at active area, the partial sidewall of the upper surface in close described tagma and close described groove, and the majority carrier concentration in described source region is higher than described epitaxial loayer;
(l) the 3rd insulating barrier covers the top of described gate electrode; With
(m) termination environment is positioned at described super knot groove metal oxide semiconductor field effect tube terminal place.
According to embodiments of the invention, another kind of super knot groove metal oxide semiconductor field effect pipe (MOSFET) with RSO structure is provided, comprising:
(a) substrate of first conduction type;
(b) epitaxial loayer of first conduction type, this epitaxial loayer is positioned at the upper surface of described substrate, and the majority carrier concentration of this epitaxial loayer is lower than described substrate;
(c) a plurality of grooves are positioned at described epitaxial loayer, and extend down into described epitaxial loayer from the upper surface of described epitaxial loayer;
(d) first insulating barrier covers the inner surface of described groove lower part;
(e) second insulating barrier covers the inner surface on described groove top, links to each other with described first insulating barrier, and the thickness of this second insulating barrier is less than the thickness of described first insulating barrier;
(f) a plurality of gate electrodes, each described gate electrode are filled in each described groove and close described first insulating barrier and described second insulating barrier;
(g) the first column doped region of a plurality of first conduction types is positioned at described epitaxial loayer, and the partial sidewall of close described groove and the degree of depth of this first column doped region in described epitaxial loayer are less than the degree of depth of described groove in described epitaxial loayer;
(h) the second column doped region of a plurality of second conduction types is positioned at described epitaxial loayer, near and surround the described first column doped region, and the described second column doped region is parallel to the described first column doped region;
(i) tagma of a plurality of second conduction types is positioned at described epitaxial loayer, near the partial sidewall of described groove and cover the upper surface of described first column doped region and the described second column doped region;
(j) source region of a plurality of first conduction types is positioned at active area, the partial sidewall of the upper surface in close described tagma and close described groove, and the majority carrier concentration in described source region is higher than described epitaxial loayer;
(k) the 3rd insulating barrier covers the top of described gate electrode; With
(l) termination environment is positioned at described super knot groove metal oxide semiconductor field effect tube terminal place.
In some preferred embodiments, the described substrate of bottom no show of described groove and the contact-making surface of described epitaxial loayer.In other preferred embodiments, the bottom of described groove is crossed the contact-making surface of described substrate and described epitaxial loayer and is extended down in the described substrate, simultaneously, the bottom surface of described first column doped region and the described second column doped region is near the contact-making surface of described substrate and described epitaxial loayer.
In some preferred embodiments, described super knot groove MOSFET also comprises: the snowslide enhanced doped regions of a plurality of second conduction types, be positioned at described tagma, and between per two adjacent described source regions, the bottom of described snowslide enhanced doped regions is positioned at the below, bottom in described source region, simultaneously, the majority carrier concentration of described snowslide enhanced doped regions is higher than described tagma; The shallow junction contact doping district of a plurality of second conduction types, upper surface near described tagma, this shallow junction contact doping district is positioned between per two adjacent described source regions and is formed at the top of described snowslide enhanced doped regions, simultaneously, the majority carrier concentration in described shallow junction contact doping district is higher than described snowslide enhanced doped regions.
In some preferred embodiments, when puncture voltage was less than or equal to 100V, described termination environment was made of guard ring, and described the 3rd insulating barrier covers described termination environment.In other preferred embodiments, when puncture voltage during greater than 100V, described termination environment is made of guard ring and a plurality of ditch grooved ring with suspension voltage, and described the 3rd insulating barrier covers the top of described termination environment.
In some preferred embodiments, described super knot groove MOSFET also comprises the source metal level, above described the 3rd insulating barrier and extend down between per two adjacent described the 3rd insulating barriers.
In some preferred embodiments, channel bottom described in the described super knot groove MOSFET power device does not contact described substrate top surface and is positioned at the top of described substrate.In other preferred embodiments, channel bottom extends and contacts the upper surface of described substrate downwards described in the described super knot groove MOSFET power device.
In some preferred embodiments, described first conduction type is the N type, and described second conduction type is the P type.
According to embodiments of the invention, a kind of manufacture method of super knot groove metal oxide semiconductor field effect pipe (MOSFET) of the RSO of having structure is provided, comprising:
(a) in the grow operation of epitaxial loayer of first conduction type of the upper surface of the substrate of described first conduction type;
(b) form the operation of one deck barrier oxide layer at the upper surface of described epitaxial loayer;
(c) upper surface in described barrier oxide layer provides trench mask, forms the operation of a plurality of grooves subsequently with the method for dried oxygen etching and dried silicon etching;
(d) form sacrificial oxide layer and the operation that removes this sacrificial oxide layer at described grooved inner surface;
(e) form the operation of screen oxide at described grooved inner surface;
(f) above described groove, carry out the operation that the angled ion of the dopant of second conduction type injects and carries out the diffusion of this dopant;
(g) above described groove, carry out the operation that the angled ion of the dopant of first conduction type injects and carries out the diffusion of this dopant;
(h) form the operation of first insulating barrier at the inner surface of described groove;
(i) polysilicon that deposit is mixed above described first insulating barrier forms the operation of source region electrode;
(j) return the operation of carving from described first insulating barrier and position source region electrode thereon, make described first insulating barrier and the source region electrode on it only be positioned at the bottom of described groove, remove described barrier oxide layer simultaneously;
(k) form the operation of second insulating barrier at the upper surface of the inner surface on described groove top and described first insulating barrier and described source region electrode, the thickness of described second insulating barrier is less than the thickness of described first insulating barrier;
(l) polysilicon that deposit is mixed above described second insulating barrier forms the operation of gate electrode;
(m) described gate electrode is returned the operation of carving, make described gate electrode fill the top of described groove;
(n) provide the operation of tagma mask at the upper surface of described epitaxial loayer;
(o) ion that carries out the dopant of second conduction type injects and the operation of diffusion, forms the tagma;
(p) remove described tagma mask and the operation of source region mask is provided at the upper surface of described epitaxial loayer;
(q) ion that carries out the dopant of first conduction type injects and the operation of diffusion, forms the source region; With
(r) remove described source region mask and in the operation of upper surface deposit the 3rd insulating barrier of described epitaxial loayer.
In some preferred embodiments, in the operation of described formation groove, the described barrier oxide layer of described groove break-through extends into described epitaxial loayer.In other preferred embodiments, described barrier oxide layer of described groove break-through and described epitaxial loayer extend into described substrate.
In some preferred embodiments, the operation of described formation first insulating barrier comprises thermal oxide growth or oxidation deposit.
In some preferred embodiments, the method at described time quarter comprises chemico-mechanical polishing (CMP) or plasma etching.
In some preferred embodiments, the manufacture method of the super knot groove MOSFET of the described RSO of having structure also comprises: provide the contact trench mask also to form the operation of contact zone with the method for dried oxygen etching on described the 3rd insulating barrier; The energetic ion that carries out the dopant of second conduction type injects the operation that forms the snowslide enhanced doped regions; The ion that carries out second conductivity type dopant injects the operation that forms shallow junction contact doping district.More preferably, also comprise: in the operation of described super knot groove metal oxide semiconductor field effect pipe deposited on top metal level; Provide the source metal mask also to form the operation of source metal with the method for metal etch.
In some preferred embodiments, before the operation that described tagma mask is provided, also comprise the ion injection of the dopant that the guard ring mask is provided and carries out second conduction type and the operation of diffusion.
An advantage of the invention is that adopted the RSO structure to reduce the CHARGE DISTRIBUTION imbalance, problems such as trapped charge make device have better operating characteristic to the influence of device performance in super knot groove metal oxide semiconductor field effect pipe.
Another advantage of the present invention is that in manufacture process, P type and N type column doped region have adopted the generation type of mixing, and only use etching groove one time, the cost of manufacture of having simplified manufacturing process and having saved device effectively.
Description of drawings
The advantage of these and other execution modes of the present invention will by below in conjunction with the detailed description of accompanying drawing as after, wherein:
Figure 1A is the cutaway view of the super knot groove MOSFET of prior art announcement.
Figure 1B is the cutaway view of the groove MOSFET of prior art announcement.
Fig. 1 C is the cutaway view of the another kind of groove MOSFET of prior art announcement.
Fig. 2 A is the cutaway view of super knot groove MOSFET according to a particular embodiment of the invention.
Fig. 2 B is the cutaway view according to the super knot groove MOSFET of another specific embodiment of the present invention.
Fig. 2 C is the cutaway view according to the super knot groove MOSFET of another specific embodiment of the present invention.
Fig. 2 D is the cutaway view according to the super knot groove MOSFET of another specific embodiment of the present invention.
Fig. 2 E is the cutaway view according to the super knot groove MOSFET of another specific embodiment of the present invention.
Fig. 3 A is the cutaway view according to the super knot groove MOSFET of another specific embodiment of the present invention.
Fig. 3 B is the cutaway view according to the super knot groove MOSFET of another specific embodiment of the present invention.
Fig. 4 A-4G is the cutaway view according to the super knot groove MOSFET manufacturing process of the embodiment of the invention shown in Fig. 2 E.
Embodiment
Fig. 2 A has disclosed the super knot of the N raceway groove groove MOSFET according to a preferred embodiment of the present invention, and the super knot of this N raceway groove groove MOSFET is made on the N+ substrate 200, and N type epitaxial loayer 202 is formed on the described substrate 200.The super knot of this N raceway groove groove MOSFET device also comprises a plurality of grooves 203, its upper surface from described N type epitaxial loayer 202 extends to described substrate 200 tops vertically downward, and wherein said groove 203 bottoms do not contact the contact-making surface of described substrate 200 and described epitaxial loayer 202.The inner surface of described groove 203 lower parts covers first insulating barrier 204 and fills the polysilicon that mixes and forms source region electrode 205.The inner surface on described groove 203 tops covers second insulating barrier 207 and fills the polysilicon that mixes and forms gate electrode 206, wherein said second insulating barrier 207 covers the inner surface on described groove top, and cover the upper surface of described first insulating barrier 204 and described source region electrode 205, the thickness of this second insulating barrier is less than described first insulating barrier.N type column doped region 208 is formed between per two adjacent grooves 203, and is parallel to P type column doped region 209 in epitaxial loayer 202.Described super knot groove MOSFET also comprises P type tagma 210, and it is formed between per two adjacent grooves 203 and is positioned at the top of described N type column doped region 208 and described P type column doped region 209.In addition, be positioned at each 210 upper surface place, P type tagma, have n+ source region 211.P+ snowslide enhanced doped regions 212 is formed in the tagma 210, and between adjacent n+ source region 211.In 213 formation of p++ type shallow junction contact doping district and the tagma 210, also between adjacent n+ source region 211, be positioned at the top of described P+ snowslide enhanced doped regions 212 simultaneously.Described super knot groove MOSFET also comprises the 3rd insulating barrier 214, and its top that is formed at described gate electrode 206 is to realize the insulation between gate electrode and source metal.
Fig. 2 B has disclosed according to another preferred embodiment of the present invention, it has similar structure to super knot groove MOSFET shown in Fig. 2 A, difference is that the groove 303 of super knot groove MOSFET shown in Fig. 2 B starts from the upper surface of described epitaxial loayer and extends into substrate 300 inside vertically downward, simultaneously, the source region electrode 305 that is positioned at groove 303 also extends down into substrate 300 inside.In addition, N type column doped region 308 and the also downward upper surface that extends and contact substrate 300 and epitaxial loayer 302 of P type column doped region 309.
Fig. 2 C has disclosed according to another preferred embodiment of the present invention, and it has similar structure to super knot groove MOSFET shown in Fig. 2 A, difference be the super knot groove MOSFET shown in Fig. 2 C have by guard ring 415 constitute the termination environment.In addition, source metal 416 covers the 3rd insulating barrier 414 tops and extends down between per two adjacent described the 3rd insulating barriers.In active area, described source metal 416 has realized that it contacts with electricity between described p++ type shallow junction contact doping district 413 and the described n+ source region 411; Near termination environment place, described source metal 416 has realized that it contacts with electricity between the described p++ type shallow junction contact doping district 413.
Fig. 2 D has disclosed according to another preferred embodiment of the present invention; it has similar structure to super knot groove MOSFET shown in Fig. 2 C, and difference is that the super knot groove MOS FE shown in Fig. 2 D has the termination environment that is made of guard ring 515 and a plurality of ditch grooved ring 517 with suspension voltage.
Fig. 2 E has disclosed according to another preferred embodiment of the present invention; it has similar structure to super knot groove MOSFET shown in Fig. 2 B, and difference is that the super knot groove MOSFET shown in Fig. 2 E has the termination environment that is made of guard ring 615 and a plurality of ditch grooved ring 617 with suspension voltage.In addition, source metal 616 is above the 3rd insulating barrier 614 and extend down between per two adjacent described the 3rd insulating barriers.In active area, described source metal 616 has realized that it contacts with electricity between described p++ type shallow junction contact doping district 613 and the described n+ source region 611; In the termination environment, described source metal 616 has realized that it contacts with electricity between the described p++ type shallow junction contact doping district 613.
Fig. 3 A has disclosed according to another preferred embodiment of the present invention, it has similar structure to super knot groove MOSFET shown in Fig. 2 A, and difference is not have the source region electrode in each groove 703 of the super knot groove MOSFET shown in Fig. 3 A and only has gate electrode 706.Wherein the inner surface of groove 703 lower parts covers first insulating barrier 704, and the inner surface on described groove 703 tops covers second insulating barrier 707, and fills the polysilicon formation gate electrode 706 that mixes at described groove 703.The thickness of wherein said second insulating barrier 707 is less than first insulating barrier 704.
Fig. 3 B has disclosed according to another preferred embodiment of the present invention, it has similar structure to super knot groove MOSFET shown in Fig. 3 A, difference is that the groove 803 of the super knot groove MOSFET shown in Fig. 3 B starts from the upper surface of described epitaxial loayer and extends into substrate 800 inside vertically downward, simultaneously, the gate electrode 806 that is positioned at groove 803 also extends down into substrate 800 inside.In addition, N type column doped region 808 and the also downward contact-making surface that extends and contact substrate 800 and epitaxial loayer 802 of P type column doped region 809.
Fig. 4 A to Fig. 4 G is the concrete making step of the preferred embodiment of the present invention shown in the shop drawings 2E.Shown in Fig. 4 A, at first, N type epitaxial loayer 602 is formed at N+ type substrate 600 upper surfaces.After this, the upper surface at described epitaxial loayer 602 forms barrier oxide layer 620.Subsequently trench mask is covered on the oxide layer 620, form a plurality of grooves 603, the described oxide layer 620 of wherein said groove 603 break-through, described epitaxial loayer 602 and extending in the described substrate 600 with the method for dried oxygen etching and dried silicon etching.
Shown in Fig. 4 B, at first, eliminate the defective that may cause in etching process at the inner surface formation sacrificial oxide layer (not shown) of groove 603 and by removing this sacrificial oxide layer.After this, the inner surface along described groove 603 forms screen oxide 621.Subsequently, inject the boron ion to form P type column doped region 609 with the method that angled ion injects, described P type column doped region is near described groove 603 and be positioned at described epitaxial loayer 602.
Shown in Fig. 4 C, the method for injecting with angled ion is injected arsenic ion or phosphonium ion to form N type column doped region 608, and at this moment, P type column doped region 609 is compressed.Described N type column doped region is near described groove 603 and be parallel to described P type bar shaped doped region 609.
Shown in Fig. 4 D, the method by thermal oxide growth or thick oxide layer deposit forms first insulating barrier 604 in the inner surface of described groove 603.After this, in described groove 603, fill the polysilicon that mixes and form source region electrode 605.Subsequently, described first insulating barrier and described source region electrode 605 are returned to carve make and reserve enough spaces to make second insulating barrier and gate electrode in the described groove.
Shown in Fig. 4 E, second insulating barrier 607 is formed at the inner surface on top of described groove 603 and the top of described first insulating barrier 604 and described source region electrode, and the thickness of described second insulating barrier 607 is less than first insulating barrier 604.After this, in described groove 603, fill the polysilicon that mixes and form gate electrode 606.Subsequently, with the method for chemico-mechanical polishing or ion etching described gate electrode 606 is returned quarter.
Next, provide guard ring mask (not shown), the ion that carries out P type dopant injects, and through spreading to form guard ring 615 and a plurality of ditch grooved ring 617 with suspension voltage.After this, provide tagma mask (not shown), the ion that carries out P type dopant injects, and through spreading to form P type tagma 610.Source region mask (not shown) is provided subsequently, and the ion that carries out N type dopant injects, and by diffuseing to form n+ source region 611.Described source region 611 is higher than described epitaxial loayer 602 near the upper surface in P type tagma 610 and the majority carrier concentration in described n+ source region 611.
Shown in Fig. 4 F, at first,, and provide the contact mask thereon at deposited on top the 3rd insulating barrier 614 of super knot groove MOSFET, afterwards, with the method formation contact hole of dried oxygen etching.Subsequently, inject the boron ion to form P+ snowslide enhanced doped regions 612 with the method that energetic ion injects, after this method that continues to inject with ion is injected BF2 to form p++ shallow junction contact doping district 613, and described P++ shallow junction contact doping district 613 is formed at described snowslide enhanced doped regions 612 tops.
Shown in Fig. 4 G, deposited metal 616 is located at the upper surface of described the 3rd insulating barrier 614 and extends down into contact hole.After this, provide source metal mask (not shown), form source metal, contact with electricity between described p++ shallow junction contact doping district 613 and the described n+ source region 611 to realize it with the described metal level 616 of the method etching of metal etch.
Although various embodiment have been described, are appreciated that without departing from the spirit and scope of the present invention and can make various modifications the present invention at this.For example, can form the structure of its conduction type and the various semiconductor regions of opposite conduction type described in the literary composition with method of the present invention, but the modification of having done should be forgiven within the scope of protection of present invention.
Claims (17)
1. super knot groove metal oxide semiconductor field effect pipe with RSO structure comprises:
The substrate of first conduction type;
The epitaxial loayer of first conduction type, this epitaxial loayer is positioned at the upper surface of described substrate, and the majority carrier concentration of this epitaxial loayer is lower than described substrate;
A plurality of grooves are positioned at described epitaxial loayer, and extend down into described epitaxial loayer from the upper surface of described epitaxial loayer;
First insulating barrier covers the inner surface of described groove lower part;
Multiple source region electrode, each described source region electrode are filled in the lower part and close described first insulating barrier of each described groove;
Second insulating barrier covers the inner surface on described groove top, and covers the top of described first insulating barrier and described source region electrode, and the thickness of this second insulating barrier is less than the thickness of described first insulating barrier;
A plurality of gate electrodes, each described gate electrode are filled in the top and close described second insulating barrier of each described groove;
The first column doped region of a plurality of first conduction types is positioned at described epitaxial loayer, and the partial sidewall of close described groove and the degree of depth of this first column doped region in described epitaxial loayer are less than the degree of depth of described groove in described epitaxial loayer;
The second column doped region of a plurality of second conduction types is positioned at described epitaxial loayer, near and surround the described first column doped region, and the described second column doped region is parallel to the described first column doped region;
The tagma of a plurality of second conduction types is positioned at described epitaxial loayer, near the partial sidewall of described groove and cover the upper surface of described first column doped region and the described second column doped region;
The source region of a plurality of first conduction types is positioned at active area, the partial sidewall of the upper surface in close described tagma and close described groove, and the majority carrier concentration in described source region is higher than described epitaxial loayer;
The 3rd insulating barrier covers the top of described gate electrode; With
The termination environment is positioned at described super knot groove metal oxide semiconductor field effect tube terminal place.
2. super knot groove metal oxide semiconductor field effect pipe with RSO structure comprises:
The substrate of first conduction type;
The epitaxial loayer of first conduction type, this epitaxial loayer is positioned at the upper surface of described substrate, and the majority carrier concentration of this epitaxial loayer is lower than described substrate;
A plurality of grooves are positioned at described epitaxial loayer, and extend down into described epitaxial loayer from the upper surface of described epitaxial loayer;
First insulating barrier covers the inner surface of described groove lower part;
Second insulating barrier covers the inner surface on described groove top, links to each other with described first insulating barrier, and the thickness of this second insulating barrier is less than the thickness of described first insulating barrier;
A plurality of gate electrodes, each described gate electrode are filled in each described groove and close described first insulating barrier and described second insulating barrier;
The first column doped region of a plurality of first conduction types is positioned at described epitaxial loayer, and the partial sidewall of close described groove and the degree of depth of this first column doped region in described epitaxial loayer are less than the degree of depth of described groove in described epitaxial loayer;
The second column doped region of a plurality of second conduction types is positioned at described epitaxial loayer, near and surround the described first column doped region, and the described second column doped region is parallel to the described first column doped region;
The tagma of a plurality of second conduction types is positioned at described epitaxial loayer, near the partial sidewall of described groove and cover the upper surface of described first column doped region and the described second column doped region;
The source region of a plurality of first conduction types is positioned at active area, the partial sidewall of the upper surface in close described tagma and close described groove, and the majority carrier concentration in described source region is higher than described epitaxial loayer;
The 3rd insulating barrier covers the top of described gate electrode; With
The termination environment is positioned at described super knot groove metal oxide semiconductor field effect tube terminal place.
3. super knot groove metal oxide semiconductor field effect pipe according to claim 1 and 2, the described substrate of bottom no show of wherein said groove and the contact-making surface of described epitaxial loayer.
4. super knot groove metal oxide semiconductor field effect pipe according to claim 1 and 2, the bottom of wherein said groove is crossed the contact-making surface of described substrate and described epitaxial loayer and is extended down in the described substrate, simultaneously, the bottom surface of described first column doped region and the described second column doped region is near the contact-making surface of described substrate and described epitaxial loayer.
5. super knot groove metal oxide semiconductor field effect pipe according to claim 1 and 2 wherein also comprises:
The snowslide enhanced doped regions of a plurality of second conduction types, be positioned at described tagma, and between per two adjacent described source regions, the bottom of described snowslide enhanced doped regions is positioned at the below, bottom in described source region, simultaneously, the concentration of the majority carrier of described snowslide enhanced doped regions is higher than described tagma;
The shallow junction contact doping district of a plurality of second conduction types, upper surface near described tagma, this shallow junction contact doping district is positioned between per two adjacent described source regions and is formed at the top of described snowslide enhanced doped regions, simultaneously, the majority carrier concentration in described shallow junction contact doping district is higher than described snowslide enhanced doped regions.
6. super knot groove metal oxide semiconductor field effect pipe according to claim 1 and 2, wherein when puncture voltage was less than or equal to 100V, described termination environment was made of guard ring, and described the 3rd insulating barrier covers described termination environment.
7. super knot groove metal oxide semiconductor field effect pipe according to claim 1 and 2; wherein when puncture voltage during greater than 100V; described termination environment is made of guard ring and a plurality of ditch grooved ring with suspension voltage, and described the 3rd insulating barrier covers described termination environment.
8. super knot groove metal oxide semiconductor field effect pipe according to claim 1 and 2 wherein also comprises:
Source metal is above described the 3rd insulating barrier and extend down between per two adjacent described the 3rd insulating barriers.
9. super knot groove metal oxide semiconductor field effect pipe according to claim 1 and 2, wherein said first conduction type is the N type, described second conduction type is the P type.
10. manufacture method with super knot groove metal oxide semiconductor field effect pipe of RSO structure comprises:
In the grow operation of epitaxial loayer of first conduction type of the upper surface of the substrate of described first conduction type;
Form the operation of one deck barrier oxide layer at the upper surface of described epitaxial loayer;
Upper surface in described barrier oxide layer provides trench mask, forms the operation of a plurality of grooves subsequently with the method for dried oxygen etching and dried silicon etching;
Form sacrificial oxide layer and the operation that removes this sacrificial oxide layer at described grooved inner surface;
Form the operation of screen oxide at described grooved inner surface;
Above described groove, carry out the operation that the angled ion of the dopant of second conduction type injects and carries out the diffusion of this dopant;
Above described groove, carry out the operation that the angled ion of the dopant of first conduction type injects and carries out the diffusion of this dopant;
Form the operation of first insulating barrier at the inner surface of described groove;
The polysilicon that deposit is mixed above described first insulating barrier forms the operation of source region electrode;
Described first insulating barrier and position source region electrode are thereon returned the operation of carving, make described first insulating barrier and the source region electrode on it only be positioned at the bottom of described groove, remove described barrier oxide layer simultaneously;
Form the operation of second insulating barrier at the upper surface of the inner surface on described groove top and described first insulating barrier and described source region electrode, the thickness of described second insulating barrier is less than described first insulating barrier;
The polysilicon that deposit is mixed above described second insulating barrier forms the operation of gate electrode;
Described gate electrode is returned the operation of carving, make described gate electrode fill the top of described groove;
The operation of tagma mask is provided at the upper surface of described epitaxial loayer;
The ion that carries out the dopant of second conduction type injects and the operation of diffusion, forms the tagma;
Remove described tagma mask and the operation of source region mask is provided at the upper surface of described epitaxial loayer;
The ion that carries out the dopant of first conduction type injects and the operation of diffusion, forms the source region; With
Remove described source region mask and in the operation of upper surface deposit the 3rd insulating barrier of described epitaxial loayer.
11. the manufacture method of super knot groove metal oxide semiconductor field effect pipe according to claim 10 wherein forms in the operation of described groove, the described barrier oxide layer of described groove break-through extends into described epitaxial loayer.
12. the manufacture method of super knot groove metal oxide semiconductor field effect pipe according to claim 10 wherein forms in the operation of described groove, described barrier oxide layer of described groove break-through and described epitaxial loayer extend into described substrate.
13. the manufacture method of super knot groove metal oxide semiconductor field effect pipe according to claim 10, the formation method of wherein said first insulating barrier comprises thermal oxide growth or oxidation deposit.
14. the manufacture method of super knot groove metal oxide semiconductor field effect pipe according to claim 10, the method at wherein said time quarter comprises chemico-mechanical polishing or plasma etching.
15. the manufacture method of super knot groove metal oxide semiconductor field effect pipe according to claim 10 wherein also comprises:
On described the 3rd insulating barrier, provide the contact mask also to form the operation of contact zone with the method for dried oxygen etching;
The energetic ion that carries out the dopant of second conduction type injects the operation that forms the snowslide enhanced doped regions;
The ion that carries out the dopant of second conduction type injects the operation that forms shallow junction contact doping district.
16. the manufacture method of super knot groove metal oxide semiconductor field effect pipe according to claim 10; wherein before the tagma mask is provided, also comprise the ion injection of the dopant that the guard ring mask is provided earlier and carries out second conduction type and the operation of diffusion.
17. the manufacture method of super knot groove metal oxide semiconductor field effect pipe according to claim 15 wherein also comprises:
Operation at described super knot groove metal oxide semiconductor field effect pipe deposited on top metal level;
Provide the source metal mask also to form the operation of source metal with the method for metal etch.
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