CN102195740B - Method and device for performing simplified decoding checking by low density parity check codes - Google Patents

Abstract

The invention relates to a method and a device for performing simplified decoding checking by low density parity check codes, which belong to the technical field of communication. In the method and the device, a checking matrix is not required in checking. In an area with a low signal to noise ratio, different iteration number threshold values are set according to different signal to noise ratios, and in the area with a high signal to noise ratio, number threshold values of sub-rows according to the different signal to noise ratios, wherein sign bits of information bits are continuously invariable before and after the sub-rows are updated. When the threshold values are exceeded, iterative decoding is finished. Compared with the conventional methods in which the checking matrix participates in the checking, the invention avoids the use of the checking matrix, greatly reduces the calculated amount of checking calculation of each time and reduces the bandwidth requirements of a memory, thereby reducing hardware overhead, saving power consumption and reducing the area.

Description

Simplified decoding method of calibration and the device of low density parity check code

Technical field

The present invention relates to the forward error correction technique in the communications field, particularly decoding method of calibration and the device of low density parity check code.

Background technology

Low density parity check code (LDPC) is a kind of error correcting code that was at first proposed in 1962 by Gallager.The main thought of low density parity check code is with low-density check matrix notation block code, in order to reduce the complexity of block code coding and decoding, and can use iterative decoding algorithm, thereby make the restriction of code length relax, can approach the Shannon channel capacity with long code.The performance of irregular LDPC codes not only is better than canonical LDPC code, even also is better than Turbo code, is at present known near the code of shannon limit, and best performance and the shannon limit announced only differ 0.0045dB.Due to its good coding efficiency, be easy to carry out theory analysis and research, the simple and practicable parallel work-flow of decoding is fit to the advantages such as hardware realization, is used in plurality of communication systems at present.Standards such as China Digital TV terrestrial broadcasting standard (DMB-TH), DVB-S2,802.11n, WIMAX has all adopted the LDPC code.

The LDPC code belongs to linear block codes.The LDPC code can represent by check matrix, and the size of the row of this check matrix is N, and the size of row is M, code check R=(N-M)/N.In check matrix, the number of contained in every row " 1 " is called capable the weight, and the number of contained in every row " 1 " is called column weight.Regular LDPC code refers to that capable weights all in check matrix all equates, all column weights also equate.Irregular LDPC codes is similar to regular LDPC code, but has the heavy and different row of other row weights of row in check matrix in all row, perhaps has the column weight row different from other column weights in all row.As shown in Figure 1, code check R=(7-4)/7=3/7, the row of the first row are heavily 3, the column weight position 2 of first row, and because the row of the third line is heavily 2, and the row of other row is heavily 3, so this LDPC code is irregular code.Check matrix is a kind of sparse matrix, and in matrix, the number of " 1 " is very rare, for example in the DMB-TH standard in the check matrix of 0.4 code check the density of " 1 " be only 0.001.The present invention is main relevant to the decoding of LDPC code, and the below introduces the decoding algorithm of LDPC code.

At present, the researcher has proposed multiple decoding algorithm based on putting letter and transmitting, and algorithm principle is similar, and its main difference is the information transmitted.Minimum-sum algorithm and the Illinois, America Mansour of university that main decoding algorithm has people such as putting letter transmission (BP) algorithm, MPC Fossorier to propose, M.M. and Shanbhag, the TDMP algorithm that N.R. proposes.Because the TDMP algorithm is accelerated iteration speed, reduce decoding delay, the Illinois, America Mansour of university, M.M. and Shanbhag, N.R. proposes the TDMP algorithm.TDMP algorithm not only amount of calculation is little, and saves memory data output, and this is conducive to reduce the ldpc decoder area, reduces power consumption.

For the ease of understanding the present invention, the below carries out brief mathematical description to the TDMP algorithm.

This algorithm meets the irregular LDPC codes of AA framework mainly for check matrix.So-called AA framework refers to that this check matrix can be divided into S1 * S2 submatrix, and namely to be divided into S1 capable for check matrix, and every row is divided into again the S2 row, and in each submatrix after decomposition, in every row and every row, " 1 " number can be over 1.In the present invention, so-called son row refers to that the S1 that check matrix is divided into is capable; So-called submatrix refers to the capable S2 row that are broken down into again of every height.As shown in Figure 2, matrix is divided into S1=4 son row, and every height is capable can be divided into again S2=8 son row, divides for S1 * S2=32 submatrix altogether, and each submatrix is 3 * 3 matrixes.Minimum-sum algorithm is adopted in the verification of this algorithm and the renewal of information node, and basic procedure is as follows:

(a) information initializing.Initializing variable nodal information Lq _vBe initial channel information, initialization check-node information R _cvBe zero.

(b) information iteration calculates.R _cvThe information that when calculating for current submatrix is capable, check-node c transmits to variable node v.R′ _cvThe information that when calculating for last son row, check-node c transmits to variable node v.N (c)/v represents the set of the remaining variables node except variable node v that is connected with check-node c.The set of all variable nodes that N (v) expression is connected with check-node c.Lq ' _vThe set of all the other check-nodes except check-node c that the last son row of expression is connected with variable node v when calculating.Lq _vThe information that represents all check-nodes of being connected with variable node v in current son row with.The calculating of equation (1) and (2) is carried out based on child is capable, completes the renewal of check-node information.The check-node information that every height is capable according to equation (3), is completed the renewal of variable node information after calculating and completing.

Lq′ _v＝Lq _v-R′ _cv (1)

$R_{\mathrm{cv}}=\underset{v\∈N\left(c\right)/v}{\∏}\mathrm{Sign}\left(L{q^{\′}}_v\right)\underset{v\∈N\left(c\right)/v}{\mathrm{Min}}\left(\right|L{q^{\′}}_v\left|\right)---\left(2\right)$

${\mathrm{Lq}}_v=\underset{m\∈\left(v\right)}{\mathrm{\Σ}}{R}_{\mathrm{cv}}$

$={{\mathrm{Lq}}^{\′}}_v+R_{\mathrm{cv}}$

(c) decoding verification.The Lq of a sub-row matrix _vAfter calculating is completed, according to Lq _vTranslate code word, Lq _v＜0 code word bits C (v)=1, otherwise C (v)=0 are as shown in equation (4).Then carry out verification according to check matrix H, verification is calculated as equation (5), i.e. the inner product of compute codeword bit and the every row of H matrix.Function mod (x, 2) expression x Modulo-two operation.Inner product module 2 is 0, this row verification succeeds.If all provisional capital verification succeeds of H matrix, decision codeword is correct, and successfully decoded flag bit F is 1, stops (a) step information iteration and calculates.Otherwise continue (b) step and (c) go on foot.When reaching maximum iteration time, no matter whether successfully decoded, withdraw from by force whole iterative process.

$C\left(v\right)=\left\{\begin{array}{cc}1& L{q}_v<0\\ 0& L{q}_v\&GreaterEqual;0\end{array}\right.---\left(4\right)$

$F=(\underset{m=1}{\overset{M}{\mathrm{\&Sigma;}}}\mathrm{mod}(\underset{n=1}{\overset{N}{\mathrm{\&Sigma;}}}C\left(v\right)\&times;H(m,n),2)==0)---\left(5\right)$

In the TDMP algorithm flow, after each son row check-node information was calculated and completed, the new check-node value of information had been improved decoding speed by in the renewal of substitution variable node.The more typical minimum-sum algorithm of data throughput is doubled.Simultaneously, owing to need not preserving initial channel information and variable node information Lq ' _n, greatly saved memory, reduced chip area, reduced power consumption.

But in this algorithm flow, after check-node information and variable node information due to the complete son row of every calculating, all need the code word that translates is carried out verification, therefore produced verification and calculated validity problem.Can find out from formula (5), when carrying out the iteration judgement, need to carry out multiplication of matrices, this has just introduced complicated calculating, not only require to increase logical circuit to improve the parallel processing capability of verification computing hardware, and require memory (particularly check matrix memory) that sufficiently high bandwidth can be provided, then 1 be difficult to reach or the cost of needs very high.Therefore, be necessary to study better iteration terminating method and solve this problem.

Summary of the invention

The purpose of this invention is to provide a kind of LDPC method of calibration and device, to overcome the deficiency of existing calibration technology.The present invention is mainly for the check matrix that meets the AA framework.In matrix, this method of calibration does not need check matrix is operated when a verification is calculated, and only the change of the sign bit before and after each the renewal is calculated.This greatly reduces amount of calculation, has reduced hardware consumption, can satisfy better system power dissipation, Area and Speed requirement.

The invention provides a kind of method of calibration of low density parity check code, the method comprises the setting of threshold value table, low noise district's code word verification, the district's code word verification of high noise and four steps of check results output, wherein, at first according to emulation, a threshold value table is set, during iterative decoding, obtain corresponding threshold value according to code check and the signal to noise ratio of enter code word from threshold value table; In the process of iteration, the district's code word verification of high noise and the district's code word verification of low noise judge and the output verification sign according to threshold value respectively; Check results is selected the still check mark in low noise district of high noise district according to the flag bit that obtains in threshold value table, and output decoding termination flag; When the decoding termination flag is 1, stop iteration.

The present invention also provides a kind of decoding calibration equipment of low density parity check code, this device comprises that controller module, threshold value table memory module, submatrix sign bit change judge module, son row sign bit and change judge module, high noise district code word correction verification module, low noise district's code word correction verification module and check results generation module, wherein, controller module is controlled the operation of whole device; The parameter that the threshold value table memory module stores sets in advance; Whether the submatrix sign bit changes the sign bit that judge module judge a sub-matrix update front and back information bit and changes; Whether son row sign bit changes the sign bit that judge module judge that a son row upgrades the front and back information bit and changes; The number of the immovable continuous son row of high noise district code word correction verification module sign bit capable of child compares with the threshold value that obtains from threshold value table and obtains judged result; Low noise district code word correction verification module compares Output rusults to the iterations of input and the threshold value that obtains from threshold value table; The check results generation module is processed the check results in high noise district and low noise district is processed, and produces the decoding termination flag.

The advantage of the inventive method comprises:

(1) during the complete laggard row decoding verification of every row submatrix iterative computation, because this method only needs to carry out the comparison of iterations in the district's iteration termination of low noise, the district carries out the iteration termination by the constant continuous son row number of sign bit that more sub-row upgrades the front and back information bit in high noise, do not need to carry out the multiplication of matrices computing, greatly reduced amount of calculation.

(2) the present invention owing to not needing reading out data from the H matrix, has greatly reduced the bandwidth requirement of H matrix storage.

(3) the present invention is only the data of the sign bit of current renewal due to what compare at every turn, has reduced the bandwidth requirement of code word memory.The minimizing of readout code word memory number of times is conducive to save power consumption.

Description of drawings

Fig. 1 is the check matrix that the LDPC code adopts;

Fig. 2 is the representation that meets the H matrix of AA framework;

Fig. 3 is the internal structure of configuration parameter information table;

Fig. 4 is checking process figure of the present invention;

Fig. 5 is control device structured flowchart of the present invention;

Fig. 6 is that submatrix sign bit of the present invention changes the judge module structure chart;

Fig. 7 is that the present invention's row sign bit changes the judge module structure chart;

Fig. 8 is the high noise of the present invention district code word correction verification module structural representation;

Fig. 9 is the low noise of the present invention district code word correction verification module structural representation;

Figure 10 is check results output module schematic diagram of the present invention.

Embodiment

Further illustrate the solution of the present invention below in conjunction with embodiment and accompanying drawing.

The method of calibration that the present invention proposes comprises following content:

(1) for the code word of different code checks and signal to noise ratio, a threshold value table is set.As shown in Figure 3, this threshold value table comprises four parts: signal to noise ratio (Eb/N0), code check, threshold value and flag bit (flag).Signal to noise ratio and code check are input variables, and threshold value and flag bit are output variables, and input variable and output variable are one-to-one relationships.Relation is to preset and be stored in holder by emulation one to one.Signal to noise ratio and code check are the attributes of enter code word.Threshold value is according to the difference of flag bit, and its implication is different.When flag bit was 0, threshold value was the threshold value that is in low noise district code word, and its expression is the maximum of iterations.When flag bit was 1, threshold value was the threshold value that is in high noise district code word, and its expression is the sign bit capable maximum number of varitron not continuously before and after son row sign bit upgrades.Flag bit can pass through formula (6) to be determined, wherein E is a signal to noise ratio, can determine by emulation.

$\mathrm{flag}=\left\{\begin{array}{cc}0& \mathrm{Eb}/\mathrm{<figure-callout\; id="0"\; label="N"\; filenames="HSA00000051084400011.png,HSA00000051084400012.png"\; state="\{\{state\}\}">N</figure-callout>}0\&le;\mathrm{<figure-callout\; id="1"\; label="E"\; filenames="HSA00000051084400011.png,HSA00000051084400012.png"\; state="\{\{state\}\}">E</figure-callout>}\\ 1& \mathrm{Eb}/\mathrm{<figure-callout\; id="0"\; label="N"\; filenames="HSA00000051084400011.png,HSA00000051084400012.png"\; state="\{\{state\}\}">N</figure-callout>}0>E\end{array}\right.---\left(6\right)$

(2) for the judgement of low noise district code word, the threshold value that order obtains from threshold value table is I _Stop, compare iterations and I _Stop, as iterations I greater than I _StopThe time, low noise district check mark Fi puts 1, stops iterative decoding, otherwise Fi sets to 0, and proceeds iteration.

$F_i=\left\{\begin{array}{cc}0& I<I_{\mathrm{stop}}\\ 1& I\&GreaterEqual;I_{\mathrm{stop}}\end{array}\right.---\left(7\right)$

(3) variation of sign bit judgement.With k son row of R (k) expression, the set of all non-zero submatrices in k son row of M (R (k)) expression.As in Fig. 2, the 3rd son row represents with R (3), all non-zero submatrices { 2,4,8} in the sub-row 3 of M (R (3)) expression.

In the iterative decoding process of LDPC, iteration all can be upgraded variable node information each time.The sign change of variable node information before and after formula (8) expression submatrix m upgrades.Wherein, s _nRepresent the symbol of n variable node information before upgrading in submatrix, s ' _nRepresent the symbol of n variable node information after upgrading in submatrix.

Represent XOR, if the sign bit before and after namely upgrading is identical be 1, otherwise result is 0.Then the result of gained is carried out operation of bits, operator operator ﹠amp;

The sign bit that sign bit before and after all information bits of a sub-row are upgraded changes before and after the information bit renewal that is equivalent in all non-zero submatrices changes, so before and after the renewal of k son row, whether sign bit does not change and can judge by formula (9), if T ^(k) _CounterEqual 0, illustrate k son row upgrade before and after sign bit do not change, if greater than 0, illustrate that k son row upgrades the front and back sign bit and change.

${T^{\left(k\right)}}_{\mathrm{counter}}=\underset{j\&Element;M\left(R\left(k\right)\right)}{\mathrm{\&Sigma;}}c(k,j)---\left(9\right)$

The immovable number in son row continuous symbol position is calculated by formula (10), if the sign bit of k all information bits of son row does not change, the constant number of son row sign bit adds 1 continuously, otherwise zero clearing.

$T_{\mathrm{counter}}=\left\{\begin{array}{cc}{T}_{\mathrm{counter}}+1& {T^{\left(k\right)}}_{\mathrm{counter}}\&NotEqual;0\\ T_{\mathrm{counter}}& {T^{\left(k\right)}}_{\mathrm{counter}}=0\end{array}\right.---\left(10\right)$

(4) for the judgement of high noise district code word, making in threshold value table the threshold parameter that obtains according to code check and signal to noise ratio is T _Stop, high noise district termination flag is F _h, as shown in formula (11), as the value T of counter _CounterMore than or equal to T _StopThe time, F _hPut 1, will stop iteration, otherwise F _hSet to 0, proceed iteration.

$F_h=\left\{\begin{array}{cc}0& T_{\mathrm{counter}}<T_{\mathrm{stop}}\\ 1& T_{\mathrm{counter}}\&GreaterEqual;T_{\mathrm{stop}}\end{array}\right.---\left(11\right)$

(5) check results output is as formula (12) as shown in, and when flag equals 0, namely code word is in when hanging down the noise district, and check results F equals F _iWhen flag equals 1, when namely code word was in high noise district, check results F equaled F _h

$F=\left\{\begin{array}{cc}{F}_i& \mathrm{flag}=0\\ F_h& \mathrm{flag}=1\end{array}\right.---\left(12\right)$

The idiographic flow of this method as shown in Figure 4, after the code word input, check in corresponding threshold value and flag bit according to code check and the signal to noise ratio of code word from threshold value table, high noise district's correction verification module and low noise district correction verification module produce respectively corresponding check mark, and the check results module is according to the still check mark in low noise district of the judgement symbol in the flag bit judgement high noise of the output district that checks in from threshold value table.If the termination flag position of check results output is zero, proceeds iteration, otherwise stop carrying out iteration.

The method of calibration according to the present invention, the device that obtains comprise that controller module, configuration parameter memory, submatrix codeword information bit sign change judge module, son row code-word symbol and change judge module, low noise district correction verification module, high noise district's correction verification module and check results generation module.

Controller module is responsible for controlling the work of whole device.Controller module receives verification enable signal, the data-signal that bit rate signal and check matrix memory are sent here.Controller module sends the data that address signal, read-write and chip selection signal read decoding information bit memory and configuration information memory; Whether the submatrix sign bit changes the sign bit that judge module judge a sub-matrix update front and back information bit and changes; Whether son row sign bit changes the sign bit that judge module judge that a son row upgrades the front and back information bit and changes; The number of the immovable continuous son row of high noise district code word correction verification module sign bit capable of child compares with the threshold value that obtains from threshold value table and obtains judged result; Low noise district code word correction verification module compares the output verification sign to the iterations of input and the threshold value that obtains from threshold value table; The check results generation module is processed the check mark of high noise district and the district's output of low noise, produces the decoding termination flag.

The configuration parameter memory is preserved the check matrix of 3 kinds of code checks of GB DMB-TH, is constant due to what store, adopts read-only memory to realize.In the configuration parameter memory, the data format of memory cell as shown in Figure 3, comprises four parts: Eb/N0, code check, threshold value and flag bit.Eb/N0 represents the signal to noise ratio of channel.When flag bit was 0, the Eb/N0 that represents this moment was in low noise district, and threshold value is representing iterations; When flag bit was 1, at this moment Eb/N0 of representative was in high noise district, and during threshold value is representing and upgrading, to change be the threshold value of zero number to sign bit continuously.

The submatrix code-word symbol changes judge module.As shown in Figure 6, s _nAnd s ' _nRepresent respectively the sign bit of information bit before and after a sub-matrix update.At first s _nAnd s ' _nObtain an intermediate object program F by xor operation ", after xor operation, then the s as a result after n XOR " ₁, s " ₂... s " _nCarry out and operation, judge whether this result is zero, if be zero, submatrix flag bit F ' puts 1, otherwise sets to 0.

Son row code-word symbol changes judge module.As shown in Figure 7, the cumulative submatrix code-word symbol of this module position changes the Output rusults of judge module, when the EOL mark position enables, stop adding up, and the output accumulation result.

High noise district code word correction verification module.As shown in Figure 8, the Output rusults that the capable code-word symbol of antithetical phrase changes judge module adds up, and this module produces an iteration and stops judgement symbol T _CounterIf T _CounterMore than or equal to the threshold value that obtains from threshold value table, the output identification position is 1, otherwise is zero.

Low noise district code word correction verification module.As shown in Figure 9, the main iterations threshold value I by iterations I and setting in low noise district method of calibration _StopCompare, if I is greater than threshold value I _Stop, stop iteration, otherwise proceed iteration.When iteration stopped, output termination tag mark and output enable sign enabled, and output enable representative output identification at this moment is effective.

The check results output module.As shown in figure 10, when the judgement symbol in high noise district and low noise district enters successfully decoded sign generation module, the flag bit F that this module need to be inputted from the parameter configuration memory _hlJudgement.When flag bit 1, export the check mark in high noise district this moment, otherwise the check mark in noise district is hanged down in output.Stop the decoding iteration when successfully decoded when being masked as 1, otherwise proceed iteration.

Hereinafter introduce the LDPC decode procedure.

Initialization check-node sequence equals full 0.The initialization information node is the channel information that receives.

Then carry out iterative computation.According to equation (1) and (2) calculation check sequence node R _cvAfter the check node calculation of a son row is completed, calculate variable node according to equation (3).In calculating, due to the precision of hardware impact, need to quantize variable node and check-node sequence.

Iterative process constantly carries out, until successfully decoded sign is effective or iterations reaches maximum, just withdraws from iterative computation.

Complete when the capable variable node information updating of each piece, obtain the decoding code word according to equation (4).

According to method of calibration of the present invention, at first the present embodiment is divided into S1 son row and S2 is listed as with the H matrix so that child is capable.The purpose of dividing like this is consistent with iterative process, convenient calculating.To the check matrix of 0.4 code check in Chinese digital TV ground standard, parameter S 1=35, S2=59.Therefore, check matrix can be divided into 35 son row, and once the iteration of whole matrix can be divided into 35 second son iteration and completes.

Fig. 5 is calibration equipment of the present invention.Operation principle to this device is described in detail the below as an example of DMB-TH example.After the code word that needs decoding entered decoder, controller module produced control signal according to code check and the verification enable signal of input.Controller module sends the data that address signal, read-write and chip selection signal read decoding information bit memory and configuration information memory; Controller module sends the submatrix sign bit and changes the data select signal of module and calculate enable signal; Controller module sends register zero clearing and the data enable signal that son row sign bit changes module; Controller module sends relatively enabling and the register reset signal of low noise district's code word correction verification module; Controller module sends relatively enabling and the register reset signal of high noise district's code word correction verification module; Controller module sends the result of successfully decoded sign generation module and selects signal and register reset signal.

When input Eb/N0 and code check, memory output parameter threshold value and flag bit.For example, when code check was 0.4, Eb/N0=1.0dB, the flag bit of output was 0, and at this moment Eb/N0 of representative is in low noise district; The threshold value of output is 6 to represent that the threshold value of the number of times that iteration stops is 6, stops iteration more than or equal to 6 the time when iterations.When code check was 0.6, Eb/N0=2.5dB, the flag bit of output was 1, and at this moment Eb/N0 of representative is in high noise district; The threshold value of output is 35 to represent son row to upgrade the constant number of sign bit be zero continuous number more than or equal to stopping iteration at 35 o'clock.

Because the size of each submatrix of DMB-TH is 127, so at the iterative process of each submatrix, s ₁, s ₂... s ₁₂₇Represent the sign bit before submatrix upgrades, s ' ₁, s ' ₂... s ' ₁₂₇Represent the sign bit after a son row upgrades.The span that makes n is 1...127, s _nAnd s ' _nObtain an intermediate object program s ' by xor operation _n, after xor operation, then the s as a result after 127 XORs " ₁, s " ₂... s " ₁₂₇Carry out and operation, judge whether this result is zero, if be zero, F " puts 1, otherwise sets to 0.

When code word is in low noise district, iterations I derives from main control module, I _StopObtain from the configuration information memory.If I is greater than threshold value I _Stop, stop iteration, otherwise proceed iteration.When iteration stops, output verification sign and output enable sign en_i, en_i is 1 o'clock, representative output identification F at this moment _iEffectively, otherwise export invalid.

When code word is in high noise district, judgement symbol F ' of output and enabler flags en_i after each submatrix judgement, the end mark parameter of son row derives from master controller, and when capable calculatings of group finished, this module produced an iteration termination judgement symbol T _CounterT _CounterWith the parameter T that reads in from the configuration parameter memory _StopRelatively, output iteration termination flag.

When the check mark in high noise district and low noise district entered successfully decoded sign generation module, this module need to be by the flag bit F ' that inputs in the parameter configuration memory _hlJudgement, and output iteration termination flag.

The effect of calibration equipment below is described:

(1) this device amount of calculation is little, and verification speed is fast.This device is owing to needing to carry out the multiplication of matrices computing, only need some simple with, XOR, addition and relatively wait operation, only need the sign bit of information bit relatively when carrying out verification, therefore greatly saved operand.When carrying out verification calculating, 127 the tunnel is parallel, 1 submatrix of 1 processing.

(2) bandwidth requirement of this device is low, saves memory.This device does not need to read the check matrix memory when verification is calculated, do not need the reading information bit memory during verification simultaneously, because as long as the sign bit of temporary original code word, and the sign bit of decoding code word can obtain before the writing information bit memory.The reading times of memory is few, and bandwidth requirement is low, and the memory of using in the time of can multiplexing iterative computation is realized, thereby saved memory.

Claims (12)

1. the simplified decoding method of calibration of a low density parity check code, it is characterized in that: the method comprises the setting of threshold value table, low noise district's code word verification, the district's code word verification of high noise and four steps of check results output, wherein, at first according to emulation, a threshold value table is set, during iterative decoding, obtain corresponding threshold value according to code check and the signal to noise ratio of enter code word from threshold value table; In the process of iteration, the code word verification of high noise district and the district's code word verification of low noise judge and the output verification sign according to threshold value respectively, check results is selected the still check mark in low noise district of high noise district according to the flag bit that obtains in threshold value table, and output decoding termination flag, when check results is 1, stop iteration.

2. simplified decoding method of calibration according to claim 1, it is characterized in that: in the setting steps of described threshold value table, threshold value table comprises four parts: signal to noise ratio (Eb/N0), code check, threshold value and flag bit, wherein, threshold value is according to signal to noise ratio and code check setting, mark position to distinguish high s/n ratio district and low signal-to-noise ratio district, 1 sign high s/n ratio district, 0 sign low signal-to-noise ratio district.

3. simplified decoding method of calibration according to claim 1, it is characterized in that: in the step of described low noise district's code word verification, at first obtain threshold value according to signal to noise ratio and code check from threshold value table, then iterations and this threshold, if iterations more than or equal to threshold value low noise district code word check mark be 1, otherwise be 0.

4. simplified decoding method of calibration according to claim 1, it is characterized in that: in the step of described high noise district's code word verification, at first obtain threshold value according to signal to noise ratio and code check from threshold value table, then before and after this threshold value and son row being upgraded calculating, the continuous immovable son row sum of sign bit compares, before and after renewal as capable in fruit is calculated, the continuous immovable son row sum of sign bit is more than or equal to this threshold value, high noise district code word check mark is 1, otherwise is 0.

5. simplified decoding method of calibration according to claim 1, it is characterized in that: in the step of described check results output, obtain flag bit according to signal to noise ratio and code check from threshold value table, flag bit is to export high noise district check mark at 1 o'clock, and flag bit is the 0 o'clock low noise of output district check mark.

6. the decoding calibration equipment of a low density parity check code, it is characterized in that: this device comprises that controller module, threshold value table memory module, submatrix sign bit change correction verification module, son row sign bit and change correction verification module, high noise district code word correction verification module, low noise district's code word correction verification module and check results generation module, wherein, controller module is controlled the operation of whole device; The parameter that the threshold value table memory module stores sets in advance; Whether the submatrix sign bit changes the sign bit that correction verification module judge a sub-matrix update front and back information bit and changes; Whether son row sign bit changes the sign bit that correction verification module judge that a son row upgrades the front and back information bit and changes; The number of the immovable continuous son row of high noise district code word correction verification module sign bit capable of child compares the output verification sign with the threshold value that obtains from threshold value table; Low noise district code word correction verification module compares the output verification sign to the iterations of input and the threshold value that obtains from threshold value table; The check results generation module is processed the check results in high noise district and low noise district is processed, and output decoding termination flag.

7. device according to claim 6, it is characterized in that: in described threshold value table memory module, memory is a read-only memory, stores the threshold value in high noise district and low noise district, simultaneously the distinctive mark in storage height noise district also; The threshold value in low noise district represents the threshold value of iterations; The threshold value in high noise district represents the threshold value of the count value that sign bit is constant after continuous sub-row iteration, no matter is in high noise district or low noise district, and when surpassing this threshold value, iteration will stop.

8. device according to claim 6, it is characterized in that: whether described submatrix sign bit changes the sign bit that correction verification module judge that every second son row upgrades the front and back information bit and changes, its sign bit by information bit before and after upgrading carries out exclusive-OR operation, then carries out AND-operation and obtain result.

9. device according to claim 6, it is characterized in that: whether described son row sign bit changes the sign bit that correction verification module judge that every second son row upgrades the front and back information bit and changes, the sign bit of the submatrix of the capable renewal of its cumulative book changes judged result, after the cumulative end of one's own profession, if accumulation result is zero, output 1, otherwise export 0.

10. device according to claim 6 is characterized in that: described high noise district code word correction verification module carries out accumulation calculating by the input data that the capable sign bit of antithetical phrase changes judge module, and result of calculation is kept in himself register; Then compare with threshold value, if more than or equal to high noise district's check results output 1 of threshold value, otherwise export 0.

11. device according to claim 6 is characterized in that: described low noise district code word correction verification module compares with the threshold value that obtains from threshold value table according to the iterations of inputting and obtains check mark.

12. device according to claim 6 is characterized in that: described check results generation module is selected the code word check mark in height noise district according to the flag bit in the threshold value look-up table.

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