CN102195740A - Method and device for performing simplified decoding checking by low density parity check codes - Google Patents

Abstract

The invention relates to a method and a device for performing simplified decoding checking by low density parity check codes, which belong to the technical field of communication. In the method and the device, a checking matrix is not required in checking. In an area with a low signal to noise ratio, different iteration number threshold values are set according to different signal to noise ratios, and in the area with a high signal to noise ratio, number threshold values of sub-rows according to the different signal to noise ratios, wherein sign bits of information bits are continuously invariable before and after the sub-rows are updated. When the threshold values are exceeded, iterative decoding is finished. Compared with the conventional methods in which the checking matrix participates in the checking, the invention avoids the use of the checking matrix, greatly reduces the calculated amount of checking calculation of each time and reduces the bandwidth requirements of a memory, thereby reducing hardware overhead, saving power consumption and reducing the area.

Description

The simplification decoding method of calibration and the device of low density parity check code

Technical field

The present invention relates to the forward error correction technique in the communications field, particularly the decoding method of calibration and the device of low density parity check code.

Background technology

Low density parity check code (LDPC) is a kind of error correcting code that was at first proposed in 1962 by Gallager.The main thought of low density parity check code is with low-density check matrix notation block code, so that reduce the complexity of block code coding and decoding, and can use iterative decoding algorithm, thereby make the restriction of code length relax, can use long code to approach the Shannon channel capacity.The performance of non-canonical LDPC sign indicating number not only is better than canonical LDPC sign indicating number, even also is better than Turbo code, is at present known near the sign indicating number of shannon limit, and best performance of having announced and shannon limit only differ 0.0045dB.Owing to its good coding efficiency, be easy to carry out theory analysis and research, decipher simple and practicable parallel work-flow, advantages such as suitable hardware realization are used in plurality of communication systems at present.For example standards such as China Digital TV terrestrial broadcasting standard (DMB-TH), DVB-S2,802.11n, WIMAX have all adopted the LDPC sign indicating number.

The LDPC sign indicating number belongs to linear block codes.The LDPC sign indicating number can represent that the size of the row of this check matrix is N by check matrix, and the size of row is M, code check R=(N-M)/N.The number of contained in every row " 1 " is called capable the weight in the check matrix, and the number of contained in every row " 1 " is called column weight.Rule LDPC sign indicating number is meant that capable weights all in the check matrix equates that all column weights also equate.Irregular LDPC codes is similar to regular LDPC sign indicating number, but exists heavy and other row of row to weigh different row in the check matrix in all row, has the column weight row different with other column weights in perhaps all row.As shown in Figure 1, code check R=(7-4)/7=3/7, the row of first row heavily are the column weight position 2 of 3, the first row, because the row of the third line heavily is 2, and the row of other row heavily is 3, so this LDPC sign indicating number is non-regular code.Check matrix is a kind of sparse matrix, and the number of " 1 " is very rare in the matrix, for example in the DMB-TH standard in the check matrix of 0.4 code check the density of " 1 " only be 0.001.The present invention is main relevant with the decoding of LDPC sign indicating number, introduces the decoding algorithm of LDPC sign indicating number below.

At present, the researcher has proposed that multiple algorithm principle is similar based on putting the decoding algorithm that letter transmits, and its main difference is the information transmitted.Minimum-sum algorithm and the Mansour of Illinois, America university that main decoding algorithm has people such as putting letter transmission (BP) algorithm, MPC Fossorier to propose, M.M. and Shanbhag, the TDMP algorithm that N.R. proposes.Because the TDMP algorithm is accelerated iteration speed, reduce decoding delay, the Mansour of Illinois, America university, M.M. and Shanbhag, N.R. proposes the TDMP algorithm.TDMP algorithm not only amount of calculation is little, and saves memory data output, and this helps reducing the ldpc decoder area, reduces power consumption.

For the ease of understanding the present invention, below the TDMP algorithm is carried out brief mathematical description.

This algorithm is primarily aimed at the irregular LDPC codes that check matrix meets the AA framework.So-called AA framework is meant that this check matrix can be divided into S1 * S2 submatrix, and promptly to be divided into S1 capable for check matrix, and every row is divided into the S2 row again, and " 1 " number can be above 1 in every row and the every row in each submatrix after the decomposition.In the present invention, so-called son row is meant that the S1 that check matrix is divided into is capable; So-called submatrix is meant the S2 row that each son row is broken down into again.As shown in Figure 3, matrix is divided into S1=4 son row, and each son row can be divided into S2=8 son row again, divides for S1 * S2=32 submatrix altogether, and each submatrix is 3 * 3 matrixes.Minimum-sum algorithm is adopted in the verification of this algorithm and the renewal of information node, and basic procedure is as follows:

(a) information initializing.Initializing variable nodal information Lq _vBe initial channel information, initialization check-node information R _CvBe zero.

(b) information iterative computation.R _CvThe information that check-node c transmits to variable node v when calculating for current submatrix is capable.R _Cv' be the last sub information that check-node c transmits to variable node v when calculating of going.N (c)/v represents the set of the remaining variables node except variable node v that links to each other with check-node c.N (v) represents the set of all variable nodes of linking to each other with check-node c.Lq _vThe set of all the other check-nodes except check-node c that the last son row of ' expression links to each other with variable node v when calculating.Lq _vThe information of representing all check-nodes of linking to each other with variable node v in the current son row with.The calculating of equation (1) and (2) is carried out based on child is capable, finishes the renewal of check-node information.After the check-node information calculations of each son row is finished,, finish the renewal of variable node information according to equation (3).

Lq′ _v＝Lq _v-R′ _cv (1)

$R_{\mathrm{cv}}=\underset{v\∈N\left(c\right)/v}{\mathrm{\Π}}\mathrm{Sign}\left({{\mathrm{Lq}}^{\′}}_v\right)\underset{v\∈N\left(c\right)/v}{\mathrm{Min}}\left(\right|{{\mathrm{Lq}}^{\′}}_v\left|\right)---\left(2\right)$

${\mathrm{Lq}}_v=\underset{m\∈N\left(v\right)}{\mathrm{\Σ}}{R}_{\mathrm{cv}}$

$={{\mathrm{Lq}}^{\′}}_v+R_{\mathrm{cv}}---\left(3\right)$

(c) decoding verification.The Lq of a sub-row matrix _vAfter calculating is finished, according to Lq _vTranslate code word, Lq _v＜0 code word bits C (v)=1, otherwise C (v)=0, shown in equation (4).Carry out verification according to check matrix H then, verification is calculated as equation (5), i.e. the inner product of compute codeword bit and the every row of H matrix.Function m od (x, 2) expression x Modulo-two operation.Inner product module 2 is 0, then this row verification succeeds.If all provisional capital verification succeeds of H matrix, then decision codeword is correct, and successfully decoded flag bit F is 1, stops (a) step information iterative computation.Otherwise continue (b) step and (c) go on foot.When reaching maximum iteration time,, withdraw from whole iterative process by force no matter whether successfully decoded.

$C\left(v\right)=\left\{\begin{array}{cc}1& {\mathrm{Lq}}_v<0\\ 0& {\mathrm{Lq}}_v\&GreaterEqual;0\end{array}\right.---\left(4\right)$

$F=(\underset{m=1}{\overset{M}{\mathrm{\&Sigma;}}}\mathrm{mod}(\underset{n=1}{\overset{N}{\mathrm{\&Sigma;}}}C\left(v\right)\&times;H(m,n),2)==0)---\left(5\right)$

In the TDMP algorithm flow, after each son row check-node information calculations was finished, the new check-node value of information had been improved decoding speed by in the renewal of substitution variable node.The more typical minimum-sum algorithm of data throughput is doubled.Simultaneously, owing to need not preserve initial channel information and variable node information Lq ' _n, saved memory greatly, reduced chip area, reduced power consumption.

But in this algorithm flow,, therefore produced verification and calculated validity problem owing to after the check-node information and variable node information of the intact son row of every calculating, all need the code word that translates is carried out verification.From formula (5) as can be seen, when carrying out the iteration judgement, need carry out multiplication of matrices, this has just introduced complicated calculating, not only require to increase logical circuit to improve the parallel processing capability of verification computing hardware, and require memory (particularly check matrix memory) that sufficiently high bandwidth can be provided, then 1 be difficult to reach or the cost of needs very high.Therefore, be necessary to study better iteration terminating method and solve this problem.

Summary of the invention

The purpose of this invention is to provide a kind of LDPC method of calibration and device, to overcome the deficiency of existing calibration technology.The present invention mainly is at the check matrix that meets the AA framework.This method of calibration does not need check matrix is operated when a verification is calculated in the matrix, only the change of the sign bit before and after each the renewal is calculated.This greatly reduces amount of calculation, has reduced hardware consumption, can satisfy system power dissipation, area and rate request better.

The invention provides a kind of method of calibration of low density parity check code, this method comprises the setting of threshold value table, low noise district code word verification, the code word verification of high noise district and four steps of check results output, wherein, at first a threshold value table is set according to emulation, during iterative decoding, from threshold value table, obtain corresponding threshold value according to the code check and the signal to noise ratio of enter code word; In the process of iteration, code word verification of high noise district and the code word verification of low noise district are judged and the output verification sign according to threshold value respectively; Check results is selected the still check mark in low noise district of high noise district according to the flag bit that obtains in the threshold value table, and output decoding termination flag; When the decoding termination flag is 1, stop iteration.

The present invention also provides a kind of decoding calibration equipment of low density parity check code, this device comprises that controller module, threshold value table memory module, submatrix sign bit change judge module, son row sign bit changes judge module, high noise district code word verification module, low noise district code word calibration mode block sum check generation module as a result, wherein, controller module is controlled the operation of whole device; The parameter that the threshold value table memory module stores sets in advance; The submatrix sign bit changes judge module and judges whether the sign bit of a sub-matrix update front and back information bit changes; The sub sign bit change judge module of going judges whether the sign bit of a son row renewal front and back information bit changes; The number that code word verification module in high noise district is gone according to the immovable continuous son of the capable sign bit of child compares with the threshold value that obtains from threshold value table and obtains judged result; Low noise district code word verification module compares the output result to the iterations of input and the threshold value that obtains from threshold value table; The check results generation module is handled the check results in high noise district and low noise district is handled, and produces the decoding termination flag.

The advantage of the inventive method comprises:

(1) during the intact laggard row decoding verification of every capable submatrix iterative computation, because this method stops only needing to carry out the comparison of iterations in low noise district iteration, carrying out iteration in high noise district by the constant continuous son row number of the sign bit of information bit before and after relatively the son row upgrades stops, do not need to carry out the multiplication of matrices computing, significantly reduced amount of calculation.

(2) the present invention has greatly reduced the bandwidth requirement of H matrix storage owing to do not need reading of data from the H matrix.

(3) the present invention only is the data of the sign bit of current renewal owing to what compare at every turn, has reduced the bandwidth requirement of code word memory.The minimizing of readout code word memory number of times helps saving power consumption.

Description of drawings

Fig. 1 is the check matrix that the LDPC sign indicating number is adopted;

Fig. 2 is the representation that meets the H matrix of AA framework;

Fig. 3 is the internal structure of configuration parameter information table;

Fig. 4 is checking process figure of the present invention;

Fig. 5 is a control device structured flowchart of the present invention;

Fig. 6 is that submatrix sign bit of the present invention changes the judge module structure chart;

Fig. 7 is that the present invention's row sign bit changes the judge module structure chart;

Fig. 8 is the high noise of a present invention district code word calibration mode block structure schematic diagram;

Fig. 9 is the low noise district of a present invention code word calibration mode block structure schematic diagram;

Figure 10 is a check results output module schematic diagram of the present invention.

Embodiment

Further specify the solution of the present invention below in conjunction with embodiment and accompanying drawing.

The method of calibration that the present invention proposes comprises following content:

(1), a threshold value table is set for the code word of different code checks and signal to noise ratio.As shown in Figure 3, this threshold value table comprises four parts: signal to noise ratio (Eb/N0), code check, threshold value and flag bit (flag).Signal to noise ratio and code check are input variables, and threshold value and flag bit are output variables, and input variable and output variable are one-to-one relationships.Relation is to preestablish and be stored in the holder by emulation one to one.Signal to noise ratio and code check are the attributes of enter code word.Threshold value is according to the difference of flag bit, its implication difference.When flag bit was 0, threshold value was the threshold value that is in low noise district code word, and its expression is the maximum of iterations.When flag bit was 1, threshold value was the threshold value that is in high noise district code word, and its represents it is the continuous not capable maximum number of varitron of sign bit before and after son row sign bit upgrades.Flag bit can pass through formula (6) and determine that wherein E is a signal to noise ratio, can determine by emulation.

$\mathrm{flag}=\left\{\begin{array}{cc}0& \mathrm{Eb}/\mathrm{<figure-callout\; id="0"\; label="N"\; filenames="HSA00000051084400011.png,HSA00000051084400012.png"\; state="\{\{state\}\}">N</figure-callout>}0\&le;\mathrm{<figure-callout\; id="1"\; label="E"\; filenames="HSA00000051084400011.png,HSA00000051084400012.png"\; state="\{\{state\}\}">E</figure-callout>}\\ 1& \mathrm{Eb}/\mathrm{<figure-callout\; id="0"\; label="N"\; filenames="HSA00000051084400011.png,HSA00000051084400012.png"\; state="\{\{state\}\}">N</figure-callout>}0>E\end{array}\right.---\left(6\right)$

(2) for the judgement of low noise district code word, the threshold value that order obtains from threshold value table is I _Stop, compare iterations and I _Stop, when iterations I greater than I _StopThe time, then low noise district check mark Fi puts 1, stop iterative decoding, otherwise Fi puts 0, proceeds iteration.

$F_i=\left\{\begin{array}{cc}0& I<I_{\mathrm{stop}}\\ 1& I\&GreaterEqual;I_{\mathrm{stop}}\end{array}\right.---\left(7\right)$

(3) variation of sign bit judgement.With k son row of R (k) expression, the set of all non-zero submatrices in k son row of M (R (k)) expression.As in Fig. 2, the 3rd son row is with R (3) expression, all non-zero submatrices in the sub-row 3 of M (R (3)) expression 2,4,8}.

In the iterative decoding process of LDPC, iteration all can be upgraded variable node information each time.The sign change of variable node information before and after formula (8) expression submatrix m upgrades.Wherein, s _nRepresent the symbol of n variable node information before upgrading in the submatrix, s _n' represent and upgrade the symbol of n variable node information afterwards in the submatrix.

Represent XOR, if the sign bit before and after promptly upgrading is identical then be 1, otherwise the result is 0.The result of gained carries out position and computing then, operator operator ﹠amp;

The sign bit that sign bit before and after all information bits of a sub-row are upgraded changes before and after the information bit renewal that is equivalent in all non-zero submatrices changes, so whether sign bit does not change and can judge by formula (9) before and after the renewal of k son row, if T ^(k) _CounterEqual 0, illustrate that then k sub-row renewal front and back sign bit do not have change,, illustrate that then k the sub renewal front and back sign bit of going changes if greater than 0.

${T^{\left(k\right)}}_{\mathrm{counter}}=\underset{j\&Element;M\left(R\left(k\right)\right)}{\mathrm{\&Sigma;}}c(k,j)---\left(9\right)$

The immovable number in son row continuous symbol position is calculated by formula (10), if the sign bit of k all information bits of son row does not change, then the constant number of son row sign bit adds 1 continuously, otherwise zero clearing.

$T_{\mathrm{counter}}=\left\{\begin{array}{cc}{T}_{\mathrm{counter}}+1& {T^{\left(k\right)}}_{\mathrm{counter}}\&NotEqual;0\\ T_{\mathrm{counter}}& {T^{\left(k\right)}}_{\mathrm{counter}}=0\end{array}\right.---\left(10\right)$

(4) for the judgement of high noise district code word, making in the threshold value table threshold parameter that obtains according to code check and signal to noise ratio is T _Stop, high noise district termination flag is F _h, as shown in Equation (11), as the value T of counter _CounterMore than or equal to T _StopThe time, F _hPut 1, will stop iteration, otherwise F _hPut 1, proceed iteration.

$F_h=\left\{\begin{array}{cc}0& T_{\mathrm{counter}}<T_{\mathrm{stop}}\\ 1& T_{\mathrm{counter}}\&GreaterEqual;T_{\mathrm{stop}}\end{array}\right.---\left(11\right)$

(5) check results output as shown in Equation (12), when flag equals 0, when promptly code word was in low noise district, check results F equaled F _iWhen flag equals 1, when promptly code word was in high noise district, check results F equaled F _h

$F=\left\{\begin{array}{cc}{F}_i& \mathrm{flag}=0\\ F_h& \mathrm{flag}=1\end{array}\right.---\left(12\right)$

The idiographic flow of this method as shown in Figure 4, after the code word input, code check and signal to noise ratio according to code word check in corresponding threshold and flag bit from threshold value table, high noise district's verification module and low noise district's verification module produce corresponding check mark respectively, and the check results module judges that according to the flag bit that checks in the judgement symbol in the high noise of output district still hangs down the check mark in noise district from threshold value table.If the termination flag position of check results output is zero, then proceeds iteration, otherwise stop to carry out iteration.

The method of calibration according to the present invention, the device that obtains comprise that controller module, configuration parameter memory, submatrix codeword information bit sign change judge module, son row code-word symbol changes judge module, low noise district verification module, high noise district calibration mode block sum check generation module as a result.

Controller module is responsible for controlling the work of whole device.Controller module receives verification enable signal, the data-signal that bit rate signal and check matrix memory are sent here.Controller module sends the data that address signal, read-write and chip selection signal read decoding information bit memory and configuration information memory; The submatrix sign bit changes judge module and judges whether the sign bit of a sub-matrix update front and back information bit changes; The sub sign bit change judge module of going judges whether the sign bit of a son row renewal front and back information bit changes; The number that code word verification module in high noise district is gone according to the immovable continuous son of the capable sign bit of child compares with the threshold value that obtains from threshold value table and obtains judged result; Low noise district code word verification module compares the output verification sign to the iterations of input and the threshold value that obtains from threshold value table; The check results generation module is handled the check mark of high noise district and the output of low noise district, produces the decoding termination flag.

The configuration parameter memory is preserved the check matrix of 3 kinds of code checks of GB DMB-TH, because storage is constant, adopts read-only memory to realize.The data format of memory cell comprises four parts: Eb/N0 as shown in Figure 3 in the configuration parameter memory, code check, threshold value and flag bit.Eb/N0 represents the signal to noise ratio of channel.When flag bit is 0, represent the Eb/N0 of this moment to be in low noise district, threshold value is being represented iterations; When flag bit was 1, at this moment Eb/N0 of representative was in high noise district, and to change be the threshold value of zero number to sign bit continuously during threshold value was being represented and upgraded.

The submatrix code-word symbol changes judge module.As shown in Figure 6, s _nAnd s _n' represent the sign bit of information bit before and after the sub-matrix update respectively.S at first _nAnd s _n' obtain an intermediate object program F by xor operation ", after the xor operation, again the s as a result behind n the XOR ₁", s ₂" ... s _n" carry out and operation, judge whether this result is zero, if be zero, then submatrix flag bit F ' puts 1, otherwise puts 0.

Son row code-word symbol changes judge module.As shown in Figure 7, this module submatrix code-word symbol position of adding up changes the output result of judge module, when the EOL mark position enables, stop to add up, and the output accumulation result.

High noise district code word verification module.As shown in Figure 8, the output result that the capable code-word symbol of antithetical phrase changes judge module adds up, and this module produces an iteration and stops judgement symbol T _CounterIf T _CounterMore than or equal to the threshold value that obtains from threshold value table, then the output identification position is 1, otherwise is zero.

Low noise district code word verification module.As shown in Figure 9, mainly pass through the iterations threshold value I of iterations I and setting in low noise district method of calibration _StopCompare, if I is greater than threshold value I _Stop, then stop iteration, otherwise proceed iteration.When iteration stopped, output termination tag mark and output enable sign enabled, and output enable representative output identification at this moment is effective.

The check results output module.As shown in figure 10, when the judgement symbol in high noise district and low noise district enters successfully decoded sign generation module, the flag bit F that this module need be imported from the parameter configuration memory _HlJudge.When flag bit 1, export the check mark in high noise district this moment, otherwise the check mark in the low noise district of output.Stop to decipher iteration when successfully decoded when being masked as 1, otherwise proceed iteration.

Hereinafter introduce the LDPC decode procedure.

Initialization check-node sequence equals complete 0.The initialization information node is the channel information that is received.

Carry out iterative computation then.According to equation (1) and (2) calculation check sequence node R _CvAfter the check node calculation of a son row is finished, calculate variable node according to equation (3).In the calculating, because the influence of the precision of hardware need quantize variable node and check-node sequence.

The iterative computation process is constantly carried out, up to successfully decoded sign effectively or iterations reach maximum, just withdraw from iterative computation.

Finish when the capable variable node information updating of each piece, obtain deciphering code word according to equation (4).

According to method of calibration of the present invention, present embodiment at first is divided into S1 son row and S2 is listed as with the H matrix so that child is capable.The purpose of Hua Fening is consistent with the iterative computation process like this, convenient calculating.To the check matrix of 0.4 code check in the Chinese digital TV ground standard, parameter S 1=35, S2=59.Therefore, check matrix can be divided into 35 son row, and once the iteration of whole matrix can be divided into 35 second son iteration and finishes.

Fig. 5 is a calibration equipment of the present invention.Being example below with DMB-TH is described in detail the operation principle of this device.After the code word of needs decoding entered decoder, controller module produced control signal according to the code check and the verification enable signal of input.Controller module sends the data that address signal, read-write and chip selection signal read decoding information bit memory and configuration information memory; Controller module sends the submatrix sign bit and changes the data select signal of module and calculate enable signal; Controller module sends register zero clearing and the data enable signal that son row sign bit changes module; Controller module sends relatively enabling and the register reset signal of low noise district code word verification module; Controller module sends relatively enabling and the register reset signal of high noise district code word verification module; The result that controller module sends successfully decoded sign generation module selects signal and register reset signal.

When input Eb/N0 and code check, memory output parameter threshold value and flag bit.For example, when code check is 0.4, during Eb/N0=1.0dB, the flag bit of output is 0, and representative Eb/N0 at this moment is in low noise district; The threshold value of output is that 6 to represent the threshold value of the number of times that iteration stops be 6, when iterations stops iteration more than or equal to 6 the time.When code check is 0.6, during Eb/N0=2.5dB, the flag bit of output is 1, and representative Eb/N0 at this moment is in high noise district; The threshold value of output is that 35 to represent son row to upgrade the constant number of sign bit be zero continuous number more than or equal to stopping iteration at 35 o'clock.

Because the size of each submatrix of DMB-TH is 127, so at the iterative process of each submatrix, s ₁, s ₂S ₁₂₇Represent the sign bit before submatrix upgrades, s ₁', s ₂' ... s ₁₂₇' represent the sign bit after a son row upgrades.The span that makes n is 1 ... 127, s _nAnd s _n' obtain an intermediate object program s by xor operation _n', after the xor operation, again the s as a result behind 127 XORs ₁", s ₂" ... s ₁₂₇" carry out and operation, judge whether this result is zero, if be zero, then F " puts 1, otherwise puts 0.

Hang down the noise district when code word is in, iterations I derives from main control module, I _StopObtain from the configuration information memory.If I is greater than threshold value I _Stop, then stop iteration, otherwise proceed iteration.When iteration stops, output verification sign and output enable sign en_i, en_i is 1 o'clock, representative output identification F at this moment _iBe effectively, otherwise export invalid.

When code word is in high noise district, judgement symbol F ' of back output and enabler flags en_i judged in each submatrix, and the end mark parameter of son row derives from master controller, and when capable calculatings of group finished, this module produced an iteration termination judgement symbol T _CounterT _CounterWith the parameter T that from the configuration parameter memory, reads in _StopRelatively, output iteration termination flag.

When the check mark in high noise district and low noise district entered successfully decoded sign generation module, this module need be by the flag bit F that imports in the parameter configuration memory _HlJudge, and output iteration termination flag.

The effect of calibration equipment below is described:

(1) this device amount of calculation is little, and verification speed is fast.This device is not owing to need to carry out the multiplication of matrices computing, only need some simple with, XOR, addition and relatively wait operation, therefore the sign bit that only needs information bit when carrying out verification has relatively saved operand greatly.127 the tunnel is parallel when carrying out verification calculating, 1 submatrix of 1 processing.

(2) bandwidth requirement of this device is low, saves memory.This device does not need to read the check matrix memory when verification is calculated, do not need to read the information bit memory during verification simultaneously, because as long as the sign bit of temporary original code word, and the sign bit of decoding code word can obtain before the writing information bit memory.The reading times of memory is few, and bandwidth requirement is low, and the memory of can be multiplexing using during iterative computation is realized, thereby saved memory.

Claims (12)

1. the simplification method of calibration of a low density parity check code, it is characterized in that: this method comprises the setting of threshold value table, low noise district code word verification, the code word verification of high noise district and four steps of check results output, wherein, at first a threshold value table is set according to emulation, during iterative decoding, from threshold value table, obtain corresponding threshold value according to the code check and the signal to noise ratio of enter code word; In the process of iteration, code word verification of high noise district and the code word verification of low noise district are judged and the output verification sign according to threshold value respectively, check results is selected the still check mark in low noise district of high noise district according to the flag bit that obtains in the threshold value table, and output decoding termination flag.When check results is 1, stop iteration.

2. decoding method of calibration according to claim 1, it is characterized in that: being provided with in the step of described threshold value table, threshold value table comprises four parts: signal to noise ratio (Eb/N0), code check, threshold value and flag bit, wherein, threshold value is according to signal to noise ratio and code check setting, mark position to distinguish high s/n ratio district and low signal-to-noise ratio district, 1 sign high s/n ratio district, 0 sign low signal-to-noise ratio district.

3. decoding method of calibration according to claim 1, it is characterized in that: in the step of described low noise district's code word verification, at first from threshold value table, obtain threshold value according to signal to noise ratio and code check, then iterations and this threshold, if iterations is 1 more than or equal to the then low noise district of threshold value code word check mark, otherwise is 0.

4. decoding method of calibration according to claim 1, it is characterized in that: in the step of described high noise district's code word verification, at first from threshold value table, obtain threshold value according to signal to noise ratio and code check, then this threshold value and the continuous immovable son row sum of son row update calculation front and back sign bit are compared, total as the continuous immovable son row of sign bit before and after the capable update calculation of fruit more than or equal to this threshold value, then high noise district code word check mark is 1, otherwise is 0.

5. decoding method of calibration according to claim 1, it is characterized in that: in the step of described check results output, obtain flag bit according to signal to noise ratio and code check from threshold value table, flag bit is to export high noise district check mark at 1 o'clock, and flag bit is the 0 o'clock low noise district of output check mark.

6. the decoding calibration equipment of a low density parity check code, it is characterized in that: this device comprises that controller module, threshold value table memory module, submatrix sign bit change the verification module, son row sign bit changes verification module, high noise district code word verification module, low noise district code word calibration mode block sum check generation module as a result, wherein, controller module is controlled the operation of whole device; The parameter that the threshold value table memory module stores sets in advance; The submatrix sign bit changes judge module and judges whether the sign bit of a sub-matrix update front and back information bit changes; The sub sign bit change judge module of going judges whether the sign bit of a son row renewal front and back information bit changes; Code word verification module in high noise district compares the output verification sign according to the number of the immovable continuous son row of the capable sign bit of child with the threshold value that obtains from threshold value table; Low noise district code word verification module compares the output verification sign to the iterations of input and the threshold value that obtains from threshold value table; The check results generation module is handled the check results in high noise district and low noise district is handled, and output decoding termination flag.

7. device according to claim 6 is characterized in that: in described threshold value table memory module, memory is a read-only memory, stores the threshold value in high noise district and low noise district, also stores the distinctive mark in height noise district simultaneously; The threshold value in low noise district is represented the threshold value of iterations; The threshold value in high noise district is represented the threshold value of the count value that sign bit is constant after the continuous sub-row iteration, no matter is in high noise district or low noise district, and when surpassing this threshold value, iteration will stop.

8. device according to claim 6, it is characterized in that: whether described submatrix sign bit changes the each sub sign bit that upgrades the front and back information bit of going of judge module judgement and changes, its sign bit by information bit before and after upgrading carries out exclusive-OR operation, carries out AND-operation again and obtains the result.

9. device according to claim 6, it is characterized in that: whether the sign bit of the each son row of described son row sign bit change judge module judgement renewal front and back information bit changes, the sign bit of the submatrix of the capable renewal of its book that adds up changes judged result, after the end that adds up of one's own profession, if accumulation result is zero, output 1, otherwise export 0.

10. device according to claim 6 is characterized in that: described high noise district's code word verification module is carried out accumulation calculating by the input data that the capable sign bit of antithetical phrase changes judge module, and result of calculation is kept in himself register; Compare with threshold value then,, otherwise export 0 if more than or equal to the then high noise of threshold value district check results output 1.

11. device according to claim 6 is characterized in that: described low noise district's code word verification module compares with the threshold value that obtains from threshold value table according to the iterations of being imported and obtains check mark.

12. device according to claim 6 is characterized in that: described check results generation module according to according to the flag bit in the threshold value look-up table, select the code word check mark in height noise district, decoding finishes the back and removes check results.

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