CN102195651A - High-speed analogue-digital converter - Google Patents
High-speed analogue-digital converter Download PDFInfo
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- CN102195651A CN102195651A CN2011101430145A CN201110143014A CN102195651A CN 102195651 A CN102195651 A CN 102195651A CN 2011101430145 A CN2011101430145 A CN 2011101430145A CN 201110143014 A CN201110143014 A CN 201110143014A CN 102195651 A CN102195651 A CN 102195651A
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Abstract
The invention discloses a high-speed analogue-digital converter, which relates to the field of digifax hybrid integrated circuit design. In the invention, an input signal id connected with an input end of a sampling and holding circuit to output a sampling and holding signal; the sampling and holding signal is connected with an input end of a 2n-times multiplier to output 2n-times sampling and holding signals, the 2n-times sampling and holding signals are respectively connected with 2n-1 comparators as well as used as a positive input end of a feedback circuit; a reference level value of the first comparator is the reference level value of the (2n-1)th comparator, an output signal of the (2n-1)th comparator is converted into a BCD (Binary-Coded Decimal) code through a code system converting circuit, a b[(n-1):0] is outputted and the b[(n-1):0] controls n logic switches; the reference level value of the n connected logic switches is used as a negative input end of the feedback circuit, and a feedback signal is 2nD-2n-1Vrefbn-1-......-20Vrefb0.
Description
Technical field
The present invention relates to the hybrid digital-analog integrated circuit design field, analog to digital converter is widely used in Digital Analog Hybrid Circuits and the SoC system, particularly a kind of high-speed AD converter.
Background technology
Analog-to-digital conversion is the technology that analog input signal is converted to N bit word output signal.Adopt Digital Signal Processing can realize various advanced persons' adaptive algorithm easily, finish the function that analog circuit can't be realized, therefore, increasing analog is replaced by digital technology.Correspondingly be, extensive day by day as the analog-to-digital application of bridge between analogue system and the digital system.
Common analog-digital converter structure mainly contains integration type, successive approximation, flash structure, pipeline structure, loop structure analog to digital converter, wherein the loop structure analog to digital converter is used very extensive having advantage aspect the trade off performance such as speed, power consumption and area.
The inventor finds to exist at least in the prior art following shortcoming and defect in realizing process of the present invention:
In order further to improve the speed of circulation AD converter, need to increase the circuit design difficulty, simultaneously the area of increasing modulus transducer.
Summary of the invention
For significantly not increasing on the basis of hardware area and design difficulty, further improve the speed of circulation AD converter, the invention provides a kind of high-speed AD converter, see for details hereinafter and describe:
A kind of high-speed AD converter, described high-speed AD converter comprises: sampling and holding circuit, 2
nTimes multiplier, 2
n-1 comparator, code system change-over circuit, a n logic switch and feedback circuit, wherein, the value of n is the positive integer more than or equal to 1,
Input signal links to each other with the input of described sampling and holding circuit, output sampling and inhibit signal; Described sampling and inhibit signal and described 2
nThe input of times multiplier links to each other, output 2
nSampling and inhibit signal, described 2
nSampling and inhibit signal are respectively with described 2
n-1 comparator links to each other, the while described 2
nSampling and inhibit signal are as the positive input terminal of described feedback circuit;
The reference level value of first comparator is
Wherein Vref is the intermediate level value of quantized interval, the 2nd
nThe reference level value of-1 comparator is
With described 2
nThe output signal of-1 comparator is converted to binary-coded decimal through described code system change-over circuit, output b[n-1:0], by described b[n-1:0] the described n of a control logic switch; The level value that a described n logic switch is continuous is as the negative input end of described feedback circuit, and feedback signal is 2
nD-2
N-1Vrefb
N-1-...-2
0Vrefb
0
The beneficial effect of technical scheme provided by the invention is:
The invention provides a kind of high-speed AD converter, the present invention is based on traditional circulation AD converter ADC structure, built-in high speed flash ADC and simple logic circuit can improve analog-to-digital conversion rate; By regulating the adjustment that built-in flash ADC figure place, multiplier multiple and feedback signal can realize conversion speed flexibly; Do not compare not obviously increase with traditional circulation AD converter adc circuit area, can realize the optimal design of speed and area.
Description of drawings
The structural representation of traditional circulation AD converter that Fig. 1 provides for prior art;
Fig. 2 is the structural representation of the high-speed AD converter of embedded 2bit provided by the invention;
Fig. 3 is the structural representation of the high-speed AD converter of embedded many bit provided by the invention.
Shown in components listed is listed as follows in the accompanying drawing:
Vin: input signal; S/H: sampling and holding circuit;
Multiplier: mlultiplying circuit; Comparator: comparator;
Vref: reference level; BCD: code system change-over circuit;
Logic: logic analysis circuit.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, embodiment of the present invention is described further in detail below in conjunction with accompanying drawing.
For significantly not increasing on the basis of hardware area and design difficulty, further improve the speed of circulation AD converter, the embodiment of the invention provides a kind of high-speed AD converter, sees for details hereinafter to describe:
Referring to Fig. 1, tradition circulation AD converter input signal Vin is behind sampling and holding circuit S/H, enter and take advantage of 2 circuit Multiplier, its output enters comparator C omparator and reference level Vref relatively, and the output signal of comparator C omparator is as the output result, and relevant with feedback signal, even be output as " 1 ", then the 2D-Vref feedback is taken advantage of 2 circuit Multiplier inputs,, the 2D feedback is taken advantage of 2 circuit Multiplier inputs if be output as " 0 ".Through multiplying and comparison once, produce 1 data transaction, finish the data transaction of n position and need pass through n clock cycle.
In order significantly not increase under the prerequisite of analog to digital converter ADC area, further improve the speed of analog to digital converter ADC, the embodiment of the invention by embedded flashADC, has effectively improved the conversion speed of analog to digital converter ADC on the basis of existing circulation AD converter.
A kind of high-speed AD converter referring to Fig. 2 and Fig. 3, comprising: sampling and holding circuit S/H, 2
nTimes multiplier Multiplier, 2
n-1 comparator C omparator, code system change-over circuit BCD, a n logic switch and feedback circuit, wherein, the value of n is the positive integer more than or equal to 1,
Input signal Vin links to each other with the input of sampling with holding circuit S/H, output sampling and inhibit signal D; Sampling and inhibit signal D and 2
nThe input of times multiplier Multiplier links to each other, output 2
nSampling and inhibit signal 2
nD, 2
nSampling and inhibit signal 2
nD is respectively with 2
n-1 comparator C omparator links to each other, the while 2
nSampling and inhibit signal 2
nD is as the positive input terminal of feedback circuit;
The reference level value of the first comparator C omparator is
Wherein Vref is the intermediate level value of quantized interval, the 2nd
nThe reference level value of-1 comparator C omparator is
With 2
nThe output signal of-1 comparator C omparator is converted to binary-coded decimal through code system change-over circuit BCD, output b[n-1:0], pass through b[n-1:0] n logic switch of control; The level value that n logic switch is continuous is as the negative input end of feedback circuit, and feedback signal is 2
nD-2
N-1Vrefb
N-1-...-2
0Vrefb
0
Be example with embedded 2bit flash ADC below, analyze its operation principle, see for details hereinafter and describe:
A kind of high-speed AD converter referring to Fig. 2, comprising: sampling and holding circuit S/H, 2
2Times multiplier Multiplier, the first comparator C omparator, the second comparator C omparator, the 3rd comparator C omparator, code system change-over circuit BCD, first logic switch, second logic switch and feedback circuit,
Input signal Vin links to each other with the input of sampling with holding circuit S/H, output sampling and inhibit signal D; Sampling and inhibit signal D and 2
2Times multiplier Multiplier input links to each other, output 2
2Sampling and inhibit signal 2
2D, 2
2Sampling and inhibit signal 2
2D links to each other with the 3rd comparator C omparator with the first comparator C omparator, the second comparator C omparator respectively, the while 2
2Sampling and inhibit signal 2
2D is as the positive input terminal of feedback circuit; The reference level value of the first comparator C omparator is
The reference level value of the second comparator C omparator is Vref, and the reference level value of the 3rd comparator C omparator is
When 2
2Sampling and inhibit signal 2
2D greater than
The time (
), first comparator C omparator output, 1, second comparator C omparator output the 1, the 3rd comparator C omparator output 1; When 2
2Sampling and inhibit signal 2
2D less than
And during greater than Vref (
), first comparator C omparator output, 0, second comparator C omparator output the 1, the 3rd comparator C omparator output 1; When 2
2Sampling and inhibit signal 2
2D less than Vref and greater than
The time (
), first comparator C omparator output, 0, second comparator C omparator output the 0, the 3rd comparator C omparator output 1; When 2
2Sampling and inhibit signal 2
2D less than
The time (
), first comparator C omparator output, 0, second comparator C omparator output the 0, the 3rd comparator C omparator output 0; The output signal of the first comparator C omparator, the second comparator C omparator and the 3rd comparator C omparator is converted to binary-coded decimal through code system change-over circuit BCD, with output signal b[1:0] be converted to b
1b
0, pass through b
1b
0Come the control logic switch; Feedback signal is 2
2D-2Vrefb
1-Vrefb
0, be about to output signal 111 and be converted to b
1Equal 1, b
0Equal 1; Output signal 011 is converted to b
1Equal 1, b
0Equal 0; Output signal 001 is converted to b
1Equal 0, b
0Equal 1; Output signal 000 is converted to b
1Equal 0, b
0Equal 0; Pass through b
1And b
0(11,10,01 and 00) comes the control logic switch; Work as b
1And b
0Equal at 11 o'clock, first logic switch and the second logic switch closure, 2Vref and Vref are as the negative input end of feedback circuit, and feedback signal is: 2
2D-2
1Vref-2
0Vref; Work as b
1And b
0Equal at 10 o'clock, the first logic switch closure, second logic switch disconnects, and 2Vref is as the negative input end of feedback circuit, and feedback signal is: 2
2D-2
1Vref; Work as b
1And b
0Equal at 01 o'clock, first logic switch disconnects, the second logic switch closure, and Vref is as the negative input end of feedback circuit, and feedback signal is: 2
2D-2
0Vref; Work as b
1And b
0Equal at 00 o'clock, first logic switch disconnects, and second logic switch disconnects, and feedback signal is: 2
2D; So far finished the analog-to-digital conversion of 2bit; Promptly finished 2 analog-to-digital conversion through a clock cycle, the more traditional circulation A DC of speed has improved 1 times.
Referring to Fig. 3, be example with embedded multidigit flash ADC, analyze its operation principle, see for details hereinafter and describe:
A kind of high-speed AD converter comprises: sampling and holding circuit S/H, 2
nTimes multiplier Multiplier, 2
n-1 comparator C omparator, code system change-over circuit BCD, a n logic switch and feedback circuit, wherein, the value of n is the positive integer more than or equal to 1,
Input signal Vin links to each other with the input of sampling with holding circuit S/H, output sampling and inhibit signal D; Sampling and inhibit signal D and 2
nTimes multiplier Multiplier input links to each other, output 2
nSampling and inhibit signal 2
nD, 2
nSampling and inhibit signal 2
nD is respectively with 2
n-1 comparator C omparator links to each other, the while 2
nSampling and inhibit signal 2
nD is as the positive input terminal of feedback circuit; The reference level value of the first comparator C omparator is
The 2nd
nThe reference level value of-1 comparator C omparator is
When 2
nSampling and inhibit signal 2
nD greater than
The time (
), 2
n-1 comparator output 1; When 2
nSampling and inhibit signal 2
nD less than
The time (
), 2
n-1 comparator C omparator output 0; 2
nThe output signal of-1 comparator C omparator is converted to binary-coded decimal through the code system change-over circuit, output b[n-1:0], output signal is converted to b
N-1b
N-2... b
0, pass through b
N-1b
N-2... b
0Control n logic switch; Feedback signal is 2
nD-2
N-1Vrefb
N-1-...-2
0Vrefb
0, so far finished the analog-to-digital conversion of many bit.
In sum, the embodiment of the invention provides a kind of high-speed AD converter, and the embodiment of the invention is based on traditional circulation AD converter ADC structure, and built-in high speed flash ADC and simple logic circuit can improve analog-to-digital conversion rate; By regulating the adjustment that built-in flash ADC figure place, multiplier multiple and feedback signal can realize conversion speed flexibly; Do not compare not obviously increase with traditional circulation AD converter adc circuit area, can realize the optimal design of speed and area.
It will be appreciated by those skilled in the art that accompanying drawing is the schematic diagram of a preferred embodiment, the invention described above embodiment sequence number is not represented the quality of embodiment just to description.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (1)
1. a high-speed AD converter is characterized in that, described high-speed AD converter comprises: sampling and holding circuit, 2
nTimes multiplier, 2
n-1 comparator, code system change-over circuit, a n logic switch and feedback circuit, wherein, the value of n is the positive integer more than or equal to 1,
Input signal links to each other with the input of described sampling and holding circuit, output sampling and inhibit signal; Described sampling and inhibit signal and described 2
nThe input of times multiplier links to each other, output 2
nSampling and inhibit signal, described 2
nSampling and inhibit signal are respectively with described 2
n-1 comparator links to each other, the while described 2
nSampling and inhibit signal are as the positive input terminal of described feedback circuit;
The reference level value of first comparator is
Wherein Vref is the intermediate level value of quantized interval, the 2nd
nThe reference level value of-1 comparator is
With described 2
nThe output signal of-1 comparator is converted to binary-coded decimal through described code system change-over circuit, output b[n-1:0], by described b[n-1:0] the described n of a control logic switch; The level value that a described n logic switch is continuous is as the negative input end of described feedback circuit, and feedback signal is 2
nD-2
N-1Vrefb
N-1-...-2
0Vrefb
0
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|---|---|---|---|
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104038230A (en) * | 2014-06-26 | 2014-09-10 | 天津大学 | Focal-plane block-matrix transformation column-parallel arithmetic analog-digital conversion method and converter |
| CN104702287A (en) * | 2015-03-18 | 2015-06-10 | 四川特伦特科技股份有限公司 | High-speed modulus processing circuit |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104038230A (en) * | 2014-06-26 | 2014-09-10 | 天津大学 | Focal-plane block-matrix transformation column-parallel arithmetic analog-digital conversion method and converter |
| CN104038230B (en) * | 2014-06-26 | 2017-03-08 | 天津大学 | Focal plane block matrix conversion row parallel arithmetic D conversion method and transducer |
| CN104702287A (en) * | 2015-03-18 | 2015-06-10 | 四川特伦特科技股份有限公司 | High-speed modulus processing circuit |
| CN104702287B (en) * | 2015-03-18 | 2017-12-01 | 四川特伦特科技股份有限公司 | A kind of high speed analog-digital conversion process circuit |
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| CN102195651B (en) | 2014-03-12 |
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Effective date of registration: 20201116 Address after: 226316 machinery and Electronics Industrial Park (Zhouwei Village), Xianfeng Town, Tongzhou District, Nantong City, Jiangsu Province Patentee after: NANTONG NANPING ELECTRONIC TECHNOLOGY Co.,Ltd. Address before: 300072 Tianjin City, Nankai District Wei Jin Road No. 92 Patentee before: Tianjin University |