CN102194808B - 功率型电极上下设置的led集成封装器件及其封装方法 - Google Patents
功率型电极上下设置的led集成封装器件及其封装方法 Download PDFInfo
- Publication number
- CN102194808B CN102194808B CN2011101185158A CN201110118515A CN102194808B CN 102194808 B CN102194808 B CN 102194808B CN 2011101185158 A CN2011101185158 A CN 2011101185158A CN 201110118515 A CN201110118515 A CN 201110118515A CN 102194808 B CN102194808 B CN 102194808B
- Authority
- CN
- China
- Prior art keywords
- led chip
- row
- led
- electrode
- line layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
Landscapes
- Led Device Packages (AREA)
Abstract
本发明涉及一种功率型电极上下设置的LED芯片的集成封装器件及其封装方法,在铝块上设有绝缘层,互相隔离的反射线路层排列组合在绝缘层上,LED芯片的P型欧姆接触电极端固晶在各自的反射线路层上;金属键合线将第一排的第一个LED芯片的N型欧姆接触电极与第二个LED芯片的反射线路层连接,直至第一排的全部LED芯片连接成第一排LED芯片串联结构,第一排至第k排LED芯片串联结构的第一个反射线路层都与阳极接出端连接,其中最后一个LED芯片的N型欧姆接触电极都与阴极接出端连接,形成第一排至第k排LED芯片串联结构的并联;最后涂覆荧光粉,包覆封装。本发明具有散热效果好,高驱动电压,发光效率高的有益效果。
Description
技术领域
本发明涉及一种LED集成封装器件及其封装方法,特别是一种功率型电极上下设置的LED集成封装器件及其封装方法。
背景技术
LED(发光二极管)集成封装因其总体积小,每瓦功率单价低,配光较简单等优点,已成为一种照明封装趋势。
目前,市场上白光集成封装用的芯片主要为同侧电极蓝宝石衬底LED芯片,因其LED芯片衬底蓝宝石是绝缘的,所以在集成封装时能够根据器件需要做成所需的串并联电路。如图1为一典型同侧电极LED芯片的串联结构图,其中1为导电的铝块,2为金属键合线,3为N型欧姆接触电极,4为N型外延层,5为P型欧姆接触电极,6为P型外延层,7为绝缘的蓝宝石衬底。
对于电极在芯片上下两侧的LED芯片,即电极上下设置的LED芯片,也称薄膜转移芯片,比较容易实现并联,如图2所示,其中1为导电的铝块,2为金属键合线,3为N型欧姆接触电极,4为N型外延层,5为P型欧姆接触电极,6为P型外延层。由于芯片底部为一导电电极P型欧姆接触电极5,在导电的铝块上无法形成串联电路,所形成的多芯片集成器件驱动电压低,电流极大,对于LED器件应用及能源转换效率均不理想。
发明内容
本发明的目的是提供一种具有散热效果好,高驱动电压,发光效率高的功率型电极上下设置的LED集成封装器件及其封装方法。
本发明的技术方案是:一种功率型电极上下设置的LED集成封装器件,包括上下设置电极的LED芯片的N型欧姆接触电极、N型外延层、P型外延层和P型欧姆接触电极自上而下依次叠加;在铝块上设有绝缘层,互相隔离的反射线路层排列组合在绝缘层上,所述上下设置电极的LED芯片的P型欧姆接触电极端固晶在各自的反射线路层上;金属键合线将第一排的LED芯片中的第一个LED芯片的N型欧姆接触电极与第二个LED芯片的反射线路层连接,金属键合线将第二个LED芯片的N型欧姆接触电极与第三个LED芯片的反射线路层连接,以此类推,金属键合线将第m个LED芯片的N型欧姆接触电极与第m+1个LED芯片的反射线路层连接,直至第一排的全部LED芯片连接成第一排LED芯片串联结构;第二排的全部LED芯片也同第一排的LED芯片一样连接成第二排LED芯片串联结构,以此类推,第k排的全部LED芯片也同第一排的LED芯片一样连接成第k排LED芯片串联结构;第一排至第k排中各排的LED芯片串联结构的第一个LED芯片的反射线路层都与位于绝缘层一端的阳极接出端连接,第一排至第k排中各排的LED芯片串联结构的最后一个LED芯片的N型欧姆接触电极都与位于绝缘层另一端的阴极接出端连接,形成第一排至第k排中各排的LED芯片串联结构的并联;最后涂覆荧光粉,包覆封装。
所述绝缘层是厚度为1-30μm的氧化铝层,绝缘层的氧化铝层优选厚度为15-25μm。所述反射线路层是厚度为10-100μm的银层,反射线路层的银层优选厚度为50-80μm。所述金属键合线为金线、铝线或者铜线。
一种功率型电极上下设置的LED集成封装器件的封装方法,包括下列步骤:
a) 在铝块上通过湿法氧化法或者电解氧化法制备一层绝缘层;
b) 在形成之后的绝缘层上通过真空蒸发法或者磁控溅射法制备互相隔离排列组合的反射线路层;
c) 将上下设置电极的LED芯片的P型欧姆接触电极端固晶在各自的反射线路层上;
d) 用金属键合线将第一排的LED芯片中的第一个LED芯片的N型欧姆接触电极与第二个LED芯片的反射线路层连接,用金属键合线将第二个LED芯片的N型欧姆接触电极与第三个LED芯片的反射线路层连接,以此类推,用金属键合线将第m个LED芯片的N型欧姆接触电极与第m+1个LED芯片的反射线路层连接,直至第一排的全部LED芯片连接成第一排LED芯片串联结构;第二排的全部LED芯片也同第一排的LED芯片一样连接成第二排LED芯片串联结构,以此类推,第k排的全部LED芯片也同第一排的LED芯片一样连接成第k排LED芯片串联结构;第一排至第k排中各排的LED芯片串联结构的第一个LED芯片的反射线路层都与位于绝缘层一端的阳极接出端连接,第一排至第k排中各排的LED芯片串联结构的最后一个LED芯片的N型欧姆接触电极都与位于绝缘层另一端的阴极接出端连接,形成第一排至第k排中各排的LED芯片串联结构的并联;最后涂覆荧光粉,包覆封装;
固晶在排列组合的反射线路层上的上下设置电极的LED芯片串联的个数按所需驱动电压确定,所述LED芯片串联结构并联的排数按所需电流确定;所述金属键合线为金线、铝线或铜线;
e) 涂覆荧光粉,包覆封装。
本发明的有益效果是:
1、 本发明能将排列组合的上下设置电极的LED芯片串联、并联连接,使之具有高驱动电压,发光效率高,克服了现有的上下设置电极的LED芯片在导电铝块上无法形成串联电路,致使驱动电压低、电流极大的不足。排列组合中上下设置电极的LED芯片串联的个数按所需驱动电压确定,并联的排数按所需电流确定;
2、 本发明的绝缘层是厚度为1-30μm的氧化铝层,绝缘层的优选厚度为15-25μm,氧化铝层比常规的有机绝缘层的导热性好,大大提高了绝缘层的散热效果,进而提高了功率型LED集成封装器件的寿命;
3、 反射线路层可以有效的对LED底部的光束进行反射,显著提高出光效率。
附图说明
图1是同侧电极的LED芯片串联结构示意图。
图2是上下设置电极的LED芯片并联结构示意图。
图3是单排功率型电极上下设置的LED芯片的串联结构示意图。
图4是功率型电极上下设置的LED芯片的串并联结构俯视图。
图5 是图4所示串并联结构电路原理图。
图6 是图3的局部放大图(画出上下设置电极的LED芯片的组成部分)。
附图中:1 --铝块, 2 --金属键合线, 3-- N型欧姆接触电极, 4-- N型外延层, 5-- P型欧姆接触电极, 6 --P型外延层, 7-- 蓝宝石衬底,8 --绝缘层, 9 --反射线路层, 10 --上下设置电极的LED芯片, 11 --阳极接出端, 12 --阴极接出端。
具体实施方式
下面结合附图和实施例对本发明进一步说明。
实施例1如附图3-6所示:一种功率型电极上下设置的LED集成封装器件,包括上下设置电极的LED芯片10的N型欧姆接触电极3、N型外延层4、P型外延层6和P型欧姆接触电极5自上而下依次叠加。在铝块1上设有绝缘层8,互相隔离的反射线路层9排列组合在绝缘层8上,所述上下设置电极的LED芯片10的P型欧姆接触电极5端固晶在各自的反射线路层9上;金属键合线2将第一排的LED芯片10中的第一个LED芯片10的N型欧姆接触电极3与第二个LED芯片10的反射线路层9连接,金属键合线2将第二个LED芯片10的N型欧姆接触电极3与第三个LED芯片10的反射线路层9连接,金属键合线2将第三个LED芯片10的N型欧姆接触电极3与第四个LED芯片10的反射线路层9连接,至此第一排的全部LED芯片10连接成第一排LED芯片串联结构;第二排的全部LED芯片10也同第一排的LED芯片一样连接成第二排LED芯片串联结构;第一排及第二排LED芯片串联结构的第一个LED芯片10的反射线路层9都与位于绝缘层8一端的阳极接出端11连接,第一排及第二排LED芯片串联结构中的第四个LED芯片10的N型欧姆接触电极3都与位于绝缘层8另一端的阴极接出端12连接,形成第一排及第二排的LED芯片串联结构的并联;最后涂覆荧光粉,包覆封装。
所述绝缘层8是厚度为20μm的氧化铝层。所述反射线路层9是厚度为60-70μm的银层。所述金属键合线2为铜线。
实施例2:一种功率型电极上下设置的LED集成封装器件的封装方法,包括下列步骤:
a) 在铝块1上通过湿法氧化法或者电解氧化法制备一层绝缘层8;
b) 在形成之后的绝缘层8上通过真空蒸发法或者磁控溅射法制备互相隔离排列组合的反射线路层9;
c) 将上下设置电极的LED芯片10的P型欧姆接触电极5端固晶在各自的反射线路层9上;
d) 用金属键合线2将第一排的LED芯片10中的第一个LED芯片10的N型欧姆接触电极3与第二个LED芯片10的反射线路层9连接,用金属键合线2将第二个LED芯片10的N型欧姆接触电极3与第三个LED芯片10的反射线路层9连接,以此类推,用金属键合线2将第m个LED芯片10的N型欧姆接触电极3与第m+1个LED芯片10的反射线路层9连接,直至第一排的全部LED芯片10连接成第一排LED芯片串联结构;第二排的全部LED芯片10也同第一排的LED芯片10一样连接成第二排LED芯片串联结构,以此类推,第k排的全部LED芯片10也同第一排的LED芯片10一样连接成第k排LED芯片串联结构;第一排至第k排中各排的LED芯片串联结构的第一个LED芯片10的反射线路层9都与位于绝缘层8一端的阳极接出端11连接,第一排至第k排中各排的LED芯片串联结构的最后一个LED芯片10的N型欧姆接触电极3都与位于绝缘层8另一端的阴极接出端12连接,形成第一排至第k排中各排的LED芯片串联结构的并联;固晶在排列组合的反射线路层9上的上下设置电极的LED芯片10串联的个数按所需驱动电压确定,所述LED芯片串联结构并联的排数按所需电流确定;
e) 涂覆荧光粉,包覆封装。
Claims (7)
1.一种功率型电极上下设置的LED集成封装器件,包括上下设置电极的LED芯片(10),所述LED芯片(10)的N型欧姆接触电极(3)、N型外延层(4)、P型外延层(6)和P型欧姆接触电极(5)自上而下依次叠加,其特征在于:在铝块(1)上设有绝缘层(8),互相隔离的反射线路层(9)排列组合在绝缘层(8)上,所述上下设置电极的LED芯片(10)的P型欧姆接触电极(5)端固晶在各自的反射线路层(9)上;金属键合线(2)将第一排的LED芯片(10)中的第一个LED芯片(10)的N型欧姆接触电极(3)与第二个LED芯片(10)的反射线路层(9)连接,金属键合线(2)将第二个LED芯片(10)的N型欧姆接触电极(3)与第三个LED芯片(10)的反射线路层(9)连接,以此类推,金属键合线(2)将第m个LED芯片(10)的N型欧姆接触电极(3)与第m+1个LED芯片(10)的反射线路层(9)连接,直至第一排的全部LED芯片(10)连接成第一排LED芯片串联结构;第二排的全部LED芯片(10)也同第一排的LED芯片(10)一样连接成第二排LED芯片串联结构,以此类推,第k排的全部LED芯片(10)也同第一排的LED芯片(10)一样连接成第k排LED芯片串联结构;第一排至第k排中各排的LED芯片串联结构的第一个LED芯片(10)的反射线路层(9)都与位于绝缘层(8)一端的阳极接出端(11)连接,第一排至第k排中各排的LED芯片串联结构的最后一个LED芯片(10)的N型欧姆接触电极(3)都与位于绝缘层(8)另一端的阴极接出端(12)连接,形成第一排至第k排中各排的LED芯片串联结构的并联;最后涂覆荧光粉,包覆封装。
2.根据权利要求1所述一种功率型电极上下设置的LED集成封装器件,其特征在于:所述绝缘层(8)是厚度为1-30μm的氧化铝层。
3.根据权利要求2所述一种功率型电极上下设置的LED集成封装器件,其特征在于:所述绝缘层(8)的氧化铝层厚度为15-25μm。
4.根据权利要求1所述一种功率型电极上下设置的LED集成封装器件,其特征在于:所述反射线路层(9)是厚度为10-100μm的银层。
5.根据权利要求4所述一种功率型电极上下设置的LED集成封装器件,其特征在于:所述反射线路层(9)的银层厚度为50-80μm。
6.根据权利要求1所述一种功率型电极上下设置的LED集成封装器件,其特征在于:所述金属键合线(2)为金线、铝线或铜线。
7.一种权利要求1所述功率型电极上下设置的LED集成封装器件的封装方法,包括下列步骤:
a)在铝块(1)上通过湿法氧化法或者电解氧化法制备一层绝缘层(8);
b)在形成之后的绝缘层(8)上通过真空蒸发法或者磁控溅射法制备互相隔离排列组合的反射线路层(9);
c)将上下设置电极的LED芯片(10)的P型欧姆接触电极(5)端固晶在各自的反射线路层(9)上;
d)用金属键合线(2)将第一排的LED芯片(10)中的第一个LED芯片(10)的N型欧姆接触电极(3)与第二个LED芯片(10)的反射线路层(9)连接,用金属键合线(2)将第二个LED芯片(10)的N型欧姆接触电极(3)与第三个LED芯片(10)的反射线路层(9)连接,以此类推,第k排的全部LED芯片(10)也同第一排的LED芯片(10)一样连接成第k排LED芯片串联结构;第一排至第k排中各排的LED芯片串联结构的第一个LED芯片(10)的反射线路层(9)都与位于绝缘层(8)一端的阳极接出端(11)连接,第一排至第k排中各排的LED芯片串联结构的最后一个LED芯片(10)的N型欧姆接触电极(3)都与位于绝缘层(8)另一端的阴极接出端(12)连接,形成第一排至第k排中各排的LED芯片串联结构的并联;固晶在排列组合的反射线路层(9)上的上下设置电极的LED芯片(10)串联的个数按所需驱动电压确定,所述LED芯片串联结构并联的排数按所需电流确定;
e)涂覆荧光粉,包覆封装。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2011101185158A CN102194808B (zh) | 2011-05-10 | 2011-05-10 | 功率型电极上下设置的led集成封装器件及其封装方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2011101185158A CN102194808B (zh) | 2011-05-10 | 2011-05-10 | 功率型电极上下设置的led集成封装器件及其封装方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102194808A CN102194808A (zh) | 2011-09-21 |
CN102194808B true CN102194808B (zh) | 2013-04-10 |
Family
ID=44602608
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2011101185158A Expired - Fee Related CN102194808B (zh) | 2011-05-10 | 2011-05-10 | 功率型电极上下设置的led集成封装器件及其封装方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN102194808B (zh) |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7535028B2 (en) * | 2005-02-03 | 2009-05-19 | Ac Led Lighting, L.Lc. | Micro-LED based high voltage AC/DC indicator lamp |
CN100555684C (zh) * | 2006-08-02 | 2009-10-28 | 中国科学院半导体研究所 | 一种照明用氮化镓基发光二极管器件 |
CN201681925U (zh) * | 2009-12-28 | 2010-12-22 | 深圳市成光兴实业发展有限公司 | 一种高效率阵列式led封装结构 |
CN201795340U (zh) * | 2010-08-26 | 2011-04-13 | 杭州创元光电科技有限公司 | 用显示类芯片制作的led芯片光源模块 |
CN202013885U (zh) * | 2011-05-10 | 2011-10-19 | 江西科技师范学院 | 电极上下设置的led集成封装器件 |
-
2011
- 2011-05-10 CN CN2011101185158A patent/CN102194808B/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN102194808A (zh) | 2011-09-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN201412704Y (zh) | 一种集成led芯片的光源 | |
CN102683534A (zh) | 垂直式交流发光二极管器件及其制作方法 | |
CN101308838B (zh) | 一种高导通电压倒装led集成芯片及制造方法 | |
CN101614333A (zh) | 高效散热led照明光源及制造方法 | |
CN102231378B (zh) | 一种led封装结构及其制备方法 | |
US20120043576A1 (en) | Led package structure | |
CN103066195A (zh) | 应用石墨烯作为导热层的倒装结构发光二极管 | |
TW201017925A (en) | Vertical AC LED | |
CN106299072A (zh) | 发光二极管芯片 | |
KR20120042699A (ko) | 수직형 발광 다이오드 셀 어레이 및 그의 제조 방법 | |
CN101859865B (zh) | 一种大功率白光led器件的无金线封装方法及白光led器件 | |
CN109791964A (zh) | 一种发光二极管芯片及其制作方法 | |
CN109891610A (zh) | 一种发光二极管元件及其制作方法 | |
CN202013885U (zh) | 电极上下设置的led集成封装器件 | |
CN102214746B (zh) | 一种氮化镓基功率型led芯片制作方法 | |
CN102194808B (zh) | 功率型电极上下设置的led集成封装器件及其封装方法 | |
CN102226995B (zh) | 一种led封装结构及其制备方法 | |
TW201205882A (en) | Manufacturing method for LED light emitting device | |
CN106206902B (zh) | 发光二极管芯片 | |
CN201412705Y (zh) | 高效散热led照明光源 | |
CN105023932B (zh) | 一种结合led外延结构与led封装基板为一体的垂直式led阵列元件 | |
CN101330080B (zh) | 一种高导通电压正装led集成芯片及制造方法 | |
CN206992110U (zh) | 一种双面发光led芯片 | |
CN106299073A (zh) | 发光二极管晶圆及其形成方法 | |
CN207116432U (zh) | 一种csp封装的高压led芯片结构 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C17 | Cessation of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130410 Termination date: 20140510 |