CN102194703A - Circuit substrate and manufacturing method thereof - Google Patents
Circuit substrate and manufacturing method thereof Download PDFInfo
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- CN102194703A CN102194703A CN2010106062075A CN201010606207A CN102194703A CN 102194703 A CN102194703 A CN 102194703A CN 2010106062075 A CN2010106062075 A CN 2010106062075A CN 201010606207 A CN201010606207 A CN 201010606207A CN 102194703 A CN102194703 A CN 102194703A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 67
- 239000000758 substrate Substances 0.000 title abstract description 26
- 239000002184 metal Substances 0.000 claims abstract description 174
- 229910052751 metal Inorganic materials 0.000 claims abstract description 174
- 238000000059 patterning Methods 0.000 claims abstract description 157
- 238000000034 method Methods 0.000 claims abstract description 92
- 238000003825 pressing Methods 0.000 claims abstract description 51
- 239000010410 layer Substances 0.000 claims description 685
- 230000004888 barrier function Effects 0.000 claims description 224
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 185
- 239000011889 copper foil Substances 0.000 claims description 156
- 229920002120 photoresistant polymer Polymers 0.000 claims description 87
- 238000007747 plating Methods 0.000 claims description 70
- 239000004020 conductor Substances 0.000 claims description 58
- 239000011241 protective layer Substances 0.000 claims description 36
- 238000003466 welding Methods 0.000 claims description 29
- 239000000853 adhesive Substances 0.000 claims description 27
- 230000001070 adhesive effect Effects 0.000 claims description 27
- 239000000463 material Substances 0.000 claims description 7
- 239000004925 Acrylic resin Substances 0.000 claims description 5
- 229920000178 Acrylic resin Polymers 0.000 claims description 5
- 229920001651 Cyanoacrylate Polymers 0.000 claims description 5
- MWCLLHOVUTZFKS-UHFFFAOYSA-N Methyl cyanoacrylate Chemical compound COC(=O)C(=C)C#N MWCLLHOVUTZFKS-UHFFFAOYSA-N 0.000 claims description 5
- 238000000926 separation method Methods 0.000 claims description 5
- 238000000227 grinding Methods 0.000 claims description 4
- 238000009713 electroplating Methods 0.000 abstract description 8
- 238000007789 sealing Methods 0.000 abstract description 3
- 230000000149 penetrating effect Effects 0.000 abstract 1
- 229910052802 copper Inorganic materials 0.000 description 29
- 239000010949 copper Substances 0.000 description 29
- 239000000126 substance Substances 0.000 description 17
- 238000005516 engineering process Methods 0.000 description 16
- 239000000084 colloidal system Substances 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 8
- 239000003814 drug Substances 0.000 description 6
- 150000002739 metals Chemical class 0.000 description 6
- 238000004806 packaging method and process Methods 0.000 description 5
- 238000005553 drilling Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 238000004080 punching Methods 0.000 description 4
- 239000012792 core layer Substances 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 238000007731 hot pressing Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000010422 painting Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 238000013515 script Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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Abstract
A circuit substrate and a manufacturing method thereof are provided, the method comprises the following steps: bonding the peripheries of the two metal layers to form a sealing area; forming at least one through hole penetrating the sealing area; forming two insulating layers on the two metal layers and two conducting layers on the two insulating layers; pressing two insulating layers and two conducting layers onto the two metal layers, wherein the two metal layers are embedded in the two insulating layers and the two insulating layers are filled in the through hole; separating the bonding areas of the two metal layers to form two separated circuit substrates. Thus, a thinner substrate can be fabricated in subsequent patterning processes, electroplating processes, and the like. In addition, the method can be used for manufacturing the circuit substrate with odd layers or even layers.
Description
Technical field
The present invention relates to a kind of circuit base plate and preparation method thereof, and particularly relate to a kind of coreless (coreless) circuit base plate and preparation method thereof.
Background technology
In semiconductor technology, chip packaging carrying plate is one of potted element that often uses at present.Chip packaging carrying plate for example is a multilayer circuit board, its mainly be by multilayer line layer and multilayer dielectric layer be superimposed the institute constitute, wherein dielectric layer is disposed between the two adjacent line layers, and line layer can be by running through dielectric layer via (Plating Through Hole, PTH) or conductive hole (via) and being electrically connected to each other.Because chip packaging carrying plate has advantages such as wiring is fine and closely woven, assembling is compact and functional, become the main flow of chip-packaging structure (chip package structure).
Generally speaking, the line construction of multilayer circuit board adopts lamination (build up) mode or pressing (laminated) mode to make mostly, therefore has elevated track density and the characteristic of dwindling line pitch.Ultra-thin substrate is because the rigidity deficiency, therefore must provide earlier to have certain thickness substrate and be used as prop carrier.Then, be coated with a large amount of colloids in regular turn and form the multilayer line layer and replace the multilayer dielectric layer of arrangement on the relative both side surface of substrate with line layer.At last, remove colloid, line layer, dielectric layer on the colloid are separated with substrate, and form two multilayer circuit boards that are separated from each other.In addition, if desire forms via or conductive hole, then can after forming one dielectric layer, form blind hole earlier, to expose the line layer of this dielectric layer below.Afterwards, again by the mode copper electroplating layer electroplated in blind hole therewith on the dielectric layer, and form another line layer and via or conductive hole.
Because known must providing has the prop carrier that certain thickness substrate is used as copper foil layer, and if substrate adopts metal material, the material cost of itself also can be higher, so the required manufacturing cost of multilayer circuit board also can improve.In addition, must use a large amount of colloids to fix between copper foil layer and the substrate, the step that therefore removes colloid is comparatively difficult, and its technology yield also can't promote.Therefore in addition, by the formed line layer of plating mode, the thick uniformity of its copper is not good, and when the thinner thickness of required line layer, then need reduce the thickness of line layer via thinning technology (for example etch process).Thus, not only can increase the making step of multilayer circuit board, also can reduce the technology yield of multilayer circuit board.
Summary of the invention
The invention provides a kind of circuit base plate and preparation method thereof, it can reduce processing step, reduce production costs, and can improve the technology yield, and then increases the reliability of product.
The present invention proposes a kind of manufacture method of circuit base plate, comprises the following steps: to engage the periphery of two metal levels, to form the driving fit district.Form and at least always wear the perforation in driving fit district.Form two insulating barriers on two metal levels, and form two conductive layers on two insulating barriers.On pressing two insulating barriers and two conductive layer to two metal levels, be embedded in two insulating barriers in two metal levels that wherein engage, and two insulating barriers fill in the perforation.The driving fit district that separates two metal levels is to form two circuit base plates of each self-separation.
In an embodiment of the present invention, the method for the periphery of above-mentioned joint two metal levels comprises electric welding, spot welding or passes through adhesive that wherein the material of adhesive comprises cyanoacrylate or acrylic resin.
In an embodiment of the present invention, the manufacture method of above-mentioned circuit base plate also comprises: after on pressing two insulating barriers and two conductive layer to two metal levels, remove part two insulating barriers and part two conductive layers, to form a plurality of blind holes that manifest two metal levels.Form electric conducting material in blind hole and on two conductive layers that are not removed.After the driving fit district that separates two metal levels, patterning conductive material, metal level and conductive layer.
In an embodiment of the present invention, the manufacture method of above-mentioned circuit base plate also comprises: after on pressing two insulating barriers and two conductive layer to two metal levels, remove part two insulating barriers and part two conductive layers, to form a plurality of blind holes that manifest two metal levels.Thinning two conductive layers.Form on two conductive layers of two plating seed layers after thinning with blind hole in.After the driving fit district that separates two metal levels, expose metal level.Form patterning photoresist layer respectively on the plating seed layer and on the metal level that is exposed out.With patterning photoresist layer is mask, and plating seed layer is electroplated.Remove patterning photoresist layer and plating seed layer and be patterned the part that the photoresist layer covers.
In an embodiment of the present invention, the manufacture method of above-mentioned circuit base plate also comprises: after on pressing two insulating barriers and two conductive layer to two metal levels, patterning two conductive layers are to form two patterned conductive layers.Form in addition two insulating barriers on two patterned conductive layers, and form in addition two conductive layers on other two insulating barriers.Pressing insulating barrier and other two conductive layers, and be embedded in the insulating barrier in two patterned conductive layers.After the driving fit district that separates two metal levels, remove partial insulative layer, part metals layer and another conductive layer of part, to form a plurality of blind holes that manifest patterned conductive layer.Form electric conducting material in blind hole and on the metal level and another conductive layer that are not removed.Patterning conductive material, metal level and another conductive layer.
In an embodiment of the present invention, the manufacture method of above-mentioned circuit base plate also comprises: after on pressing two insulating barriers and two conductive layer to two metal levels, patterning two conductive layers are to form two patterned conductive layers.Form in addition two insulating barriers on two patterned conductive layers, and form in addition two conductive layers on other two insulating barriers.Pressing insulating barrier and other two conductive layers, and be embedded in the insulating barrier in two patterned conductive layers.After the driving fit district that separates two metal levels, remove partial insulative layer, part metals layer and another conductive layer of part, to form a plurality of blind holes that manifest patterned conductive layer.Remove another conductive layer and metal level, to expose insulating barrier.Form two plating seed layers on insulating barrier with blind hole in.Form two patterning photoresist layers on two plating seed layers.With patterning photoresist layer is mask, and plating seed layer is electroplated.Remove patterning photoresist layer and plating seed layer and be patterned the part that the photoresist layer covers.
In an embodiment of the present invention, the manufacture method of above-mentioned circuit base plate, also comprise: after on pressing two insulating barriers and two conductive layer to two metal levels, remove part two insulating barriers and part two conductive layers, to form a plurality of first blind holes that manifest two metal levels.Remove two conductive layers to expose two insulating barriers.Form two plating seed layers on two insulating barriers with first blind hole in.Form two patterning photoresist layers on plating seed layer.With patterning photoresist layer is mask, and plating seed layer is electroplated.Remove patterning photoresist layer and plating seed layer and be patterned the part that the photoresist layer covers, on two insulating barriers, to form two patterned conductive layers and a plurality of conductivity through-hole structure.Form in addition two insulating barriers on two patterned conductive layers, and form in addition two conductive layers on other two insulating barriers.Pressing insulating barrier and other two conductive layers, and be embedded in the insulating barrier in two patterned conductive layers.After the driving fit district that separates two metal levels, remove partial insulative layer, metal level and another conductive layer, to form a plurality of second blind holes that manifest patterned conductive layer.Form two plating seed layers in addition on other two insulating barriers, in the end and second blind hole of first blind hole.Form in addition two patterning photoresist layers on other two plating seed layers.With other two patterning photoresist layers is mask, and other two plating seed layers are electroplated.Remove two patterning photoresist layers in addition and the part that covered by other two patterning photoresist layers of two plating seed layers in addition.
In an embodiment of the present invention, two above-mentioned metal levels comprise first copper foil layer and second copper foil layer respectively, and the thickness of each second copper foil layer is in fact greater than the thickness of each first copper foil layer, and second copper foil layer engages each other.
In an embodiment of the present invention, the manufacture method of above-mentioned circuit base plate also comprises: after on pressing two insulating barriers and two conductive layer to two metal levels, patterning two conductive layers are to form first patterned conductive layer and second patterned conductive layer.Form a plurality of first perforations that extend to second patterned conductive layer from first patterned conductive layer.After the driving fit district that separates two metal levels, remove second copper foil layer.Form first insulating barrier on first patterned conductive layer, and form first conductive layer on first insulating barrier.Pressing first insulating barrier and first conductive layer, and be embedded in first patterned conductive layer in the insulating barrier and first insulating barrier.Remove partial insulative layer, first insulating barrier, part first copper foil layer and part first conductive layer, to form a plurality of first blind holes that manifest first patterned conductive layer.Form respectively plating seed layer on first copper foil layer that does not remove with first blind hole in and on first conductive layer that does not remove with first blind hole in.Form two patterning photoresist layers on plating seed layer.With patterning photoresist layer is mask, plating seed layer is electroplated, to form a plurality of conductive blind hole structures in first blind hole.Remove patterning photoresist layer and plating seed layer and be patterned the part that the photoresist layer covers.
In an embodiment of the present invention, above-mentioned formation first insulating barrier and forms first conductive layer in being on first insulating barrier after separating the driving fit district of two metal levels on first patterned conductive layer.
In an embodiment of the present invention, above-mentioned formation first insulating barrier and forms first conductive layer in being on first insulating barrier before separating the driving fit district of two metal levels on first patterned conductive layer.
In an embodiment of the present invention, the manufacture method of above-mentioned circuit base plate, also comprise: form first insulating barrier on first patterned conductive layer, and form first conductive layer on first insulating barrier time, form on second insulating barrier and second patterned conductive layer, and form second conductive layer on second insulating barrier.
In an embodiment of the present invention; the manufacture method of above-mentioned circuit base plate; also comprise: remove patterning photoresist layer and plating seed layer and be patterned after the part that the photoresist layer covers; form first protective layer on first insulating barrier; and form second protective layer on insulating barrier, wherein first protective layer and second protective layer cover conductive blind hole structures.Carry out grinding technics, to remove part first protective layer and part second protective layer to exposing conductive blind hole structures.Remove first protective layer and second protective layer left over.
In an embodiment of the present invention, the manufacture method of above-mentioned circuit base plate, comprise that also removing patterning photoresist layer and plating seed layer is patterned after the part that the photoresist layer covers, form first welding resisting layer on first insulating barrier, and form second welding resisting layer on insulating barrier, wherein first welding resisting layer has a plurality of first openings, and second welding resisting layer has a plurality of second openings, and first opening and second opening expose the partially conductive blind hole structure.
The present invention proposes a kind of circuit base plate, and it comprises the metal level of patterning, conductive layer, insulating barrier and the electric conducting material of patterning.Insulating barrier is between the conductive layer of the metal level of patterning and patterning.Electric conducting material is arranged in a plurality of blind holes, and wherein blind hole runs through insulating barrier, and electric conducting material is electrically connected at the metal level of patterning and the conductive layer of patterning.
The present invention proposes a kind of circuit base plate, and it comprises the metal level of patterning, conductive layer, patterned conductive layer, two insulating barriers and the electric conducting material of patterning.Patterned conductive layer is between the conductive layer of the metal level of patterning and patterning.Insulating barrier lays respectively between the metal level of patterning and the patterned conductive layer and between the conductive layer and patterned conductive layer of patterning.Electric conducting material is arranged in a plurality of blind holes, and wherein blind hole runs through insulating barrier, and electric conducting material is electrically connected between the metal level of patterning and the patterned conductive layer and between the conductive layer and patterned conductive layer of patterning.
Based on above-mentioned, the present invention will engage around two metal levels earlier, to form seal area.Wait to finish after the pressing step of two-sided insulating barrier and two-sided conductive layer, again two metal levels are separated.Therefore, compared to known technology, the manufacture method of circuit base plate of the present invention need not to adopt metal substrate to be used as supports loadboard, meaning is a kind of coreless (coreless) circuit substrate structure, can effectively reduce the cost of manufacture of circuit base plate, and can improve the reliability of circuit base plate and effectively reduce the time-histories of making circuit base plate.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and conjunction with figs. is described in detail below.
Description of drawings
Figure 1A to Fig. 1 H is the generalized section of manufacture method of the circuit base plate of embodiments of the invention.
Figure 1A to Fig. 1 E and 1F ' are the generalized section of manufacture method of the circuit base plate of another embodiment of the present invention to Fig. 1 J '.
Fig. 2 A to Fig. 2 I is the generalized section of manufacture method of circuit base plate of another embodiment of embodiments of the invention.
Fig. 2 A to Fig. 2 G and Fig. 2 H ' are the generalized section of manufacture method of the circuit base plate of another embodiment of the present invention to Fig. 2 K '.
Fig. 2 A to Fig. 2 C and Fig. 2 D " to Fig. 2 M " are the generalized section of manufacture method of the circuit base plate of another embodiment of the present invention.
Fig. 3 A to Fig. 3 P is the generalized section of manufacture method of circuit base plate of another embodiment of embodiments of the invention.
Fig. 4 A to Fig. 4 B is the generalized section of manufacture method of circuit base plate of another embodiment of embodiments of the invention.
Description of reference numerals
100a, 100a ', 100b: circuit base plate 102: metal level
104: driving fit district 112: insulating barrier
112a: upper surface 112b: lower surface
122,122 ': conductive layer 124,124 ': electric conducting material
124a: the first patterning conductive material 124b: second patterning conductive material
124c: conductive blind hole structures 132: plating seed layer
134: patterning photoresist layer
200a, 200a ', 200b, 200c, 200c ': circuit base plate
202: metal level 204: the driving fit district
232,212,234: insulating barrier 212b: lower surface
222: conductive layer 222a: patterned conductive layer
232a: upper surface 242,248: conductive layer
244,244 ': electric conducting material 244a: the first patterning conductive material layer
244b: the second patterning conductive material layer 244c: conductive blind hole structures
246: electric conducting material 246a: the patterning conductive material layer
246b: conductive blind hole structures 249: electric conducting material
249a: patterning conductive material layer 249b: conductive blind hole structures
252,256: plating seed layer 254,258: patterning photoresist layer
300: circuit base plate 310 ', 310 ": metal level
310a: the first copper foil layer 310b: second copper foil layer
310c: the 3rd copper foil layer 310d: the 4th copper foil layer
310e: the 5th copper foil layer 310f: the 6th copper foil layer
320: 332: the first perforations of adhesive
342: the first conductive layers of 334: the second perforations
342a: 344: the second conductive layers of first line layer
344a: the second line layer 350a: first insulating barrier
350b: the second insulating barrier 350c: the 3rd insulating barrier
350d: the 4th insulating barrier 360a: first circuit base plate
360b: the second circuit base plate 400a: first circuit base plate
400c: tertiary circuit substrate 400d: the 4th circuit base plate
412: the first blind hole 412a: first conductive blind hole structures
414: the second blind hole 414a: second conductive blind hole structures
420: the chemical copper layer
432: the first patterning dry film photoresist layers
434: the second patterning dry film photoresist layers
440: 452: the first protective layers of copper electroplating layer
462: the first welding resisting layers of 454: the second protective layers
462a: 464: the second welding resisting layers of first opening
464a: second opening
H: perforation V: blind hole
V1: the first blind hole V2: second blind hole
Embodiment
Figure 1A to Fig. 1 H is the generalized section of manufacture method of the circuit base plate of embodiments of the invention.Please earlier simultaneously with reference to Figure 1A and Figure 1B, about the manufacture method of the circuit base plate of present embodiment, at first, two metal levels 102 are provided, wherein these metal levels 102 for example are Copper Foil or other tinsels, and engage the periphery of these metal levels 102, to form driving fit district 104.In the present embodiment, the method that engages the periphery of these metal levels 102 comprises electric welding or spot welding, and these metal levels 102 temporarily are bonded together, and employed medicament infiltrates between these metal levels 102 in the subsequent technique to avoid.Certainly, except using electric welding or spot welding, also can use adhesive, its material comprises cyanoacrylate or acrylic resin, or other colloid, and the periphery of these metal levels 102 temporarily is bonded together.What deserves to be mentioned is that these metal levels 102 described herein can be considered coreless (coreless) structure sheaf.
In addition, refer again to Figure 1B, in the present embodiment, engage after the periphery of these metal levels 102, also can form the perforation H (only schematically illustrating two among Figure 1B) that at least always wears the driving fit district.The method that forms these perforations H comprises laser punching or machine drilling, because the aperture of these perforations H is less than driving fit district 104, so the sealing in driving fit district 104 can not destroyed by these perforations H.
Then, please also refer to Fig. 1 C and Fig. 1 D, form two insulating barriers 112 on these metal levels 102, form two conductive layers 122 on these insulating barriers 112, and these insulating barriers 112 of pressing and these conductive layers 122, and be embedded between these insulating barriers 112 in these metal levels 102 that engage.Simultaneously, these insulating barriers 112 also can fill among these perforations H in driving fit district 104 when pressing.Because the size of these insulating barriers 112 is greater than the size of these metal levels 102, so these metal levels 102 can fully be coated in these insulating barriers 112, can not polluted by the impurity in the external world or medicament.
Then, please refer to Fig. 1 E, remove these insulating barriers 112 of part and these conductive layers 122 of part, to form a plurality of blind hole V that manifest these metal levels 102.In the present embodiment, the method that forms these blind holes V comprises laser punching, and the method for these conductive layers 122 comprises laser-induced thermal etching or photoetching etching etc. and remove partly.
Then, please refer to Fig. 1 F, form electric conducting material 124 in these blind holes V and on these conductive layers 122 that are not removed.Wherein, the method that forms electric conducting material 124 comprises plating, and electric conducting material 124 for example is copper or other metals.In this mandatory declaration be, because these metal levels 102 can fully be coated in these insulating barriers 112, and can not polluted by the impurity in the external world or medicament, therefore form when seeing through electroplating technology electric conducting material 124 in these blind holes V with these conductive layers 122 that are not removed on the time, be embedded in the size and the thickness of these metal levels 102 scripts in these insulating barriers 112 in can not having influence on.
Then, please also refer to Fig. 1 F and Fig. 1 G, separate the driving fit district 104 of these metal levels 102, to form two circuit base plate 100a ' of each self-separation.Present embodiment can utilize make-up machine or other instruments, is datum mark with these perforations H, driving fit district 104 is coated these metal level 102 zones remove, and these metal levels 102 are fully separated.Certainly, separating these metal levels 102 does not limit in the above described manner and carries out.
Afterwards, please refer to Fig. 1 H, patterning conductive material 124, these metal levels 102 and these conductive layers 122 forming required circuit on circuit base plate 100a ' separately, and form two circuit base plate 100a.In brief, each circuit base plate 100a of present embodiment comprises the metal level 102 of patterning, conductive layer 122, insulating barrier 112 and the electric conducting material 124 of patterning, and wherein insulating barrier 112 is between the conductive layer 122 of the metal level 102 of patterning and patterning.Electric conducting material 124 is arranged in a plurality of blind hole V, and wherein these blind holes V runs through insulating barrier 112, and electric conducting material 124 is electrically connected at the metal level 102 of patterning and the conductive layer 122 of patterning.So far, finished the making of the circuit base plate 100a of coreless.
In this mandatory declaration is that following embodiment continues to use the element numbers and the partial content of previous embodiment, wherein adopts identical label to represent identical or approximate element, and has omitted the explanation of constructed content.Explanation about clipped can be with reference to previous embodiment, and following embodiment no longer repeats to give unnecessary details.
Figure 1A to Fig. 1 E and 1F ' are the generalized section of manufacture method of the circuit base plate of another embodiment of the present invention to Fig. 1 J '.The manufacture method of the circuit base plate 100b of present embodiment is similar to the manufacture method of existing base board 100a, its difference is: after the step of Fig. 1 E, meaning promptly removes these insulating barriers 112 of part and these conductive layers 122 of part, to form a plurality of blind hole V and these conductive layers 122 that manifest these metal levels 102.Afterwards, please also refer to Fig. 1 E and Fig. 1 F ', these conductive layers 122 of thinning are to form a plurality of conductive layers 122 ', and form two plating seed layers 132 on these conductive layers 122 ' and in these blind holes V, wherein these plating seed layers 132 cover inwall and these metal levels 102 of part of these conductive layers 122 ' and these blind holes V fully.Then, please refer to Fig. 1 G ', the driving fit district 104 that separates these metal levels 102 is to expose metal level 102.Then, please refer to Fig. 1 H ', form patterning photoresist layer 134 respectively on the plating seed layer 132 and on the metal level 102 that is exposed out.Afterwards, please refer to Fig. 1 I ', is mask with these patterning photoresist layers 134, plating seed layer 132 and metal level 102 is electroplated, to form electric conducting material 124 '.At last, please refer to Fig. 1 J ', remove these patterning photoresist layers 134, part and metal level 102 that plating seed layer 132 is patterned 134 covering of photoresist layer are patterned the part that photoresist layer 134 covers, with part upper surface 112a and the part lower surface 112b that exposes insulating barrier 112, and form the first patterning conductive material layer 124a, the second patterning conductive material layer 124b and conductive blind hole structures 124c, wherein conductive blind hole structures 124c electrically connects the first patterning conductive material layer 124a and the second patterning conductive material layer 124b.So far, finished the making of circuit base plate 100b.
The foregoing description is to form two-layer circuit base plate 100a, 100b, but in another embodiment, can be with two-layer circuit base plate 100a, 100b as core layer, and finish four layers, the circuit base plate more than six layers or six layers in regular turn, its practice is general circuit substrate process, does not repeat them here.In addition, in order to make the circuit of odd-level, the present invention proposes a kind of manufacture method of circuit base plate in addition.
Fig. 2 A to Fig. 2 I is the generalized section of manufacture method of circuit base plate of another embodiment of embodiments of the invention.Please earlier simultaneously with reference to figure 2A and Fig. 2 B, the manufacture method about the circuit base plate of present embodiment at first, provides two metal levels 202, for example is Copper Foil or other tinsels, and engages the periphery of these metal levels 202, with formation driving fit district 204.Wherein, the method that engages the periphery of these metal levels 202 comprises electric welding or spot welding, and these metal levels 202 temporarily are bonded together, and employed medicament infiltrates between these metal levels 202 in the subsequent technique to avoid.Certainly, except using electric welding or spot welding, also can use adhesive, its material comprises cyanoacrylate or acrylic resin, or other colloid, and the periphery of these metal levels 202 temporarily is bonded together.What deserves to be mentioned is that these metal levels 202 described herein can be considered coreless (coreless) structure sheaf.
Refer again to Fig. 2 B, in the present embodiment, engage after the periphery of these metal levels 202, also can form the perforation H (only schematically illustrating two among Fig. 2 B) that at least always wears driving fit district 204.Wherein, the method that forms these perforations H comprises laser punching or machine drilling.
Then, please refer to Fig. 2 C to Fig. 2 E, form two insulating barriers 212 on these metal levels 202, form two conductive layers 222 on these insulating barriers 212.Can be still under closed state at these metal levels 202, these conductive layers 222 of patterning simultaneously are to form two patterned conductive layer 222a.Then, form in addition two insulating barriers 232 on these patterned conductive layers 222a, and form in addition two conductive layers 242 on these insulating barriers 232.In Fig. 2 C, these insulating barriers 212 of pressing and these conductive layers 222, and be embedded in these insulating barriers 212 in these metal levels 202 that engage.In addition, in Fig. 2 E, these insulating barriers 232,212 of pressing and these conductive layers 242, and be embedded in these patterned conductive layers 222a in these insulating barriers 232,212.Simultaneously, these insulating barriers 212 also can fill among these perforations H in driving fit district 204 when pressing.Because the size of these insulating barriers 212 is greater than the size of these metal levels 202, so these metal levels 202 can fully be coated in these insulating barriers 212, can not polluted by the impurity in the external world or medicament.
Then, please refer to Fig. 2 F, separate the driving fit district 204 of these metal levels 202, to form two circuit base plate 200a ' of each self-separation.In this, these circuit base plates 200a ' has three layer line roads respectively.Present embodiment can utilize make-up machine or other instruments, is datum mark with these perforations H (please refer to Fig. 2 E), driving fit district 204 is coated these metal level 202 zones remove, and these metal levels 202 are fully separated.Certainly, separating these metal levels 202 does not limit in above-mentioned mode and carries out.
Then, please refer to Fig. 2 G, only illustrate one of them circuit base plate 200a '.Remove these insulating barriers 212,232 of part, part metals layer 202 and partially conductive layer 242, to form a plurality of blind hole V that manifest patterned conductive layer 222a.Wherein, the method that forms these blind holes V comprises laser punching.Afterwards, please refer to Fig. 2 H, form electric conducting material 244 in these blind holes V and on the metal level 202 and conductive layer 242 that are not removed.Wherein, the method that forms electric conducting material 244 comprises plating, and electric conducting material 244 for example is copper or other metals.At last, please refer to Fig. 2 I, patterning conductive material 244, metal level 202 and conductive layer 242 forming required circuit on circuit base plate 200a ' separately, and are finished the making of circuit base plate 200a.
In brief, the circuit base plate 200a ' shown in Fig. 2 I with three layer line roads, it comprises metal level 202, the conductive layer 242 of patterning, patterned conductive layer 222a, two insulating barrier 212,232 and the electric conducting materials 244 of patterning.Patterned conductive layer 222a is between the conductive layer 242 of the metal level 202 of patterning and patterning.These insulating barriers 212,232 lay respectively between the metal level 202 of patterning and the patterned conductive layer 222a and between the conductive layer 242 and patterned conductive layer 222a of patterning.Electric conducting material 244 is arranged in a plurality of blind hole V, these blind holes V runs through these insulating barriers 212,232, and electric conducting material 244 is electrically connected between the metal level 202 of patterning and the patterned conductive layer 222a and between the conductive layer 242 and patterned conductive layer 222a of patterning.
Fig. 2 A to Fig. 2 G and Fig. 2 H ' are the generalized section of manufacture method of the circuit base plate of another embodiment of the present invention to Fig. 2 K '.The manufacture method of the circuit base plate 200b of present embodiment is similar to the manufacture method of existing base board 200a, its difference is: after the step of Fig. 2 G, meaning promptly removes these insulating barriers 212,232 of part, part metals layer 202 and partially conductive layer 242, manifest with formation after these blind holes V of patterned conductive layer 222a, please refer to Fig. 2 H ', remove conductive layer 242 and metal level 202, exposing insulating barrier 232,212, and form two plating seed layers 252 on these insulating barriers 212,232 with these blind holes V in.Then, please refer to Fig. 2 I ', form two patterning photoresist layers 254 on these plating seed layers 252.Afterwards, please refer to Fig. 2 J ', is mask with these patterning photoresist layers 254, these plating seed layers 252 is electroplated, to form electric conducting material 244 '.At last, please refer to Fig. 2 K ', remove the part that these patterning photoresist layers 254 and these plating seed layers 252 are covered by these patterning photoresist layers 254, with the part upper surface 232a that exposes insulating barrier 232 and the part lower surface 212b of insulating barrier 212, and form the first patterning conductive material layer 244a, the second patterning conductive material layer 244b and a plurality of conductive blind hole structures 244c, wherein these conductive blind hole structures 224c electrically connects the first patterning conductive material layer 244a and patterned conductive layer 222a and the patterned conductive layer 222a and the second patterning conductive material layer 244b.So far, finished the making of circuit base plate 200b.
Fig. 2 A to Fig. 2 C and Fig. 2 D " to Fig. 2 M " are the generalized section of manufacture method of the circuit base plate of another embodiment of the present invention.The manufacture method of the circuit base plate 200c of present embodiment is similar to the manufacture method of existing base board 200a, its difference is: after the step of Fig. 2 C, meaning be these insulating barriers 212 of pressing and these conductive layers 222 to these metal levels 202 after, please refer to Fig. 2 D "; remove these insulating barriers 212 of part and these conductive layers 222 of part, to form a plurality of first blind hole V1 that manifest these metal levels 202.Then, please refer to Fig. 2 E ", remove these conductive layers 222 exposing these insulating barriers 212, and form two plating seed layers 252 on these insulating barriers 212 with these first blind holes V1 in.Then, please refer to Fig. 2 F ", form two patterning photoresist layers 254 on these plating seed layers 252.Then, please refer to Fig. 2 G ", be mask with these patterning photoresist layers 254, these plating seed layers 252 are electroplated, to form electric conducting material 246.Then, please refer to Fig. 2 H "; remove the part that these patterning photoresist layers 254 and these plating seed layers 252 are covered by these patterning photoresist layers 254, on these insulating barriers 252, to form two patterning conductive material layer 246a and a plurality of conductivity through-hole structure 246b.
Then, please refer to Fig. 2 I ", form in addition two insulating barriers 234 on these patterned conductive layers 246a, and form in addition two conductive layers 248 on these insulating barriers 234.Then, these insulating barriers 234 of pressing and these conductive layers 248, and be embedded in these patterned conductive layers 246a in these insulating barriers 212,234.Then, please refer to Fig. 2 J ", separate the driving fit district 204 of these metal levels 202, to form two circuit base plate 200c ' of each self-separation.Be Fig. 2 J in this mandatory declaration " in only illustrate one of them circuit base plate 200c '.Then, refer again to Fig. 2 J ", remove partial insulative layer 234, metal level 202 and conductive layer 248, to form a plurality of second blind hole V2 that manifest patterned conductive layer 246a.Then, please refer to Fig. 2 K ", form two plating seed layers 256 in addition on these insulating barriers 212,234, in the end and the second blind hole V2 of the first blind hole V1.Then, please refer to Fig. 2 L ", form in addition two patterning photoresist layers 258 on these plating seed layers 256, and be mask with these patterning photoresist layers 258, these plating seed layers 256 are electroplated, to form electric conducting material 249.At last, please refer to Fig. 2 M "; remove the part that these patterning photoresist layers 258 and these plating seed layers 256 are covered by these patterning photoresist layers 258, on these insulating barriers 212,234, to form two patterning conductive material layer 249a and a plurality of conductivity through-hole structure 249b.In this, these conductivity through-hole structures 246b, 249b electrically connect patterned conductive layer 246a and these patterning conductive material layers 249a.So far, to finish the making of the circuit base plate 200c with three layer line roads.
What deserves to be mentioned is, the foregoing description is circuit base plate 200a, 200b, the 200c that forms three layer line roads, but in the embodiment that other do not illustrate, can be with circuit base plate 200a, the 200b on three layer line roads, 200c as core layer, and finish five layers, the circuit base plate more than seven layers or seven layers in regular turn, its practice is general circuit substrate process, those skilled in the art works as can be with reference to the explanation of previous embodiment, according to actual demand, and select aforementioned components for use, to reach required technique effect, so do not repeat them here.
By above-mentioned explanation as can be known, no matter be that odd-level circuit or even level circuit all can use the manufacture method of above-mentioned circuit base plate 100a, 100b, 200a, 200b, 200c to finish, not only can in identical Production Time, finish two circuit base plate 100a, 100b, 200a, 200b, 200c, to accelerate the making time-histories of multilayer circuit board, also can avoid the problem of circuit base plate 100a, 100b, 200a, 200b, 200c warpage.In addition, compared to known technology, the manufacture method of circuit base plate 100a, the 100b of present embodiment, 200a, 200b, 200c need not to adopt metal substrate to be used as supports loadboard, be a kind of coreless circuit base plate, can effectively reduce the cost of manufacture of circuit base plate 100a, 100b, 200a, 200b, 200c, and can improve the reliability of circuit base plate 100a, 100b, 200a, 200b, 200c and effectively reduce the time-histories of making circuit base plate 100a, 100b, 200a, 200b, 200c.
What deserves to be mentioned is; the present invention does not limit the form of these metal levels 102,202; though these metal levels 102,202 that reach mentioned herein are specialized the forms that are respectively single metal level; but in other embodiment; the metal level that these metal levels 102,202 also are made up of the multilayer copper foil layer; this still belongs to the adoptable technical scheme of the present invention, does not break away from the scope of institute of the present invention desire protection.
Specifically, Fig. 3 A to Fig. 3 P is the generalized section of manufacture method of circuit base plate of another embodiment of embodiments of the invention.Please refer to Fig. 3 A, manufacture method about the circuit base plate of present embodiment, at first, two metal levels 310 ', 310 are provided "; wherein metal level 310 ' is made up of the first copper foil layer 310a, the second copper foil layer 310b that is positioned on the first copper foil layer 310a, and metal level 310 " be by the 3rd copper foil layer 310c and be positioned at the 4th copper foil layer 310d on the 3rd copper foil layer 310c.Wherein, the second copper foil layer 310b is incorporated on the 4th copper foil layer 310d by adhesive 320 parts.That is to say that adhesive 320 is between the second copper foil layer 310b and the 4th copper foil layer 310d, and only bonding partly second copper foil layer 310b and the 4th copper foil layer 310d.In addition, first copper foil layer 310a described herein and the second copper foil layer 310b on it can be considered coreless (coreless) structure sheaf.In like manner, the 3rd copper foil layer 310c and the 4th copper foil layer 310d on it can be considered the coreless structure sheaf.
In the present embodiment, greater than the thickness of the first copper foil layer 310a, wherein the thickness of the first copper foil layer 310a for example is 3 microns (μ m) to the thickness of the second copper foil layer 310b in fact, and the thickness of the second copper foil layer 310b for example is 12 microns (μ m).The thickness of the first copper foil layer 310a is identical in fact with the thickness of the 3rd copper foil layer 310c, and the meaning i.e. thickness of the 3rd copper foil layer 310c also for example is 3 microns (μ m).The thickness of the second copper foil layer 310b is identical in fact with the thickness of the 4th copper foil layer 110d, and the meaning i.e. thickness of the 4th copper foil layer 310d also for example is 12 microns (μ m).Wherein, the second copper foil layer 310b of present embodiment can be in order to the usefulness as the support first copper foil layer 310a, and in like manner, the 4th copper foil layer 310d can be in order to the usefulness as support the 3rd copper foil layer 310c.Therefore, present embodiment need not be used as prop carrier as known use metal substrate, can effectively reduce cost of manufacture.In addition, the adhesive 320 of present embodiment for example is cyanoacrylate (generally being commonly called as three seconds glue), acrylic resin (being PP glue).What deserves to be mentioned is, though be to adopt adhesive 320 to engage the second copper foil layer 310b and the 4th copper foil layer 310d in present embodiment, but in the embodiment that other do not illustrate, the mode that also can see through the welding Copper Foil is come in conjunction with the second copper foil layer 310b and the 4th copper foil layer 310d, and the adhesive 320 of this moment then is the Copper Foil of fusion.Herein, described juncture must belong to the example that the present invention desires to contain.
Then, please refer to Fig. 3 B, form a plurality of first perforations 332 that extend to the 3rd copper foil layer 310c from the first copper foil layer 310a.Anticipate promptly, first perforation 332 runs through the first copper foil layer 310a, the second copper foil layer 310b, the 4th copper foil layer 310d and the 3rd copper foil layer 310c at least.In the present embodiment, the method that forms first perforation 332 comprises machine drilling.
Then, please refer to Fig. 3 C, the pressing first insulating barrier 350a be positioned at first conductive layer 342 on the first insulating barrier 350a on the first copper foil layer 310a, and the second insulating barrier 350b of pressing simultaneously be positioned at second conductive layer 344 on the second insulating barrier 350b on the 3rd copper foil layer 310c.In the present embodiment, the first insulating barrier 350a and the second insulating barrier 350b are respectively in the face of the first copper foil layer 310a and the 3rd copper foil layer 310c, wherein when pressing, the first insulating barrier 350a and the second insulating barrier 350b of part are filled in first perforation 332, to fill up first perforation 332.In addition, the material of first conductive layer 342 and second conductive layer 344 for example is a copper.
Particularly, in the present embodiment, the thickness of the first insulating barrier 350a adds that the thickness of first conductive layer 342 adds the thickness of the second copper foil layer 310b greater than the thickness of the first copper foil layer 310a.Wherein, the thickness of the first insulating barrier 350a for example is 40 microns (μ m), and the thickness of first conductive layer 342 for example is 18 microns (μ m).In like manner, the thickness of the second insulating barrier 350b adds that the thickness of second conductive layer 344 adds the thickness of the 4th copper foil layer 310d greater than the thickness of the 3rd copper foil layer 310c.Wherein, the thickness of the second insulating barrier 350b is identical in fact with the thickness of the first insulating barrier 350a, and it for example is 40 microns (μ m).The thickness of second conductive layer 344 is identical in fact with the thickness of first conductive layer 342, and it for example is 18 microns (μ m).
Then, please refer to Fig. 3 D, form and a plurality ofly extend to second perforation 334 of second conductive layer 344 from first conductive layer 342, wherein second perforation 334 runs through first conductive layer 342, the first insulating barrier 350a, the first copper foil layer 310a, the second copper foil layer 310b, the 4th copper foil layer 310d and the 3rd copper foil layer 310c, the second insulating barrier 350b and second conductive layer 344 at least.In addition, second perforation 334 can be in order to as the follow-up auxiliary usefulness that removes adhesive 320, and meaning promptly removes the zone that the second copper lamina 310b combines with the 4th copper foil layer 310d.In general, usually all can be on first conductive layer 342 and second conductive layer 344 by a plurality of metal patterns (not illustrating), and the purpose of metal pattern is to can be used as in the technology datum mark of location and contraposition.That is to say, metal pattern on first conductive layer 342 and second conductive layer 344 can be used as the benchmark with the first copper foil layer 310a and the 3rd copper foil layer 310c location and contraposition, also can be used as and the location of follow-up the 5th copper foil layer 310e (please refer to Fig. 3 G) and the benchmark of contraposition.
Then, please refer to Fig. 3 E, patterning first conductive layer 342 and second conductive layer 344 are to form the first line layer 342a and the second line layer 344a.Wherein, the method for patterning first conductive layer 342 and second conductive layer 344 comprises the photoengraving carving technology.Particularly, since first conductive layer 342 of present embodiment and second conductive layer 344 are modes of seeing through pressing be pressed on respectively that the first insulating barrier 350a goes up and the second insulating barrier 350b on, and form the first line layer 342a and the second line layer 344a via the mode of patterning.Therefore, compared to the known formed line layer of plating mode that utilizes, the first line layer 342a and the second line layer 344a of present embodiment have the thick uniformity of preferred copper.In addition, since the first copper foil layer 310a, the second copper foil layer 310b, the 3rd copper foil layer 310 and the 4th copper foil layer 310d of this enforcement all because hot pressing and in be embedded among the first insulating barrier 350a and the second insulating barrier 350b, therefore when patterning first conductive layer 342 and second conductive layer 344, can avoid extraneous impurity or medicament to pollute, and can keep size and the thickness of the first copper foil layer 310a, the second copper foil layer 310b, the 3rd copper foil layer 310 and the 4th copper foil layer 310d.
Then, please refer to Fig. 3 F, remove adhesive 320, the first circuit base plate 360a and the second circuit base plate 360b that are separated from each other with formation.In the present embodiment, can be by aforementioned described second perforation, the 334 auxiliary adhesives 320 that remove.That is to say that the formation that sees through second perforation 334 can destroy the adhesion strength between adhesive 320 and the second copper foil layer 310b and the 4th copper foil layer 310d, so more easily removes adhesive 320.In addition, the method that removes adhesive 320 for example is machine drilling or milling machine processing.What deserves to be mentioned is, in the present embodiment, because adhesive 320 only is incorporated between the second copper foil layer 310b and the 4th copper foil layer 310d part, therefore remove colloids a large amount of between line layer and the metal substrate compared to known, present embodiment is comparatively simple and the difficulty in process degree is also lower in the step that removes adhesive 320, can improve the technology yield.
In the present embodiment, removing the adhesive 320 formed first circuit base plate 360a in back and the second circuit base plate 360b is symmetrical structure.Wherein, the first circuit base plate 360a comprises the first line layer 342a, the first insulating barrier 350a, the first copper foil layer 310a and the second copper foil layer 310b in regular turn.The second circuit base plate 360b comprises the second line layer 344a, the second insulating barrier 350b, the 3rd copper foil layer 310c and the 4th copper foil layer 310d in regular turn.Below for convenience of description for the purpose of, be the making that example is carried out follow-up circuit base plate only with the first circuit base plate 360a.
Then, please refer to Fig. 3 G, remove the second copper foil layer 310b, and pressing the 3rd insulating barrier 350c and be positioned at the 5th copper foil layer 310e on the 3rd insulating barrier 350c on the first line layer 342a.In the present embodiment, the method that removes the second copper foil layer 310b for example is to peel off method (lift-off), and meaning promptly utilizes the mode of peeling off that the second copper foil layer 310b is peeled off the first copper foil layer 310a.In addition, pressing the 3rd insulating barrier 350c and the 5th copper foil layer 310e are on the first line layer 342a, so that the first line layer 342a becomes the internal wiring layer.Meaning promptly, the first line layer 342a is embedded in the line layer between the 3rd insulating barrier 350c and the first insulating barrier 350a in being.In addition, pressing the 5th copper foil layer 310e can guarantee to have preferred contraposition precision between the first copper foil layer 310a, the first line layer 342a and the 5th copper foil layer 310e in being that metal pattern (not illustrating) with on the first line layer 342a (former first conductive layer 342) is used as benchmark on the first line layer 342a.
In general; the thinner thickness of the 5th copper foil layer 310e; it for example is 3 microns (μ m); therefore when desiring pressing the 5th copper foil layer 310e; usually can be prior to adding the thicker copper foil layer of another thickness (not illustrating) on the 5th copper foil layer 310e; its thickness for example is 12 microns (μ m), can prevent that the 5th copper foil layer 310e after the pressing from presenting the phenomenon of bending, to keep the surface smoothness of the 5th copper foil layer 310e after the pressing.Afterwards, after pressing, again that thickness is thicker copper foil layer is peeled off, and the 5th copper foil layer 310e that stays thinner thickness carries out follow-up technology.
In brief, the 3rd insulating barrier 350c of present embodiment is pressed on after removing adhesive 320 on the first line layer 342a with the 5th copper foil layer 310e that is positioned on the 3rd insulating barrier 350c.Yet, the present invention do not limit pressing the 3rd insulating barrier 350c with the position thereon the 5th copper foil layer 310e and the sequence of steps that removes adhesive 320.In other embodiment, the 3rd insulating barrier 350c and the 5th copper foil layer 310e that is positioned on the 3rd insulating barrier 350c also can be pressed on before removing adhesive 320 on the first line layer 342a.
Specifically, can be shown in Fig. 4 A, pressing the 3rd insulating barrier 350c of elder generation and be positioned at the 5th copper foil layer 310e on the 3rd insulating barrier 350c on the first line layer 342a, and pressing the 4th insulating barrier 350d and be positioned at the 6th copper foil layer 310f on the 4th insulating barrier 350d on the second line layer 344a simultaneously.Then, shown in Fig. 4 B, remove adhesive 320, the second copper foil layer 310b and the 4th copper foil layer 310d for another example, the tertiary circuit substrate 400c and the 4th circuit base plate 400d that are separated from each other with formation.Wherein, remove that formed tertiary circuit substrate 400c and the 4th circuit base plate 400d are symmetrical structure behind adhesive 320, the second copper foil layer 310b and the 4th copper foil layer 310d, and tertiary circuit substrate 400c comprises the 5th copper foil layer 310e, the 3rd insulating barrier 350c, the first line layer 342a, the first insulating barrier 350a and the first copper foil layer 310a in regular turn.In like manner, the 4th circuit base plate 400d comprises the 6th copper foil layer 310f, the 4th insulating barrier 350d, the second line layer 344a, the second insulating barrier 350b and the 3rd copper foil layer 310c in regular turn.In other words, can optionally adjust according to process requirements pressing insulating barrier and thereon copper foil layer of position on line layer with the step that removes adhesive 320, therefore above-mentioned Fig. 3 F to Fig. 3 G is only for illustrating, not as limit.
So far, finished the making of the first circuit base plate 400a, wherein the first circuit base plate 400a comprises the 5th copper foil layer 310e, the 3rd insulating barrier 350c, the first line layer 342a, the first insulating barrier 350a and the first copper foil layer 310a in regular turn.
Then, please refer to Fig. 3 H, the 5th copper foil layer 310e and the first copper foil layer 310a are carried out bore process, a plurality ofly extend to first blind hole 412 of the first line layer 342a and a plurality of second blind hole 414 that extends to the first line layer 342a from the first copper foil layer 310a to form from the 5th copper foil layer 310e.Wherein, first blind hole 412 and second blind hole 414 expose the part first line layer 342a.In the present embodiment, bore process for example is a laser drill, and meaning is that first blind hole 412 and second blind hole 414 are to adopt the mode of laser ablation to form.
Then, please refer to Fig. 3 I, form chemical copper layer 420 in first blind hole 412 and second blind hole 414, wherein chemical copper layer 420 connection the 5th copper foil layer 310e is with the first line layer 342a and be connected the first copper foil layer 310a and the first line layer 342a.Particularly, in the present embodiment, chemical copper layer 420 covers the 5th copper foil layer 310e, first blind hole 412, the first copper foil layer 310a and second blind hole 414, and the 5th copper foil layer 310e sees through chemical copper layer 420 and the first line layer 342a electrically connects, and the first copper foil layer 310a sees through chemical copper layer 420 and the first line layer 342a electrically connects.In addition, the method that forms chemical copper layer 420 is for example carried out electroless plating technology (electroless plating process).
Then, please refer to Fig. 3 J, form the first patterning dry film photoresist layer 432 on the 5th copper foil layer 310e, and form the second patterning dry film photoresist layer 434 on the first copper foil layer 310a.Wherein, the first patterning dry film photoresist layer 432 exposes first blind hole, 412, the second patterning dry film photoresist layers 434 at least and exposes second blind hole 414 at least.Particularly, in the present embodiment, the first patterning dry film photoresist layer 432 exposes the chemical copper layer 420 that is positioned at first blind hole 412 and is positioned at chemical copper layer 420 on part the 5th copper foil layer 310e.The second patterning dry film photoresist layer 434 expose be positioned at second blind hole 414 chemical copper layer 420 and be positioned at chemical copper layer 420 on the part first copper foil layer 310e.
Then, please refer to Fig. 3 K, form copper electroplating layer 440 to being less than in first blind hole 412 with in second blind hole 414, wherein copper electroplating layer 440 fills up first blind hole 412 and second blind hole 414, and cover part chemical copper layer 420.In the present embodiment, by the first patterning dry film photoresist layer 432 and the second patterning dry film photoresist layer 434 mask when electroplating, form copper electroplating layer 440 in first blind hole 412, in second blind hole 414 and do not cover on the chemical copper layer 420 of the first patterning dry film photoresist layer 432 and the second patterning dry film photoresist layer 434 in the mode that adopts filling perforation to electroplate (via filling plating).
Then, please refer to Fig. 3 L, remove the first patterning dry film photoresist layer 432 and the part chemical copper layer 420 and part the 5th copper foil layer 310e that are positioned under the first patterning dry film photoresist layer 432, and remove the second patterning dry film photoresist layer 434 and the part chemical copper layer 420 and the part first copper foil layer 310a that are positioned under the second patterning dry film photoresist layer 434.So, exposing part the 3rd insulating barrier 350c and the part first insulating barrier 350a, and in first blind hole 412, form the first conductive blind hole structures 412a, the formation second conductive blind hole structures 414a second blind hole 414 in.In the present embodiment, removing the first patterning dry film photoresist layer 432, be positioned at part chemical copper layer 420 and part the 5th copper foil layer 310e, the second patterning dry film photoresist layer 434 under the first patterning dry film photoresist layer 432 and be positioned at part chemical copper layer 420 under the second patterning dry film photoresist layer 434 and the method for the first copper foil layer 310a, for example is to carry out etch process.So far, formed the first conductive blind hole structures 412a and the second conductive blind hole structures 414a that electrically connects with the first line layer 342a.
Then, please refer to Fig. 3 M, form first protective layer 452 on the 3rd insulating barrier 350c, and form second protective layer 454 on the first insulating barrier 350a.In the present embodiment, first protective layer 452 covers the 3rd insulating barrier 350c and the first conductive blind hole structures 412a that is exposed on the 3rd insulating barrier 350c, in order to protect the pattern integrity of the first conductive blind hole structures 412a.In like manner, second protective layer 454 covers the first insulating barrier 350a and the second conductive blind hole structures 414a that is exposed on the first insulating barrier 350a, in order to protect the pattern integrity of the second conductive blind hole structures 414a.In addition, the method that forms first protective layer 452 and second protective layer 454 for example is a screen painting, and the material of first protective layer 452 and second protective layer 454 for example is a printing ink.
Then, please refer to Fig. 3 N, carry out grinding technics, removing part first protective layer 452, and remove part second protective layer 454 to the surface that exposes the first conductive blind hole structures 412a to the surface that exposes the first conductive blind hole structures 412a.At this moment, the surface of the surface of first protective layer 452 and the first conductive blind hole structures 412a trims in fact, and the surface of the surface of second protective layer 454 and the second conductive blind hole structures 414a trims in fact.
Then; please refer to Fig. 3 O; remove first protective layer 452 and second protective layer 454 left over, to expose part the 3rd insulating barrier 350c, be exposed to the first conductive blind hole structures 412a, the part first insulating barrier 350a on the 3rd insulating barrier 350c and be exposed to the second conductive blind hole structures 414a on the first insulating barrier 350a.In the present embodiment; form first protective layer 452 and second protective layer 454, carry out grinding technics and remove first protective layer 452 and the purpose of the processing step that second protective layer 454 etc. is continuous is to make the surface of the first conductive blind hole structures 412a and the surface of the second conductive blind hole structures 414a to have preferred surface smoothness, help follow-up and packaging technology chip.
Then, please refer to Fig. 3 P, form first welding resisting layer 462 on the 3rd insulating barrier 350c, and form second welding resisting layer 464 on the first insulating barrier 350a.In the present embodiment, first welding resisting layer 462 has a plurality of first opening 462a, and wherein the first opening 462a exposes the part first conductive blind hole structures 412a, can be in order to the usefulness as joint sheet.Second welding resisting layer 464 has a plurality of second opening 464a, and wherein the second opening 464a exposes the part second conductive blind hole structures 414a, can be in order to the usefulness as joint sheet.So far, finished the making of circuit base plate 300.
Because the first opening part that 462a exposes, the first conductive blind hole structures 412a of first welding resisting layer 462 can be in order to the usefulness as joint sheet, and the second opening part that 464a exposes, the second conductive blind hole structures 414a of second welding resisting layer 464 can be in order to the usefulness as joint sheet.So, when mode and the joint sheet electric connection of chip (not illustrating), and after being coated on chip in the colloid (not illustrating) with the filler mould, can finish chip package process by wire-bonded or flip-chip bonded.In other words, the circuit base plate 300 of present embodiment is suitable for as chip packaging carrying plate.
In brief, because present embodiment need not support the first copper foil layer 310a and the 3rd copper foil layer 310c by metal substrate, therefore compared to known technology, the manufacture method of the circuit base plate 300 of present embodiment can effectively reduce cost of manufacture.In addition, present embodiment is by pressing first conductive layer 342 and second conductive layer 344, and the mode by patterning first conductive layer 342 and second conductive layer 344 forms the first line layer 342a and the second line layer 344a more afterwards.By the formed line layer of plating mode, the first line layer 342a and the second line layer 344a of present embodiment have the thick uniformity of preferred copper compared to known.In addition, present embodiment is by location and the contraposition reference of the first line layer 342a (former first conductive layer 342) as the first copper foil layer 310a and the 5th copper foil layer 310e.Thus, can effectively promote the contraposition precision of circuit base plate 300, make the circuit base plate that forms 300 have preferred production yield and reliability.
In sum, the present invention will engage around two metal levels earlier, to form seal area.Wait to finish after the pressing step of two-sided insulating barrier and two-sided conductive layer, again two metal levels are separated.Therefore, compared to known technology, the manufacture method of circuit base plate of the present invention need not to adopt metal substrate to be used as supports loadboard, meaning is the coreless circuit base plate, can effectively reduce the cost of manufacture of circuit base plate, and can improve the reliability of circuit base plate and effectively reduce the time-histories of making circuit base plate.In addition, the present invention also need not to fix metal substrate and line layer as a large amount of colloid of known use, and therefore the manufacture method of circuit base plate of the present invention need not face a difficult problem that removes a large amount of colloid layers, can effectively reduce difficulty in process degree and processing step.In addition, because the present invention also can utilize the mode pressing conductive layer of pressing, the mode by patterned conductive layer forms line layer more afterwards.
Though the present invention discloses as above with embodiment; right its is not in order to qualification the present invention, those of ordinary skill in any affiliated technical field, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention defines and is as the criterion when looking claim.
Claims (16)
1. the manufacture method of a circuit base plate comprises:
Engage the periphery of two metal levels, to form the driving fit district;
Form and at least always wear the perforation in this driving fit district;
Form two insulating barriers on this two metal level, and form two conductive layers on this two insulating barrier;
This two insulating barrier of pressing and this two conductive layer wherein be embedded in this two insulating barrier in this that engages two metal levels, and this two insulating barrier fill in this perforation to this two metal level; And
This driving fit district that separates this two metal level is to form two circuit base plates of each self-separation.
2. the manufacture method of circuit base plate as claimed in claim 1, the method that wherein engages the periphery of this two metal level comprise electric welding, spot welding or by adhesive, and the material of this adhesive comprises cyanoacrylate or acrylic resin.
3. the manufacture method of circuit base plate as claimed in claim 1 also comprises:
After this two insulating barrier of pressing and this two conductive layer are to this two metal level, remove this two insulating barrier of part and this two conductive layer of part, to form a plurality of blind holes that manifest this two metal level;
Form electric conducting material in these a plurality of blind holes and on this two conductive layer that is not removed; And
After this driving fit district that separates this two metal level, this electric conducting material of patterning, this metal level and this conductive layer.
4. the manufacture method of circuit base plate as claimed in claim 1 also comprises:
After this two insulating barrier of pressing and this two conductive layer are to this two metal level, remove this two insulating barrier of part and this two conductive layer of part, to form a plurality of blind holes that manifest this two metal level;
This two conductive layer of thinning;
Form on two plating seed layers this two conductive layer after thinning with these a plurality of blind holes in;
After this driving fit district that separates this two metal level, expose this metal level;
Form patterning photoresist layer respectively in being positioned on this plating seed layer and on this metal level that is exposed out;
With these a plurality of patterning photoresist layers is mask, and these a plurality of plating seed layers are electroplated; And
Remove the part that these a plurality of patterning photoresist layers and this a plurality of plating seed layers are covered by these a plurality of patterning photoresist layers.
5. the manufacture method of circuit base plate as claimed in claim 1 also comprises:
After this two insulating barrier of pressing and this two conductive layer were to this two metal level, this two conductive layer of patterning was to form this two patterned conductive layer;
Form in addition two insulating barriers on this two patterned conductive layer, and form in addition two conductive layers in this in addition on two insulating barriers;
These a plurality of insulating barriers of pressing reach two conductive layers in addition, and are embedded in these a plurality of insulating barriers in this two patterned conductive layer;
After this driving fit district that separates this two metal level, remove these a plurality of insulating barriers of part, this metal level of part and this another conductive layer of part, to form a plurality of blind holes that manifest this patterned conductive layer;
Form electric conducting material in these a plurality of blind holes and on this metal level and this another conductive layer of not being removed; And
This electric conducting material of patterning, this metal level and this another conductive layer.
6. the manufacture method of circuit base plate as claimed in claim 1 also comprises:
After this two insulating barrier of pressing and this two conductive layer were to this two metal level, this two conductive layer of patterning was to form this two patterned conductive layer;
Form in addition two insulating barriers on this two patterned conductive layer, and form in addition two conductive layers in this in addition on two insulating barriers;
These a plurality of insulating barriers of pressing reach two conductive layers in addition, and are embedded in these a plurality of insulating barriers in this two patterned conductive layer;
After this driving fit district that separates this two metal level, remove these a plurality of insulating barriers of part, this metal level of part and this another conductive layer of part, to form a plurality of blind holes that manifest this patterned conductive layer;
Remove this another conductive layer and this metal level, to expose this a plurality of insulating barriers;
Form two plating seed layers on these a plurality of insulating barriers and in these a plurality of blind holes;
Form two patterning photoresist layers on this two plating seed layer;
With these a plurality of patterning photoresist layers is mask, and these a plurality of plating seed layers are electroplated; And
Remove the part that these a plurality of patterning photoresist layers and this a plurality of plating seed layers are covered by these a plurality of patterning photoresist layers.
7. the manufacture method of circuit base plate as claimed in claim 1 also comprises:
After this two insulating barrier of pressing and this two conductive layer are to this two metal level, remove this two insulating barrier of part and this two conductive layer of part, to form a plurality of first blind holes that manifest this two metal level;
Remove this two conductive layer to expose this two insulating barrier;
Form two plating seed layers on this two insulating barrier and in these a plurality of first blind holes;
Form two patterning photoresist layers on these a plurality of plating seed layers;
With these a plurality of patterning photoresist layers is mask, and these a plurality of plating seed layers are electroplated;
Remove the part that these a plurality of patterning photoresist layers and this a plurality of plating seed layers are covered by these a plurality of patterning photoresist layers, on this two insulating barrier, to form two patterned conductive layers and a plurality of conductivity through-hole structure;
Form in addition two insulating barriers on this two patterned conductive layer, and form in addition two conductive layers in this in addition on two insulating barriers;
These a plurality of insulating barriers of pressing reach two conductive layers in addition, and are embedded in these a plurality of insulating barriers in this two patterned conductive layer;
After this driving fit district that separates this two metal level, remove these a plurality of insulating barriers of part, this metal level and this another conductive layer, to form a plurality of second blind holes that manifest this patterned conductive layer;
Form two plating seed layers in addition in this in addition on two insulating barriers, in the end and this a plurality of second blind holes of these a plurality of first blind holes;
Form in addition two patterning photoresist layers in this in addition on two plating seed layers;
Other two patterning photoresist layers are mask with this, and other electroplates by two plating seed layers to this; And
Remove this in addition two patterning photoresist layers and the part that covered by two patterning photoresist layers in addition of two plating seed layers in addition.
8. the manufacture method of circuit base plate as claimed in claim 1, wherein this two metal level comprises first copper foil layer and second copper foil layer respectively, and respectively greater than the thickness of this first copper foil layer respectively, these a plurality of second copper foil layers engage the thickness of this second copper foil layer each other in fact.
9. the manufacture method of circuit base plate as claimed in claim 8 also comprises:
This two insulating barrier of pressing and this two conductive layer to this two metal level after, this two conductive layer of patterning is to form first patterned conductive layer and second patterned conductive layer;
Form a plurality of first perforations that extend to this second patterned conductive layer from this first patterned conductive layer;
After this driving fit district that separates this two metal level, remove this second copper foil layer;
Form first insulating barrier on this first patterned conductive layer, and form first conductive layer on this first insulating barrier;
This first insulating barrier of pressing and this first conductive layer, and be embedded in this first patterned conductive layer in this insulating barrier and this first insulating barrier;
Remove this insulating barrier of part, this first insulating barrier, this first copper foil layer of part and this first conductive layer of part, to form a plurality of first blind holes that manifest this first patterned conductive layer;
Form plating seed layer respectively on this first copper foil layer that does not remove and in these a plurality of first blind holes and on this first conductive layer that does not remove and in these a plurality of first blind holes;
Form two patterning photoresist layers on these a plurality of plating seed layers;
With these a plurality of patterning photoresist layers is mask, these a plurality of plating seed layers is electroplated, to form a plurality of conductive blind hole structures in these a plurality of first blind holes; And
Remove the part that these a plurality of patterning photoresist layers and this a plurality of plating seed layers are covered by these a plurality of patterning photoresist layers.
10. the manufacture method of circuit base plate as claimed in claim 9 wherein forms this first insulating barrier on this first patterned conductive layer, and forms this first conductive layer in being on this first insulating barrier after separating this driving fit district of this two metal level.
11. the manufacture method of circuit base plate as claimed in claim 9 wherein forms this first insulating barrier on this first patterned conductive layer, and forms this first conductive layer in being on this first insulating barrier before separating this driving fit district of this two metal level.
12. the manufacture method of circuit base plate as claimed in claim 11 also comprises:
Form this first insulating barrier on this first patterned conductive layer, and form this first conductive layer on this first insulating barrier the time, form on second insulating barrier and this second patterned conductive layer, and form second conductive layer on this second insulating barrier.
13. the manufacture method of circuit base plate as claimed in claim 9 also comprises:
Remove these a plurality of patterning photoresist layers and this a plurality of plating seed layers by after the part of these a plurality of patterning photoresist layers coverings, form first protective layer on this first insulating barrier, and form second protective layer on this insulating barrier, wherein this first protective layer and this second protective layer cover these a plurality of conductive blind hole structures;
Carry out grinding technics, to remove this first protective layer of part and this second protective layer of part to exposing this a plurality of conductive blind hole structures;
Remove this first protective layer and this second protective layer left over.
14. the manufacture method of circuit base plate as claimed in claim 9 also comprises:
Remove these a plurality of patterning photoresist layers and this a plurality of plating seed layers by after the part of these a plurality of patterning photoresist layers coverings, form first welding resisting layer on this first insulating barrier, and form second welding resisting layer on this insulating barrier, wherein this first welding resisting layer has a plurality of first openings, this second welding resisting layer has a plurality of second openings, and these a plurality of first openings expose this conductive blind hole structures of part with these a plurality of second openings.
15. the circuit base plate with the manufacture method made of the described circuit base plate of claim 3 comprises:
The metal level of patterning;
The conductive layer of patterning;
Insulating barrier is between the conductive layer of the metal level of this patterning and this patterning; And
Electric conducting material is arranged in a plurality of blind holes, and these a plurality of blind holes run through this a plurality of insulating barriers, and this electric conducting material is electrically connected at the metal level of this patterning and the conductive layer of this patterning.
16. the circuit base plate with the manufacture method made of the described circuit base plate of claim 5 comprises:
The metal level of patterning;
The conductive layer of patterning;
Patterned conductive layer is between this conductive layer of this metal level of patterning and patterning;
Two insulating barriers lay respectively between this metal level of patterning and this patterned conductive layer and between this conductive layer and this patterned conductive layer of patterning; And
Electric conducting material is arranged in a plurality of blind holes, and these a plurality of blind holes run through this a plurality of insulating barriers, and this electric conducting material is electrically connected between this metal level of patterning and this patterned conductive layer and between this conductive layer and this patterned conductive layer of patterning.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010135838.3 | 2010-03-16 | ||
| CN201010241628.2 | 2010-07-29 | ||
| TW099141954A TWI400025B (en) | 2009-12-29 | 2010-12-02 | Circuit substrate and manufacturing method thereof |
| TW99141954 | 2010-12-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102194703A true CN102194703A (en) | 2011-09-21 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010106062075A Pending CN102194703A (en) | 2010-03-16 | 2010-12-24 | Circuit substrate and manufacturing method thereof |
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| Country | Link |
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| CN (1) | CN102194703A (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020125044A1 (en) * | 2000-12-28 | 2002-09-12 | Henry Johnson | Layered circuit boards and methods of production thereof |
| US6486394B1 (en) * | 1996-07-31 | 2002-11-26 | Dyconex Patente Ag | Process for producing connecting conductors |
| US20030168255A1 (en) * | 2000-04-11 | 2003-09-11 | Lg Electronics Inc. | Multi-layer printed circuit board and a BGA semiconductor package using the multi-layer printed circuit board |
| JP2005311076A (en) * | 2004-04-21 | 2005-11-04 | Sanyo Electric Co Ltd | Method for manufacturing multilayer board |
| JP2006049660A (en) * | 2004-08-06 | 2006-02-16 | Cmk Corp | Manufacturing method of printed wiring board |
| CN1993021A (en) * | 2005-12-26 | 2007-07-04 | 新光电气工业株式会社 | Method for manufacturing wiring board |
| JP2009081357A (en) * | 2007-09-27 | 2009-04-16 | Shinko Electric Ind Co Ltd | Wiring board and method of manufacturing the same |
| US20100031502A1 (en) * | 2008-08-07 | 2010-02-11 | Unimicron Technology Corp. | Method for fabricating blind via structure of substrate |
-
2010
- 2010-12-24 CN CN2010106062075A patent/CN102194703A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6486394B1 (en) * | 1996-07-31 | 2002-11-26 | Dyconex Patente Ag | Process for producing connecting conductors |
| US20030168255A1 (en) * | 2000-04-11 | 2003-09-11 | Lg Electronics Inc. | Multi-layer printed circuit board and a BGA semiconductor package using the multi-layer printed circuit board |
| US20020125044A1 (en) * | 2000-12-28 | 2002-09-12 | Henry Johnson | Layered circuit boards and methods of production thereof |
| JP2005311076A (en) * | 2004-04-21 | 2005-11-04 | Sanyo Electric Co Ltd | Method for manufacturing multilayer board |
| JP2006049660A (en) * | 2004-08-06 | 2006-02-16 | Cmk Corp | Manufacturing method of printed wiring board |
| CN1993021A (en) * | 2005-12-26 | 2007-07-04 | 新光电气工业株式会社 | Method for manufacturing wiring board |
| JP2009081357A (en) * | 2007-09-27 | 2009-04-16 | Shinko Electric Ind Co Ltd | Wiring board and method of manufacturing the same |
| US20100031502A1 (en) * | 2008-08-07 | 2010-02-11 | Unimicron Technology Corp. | Method for fabricating blind via structure of substrate |
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Application publication date: 20110921 |