CN102186234B - Gain control circuit and method - Google Patents
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Abstract
The invention discloses a gain control circuit and method. The gain control circuit comprises an instantaneous power calculator, a loop filter, a gain accumulator and an accumulated gain value processing module, wherein the instantaneous power calculator is used for calculating instantaneous output power; the loop filter is used for filtering the instantaneous output power; the gain accumulator is used for calculating the current accumulated gain value according to the filtered instantaneous output power; the accumulated gain value processing module is used for receiving the accumulated gain value; bitwise reversion is performed on a bit used for representing the accumulated gain value, and a preset value is added to the accumulated gain value to obtain a processed accumulated gain value if the accumulated gain value exceeds a preset grain range; and the processed accumulated gain value as a gain application value is output to an input end of DAGC (Delayed Automatic Gain Control). In the control circuit disclosed by the embodiment of the invention, the bitwise reversion is performed on the bit used for representing the accumulated gain value, and the preset value is added to the accumulated gain value when the accumulated gain value exceeds the preset grain range, so that the phenomenon of influencing the convergence rate of the DAGC due to DAGC circuit oscillation caused by an overlarge or over small gain application value is avoided, and therefore, the working stability of the DAGC is ensured.
Description
Technical field
The present invention relates to communication technical field, relate in particular to gain control circuit and method.
Background technology
Mobile telecommunication channel is a kind of communication channel of complexity, and it has characteristics such as rapid fading, slow fading and multipath stack, and dafing depth can reach tens dB.This decline causes receiving signal and has very big power excursion, worsens the demodulation performance of system.
Usually use DAGC(Digital Automatic Gain Control in the mobile telecommunication channel, digital gain control), adjust the power of supplied with digital signal, make when input signal strength changes, the intensity of output signal can remain unchanged substantially, and output signal is carried out amplitude limiting processing, to reduce the realization burden of follow-up base band signal process algorithm, increase it and realize precision, reduce and realize bit wide.Usually the DAGC module comprises instantaneous power computing unit, loop filter and gain accumulator.Above-mentioned each unit cooperatively interacts, and according to the statistic of output signal power and the residual quantity of reference power thresholding, decides the variable quantity of adjusting yield value, with the numeric field power stability at reference levels.
But; in the said method because fluctuation and the hysteresis quality of power detection; can there be the accumulative total effect; therefore; the accumulated value that can cause gaining exceeds the gain ranging that digital bit wide can be represented; thereby cause gain to be overflowed, the gain accumulated value that will exceed the bit wide scope is applied in the circuit, can make the rate of convergence of circuit very slow.
Summary of the invention
In view of this, the invention provides a kind of gain control circuit and method, its concrete scheme is as follows:
A kind of digital gain control circuit DAGC comprises: instantaneous power calculator, loop filter, gain accumulator, gain accumulated value processing module and control module, wherein:
Described instantaneous power calculator be used for to calculate the instantaneous output of DAGC output, and described instantaneous output is inputed to described loop filter;
Described loop filter is used for described instantaneous output is carried out filtering, and filtered instantaneous output is inputed to described gain accumulator;
Described gain accumulator is used for calculating current gain accumulated value according to described filtered instantaneous output, and described gain accumulated value is inputed to described gain accumulated value processing module;
Described gain accumulated value processing module, be used for receiving described gain accumulated value, if described gain accumulated value exceeds default gain ranging, gain accumulated value after the bit of representing described gain accumulated value carried out the step-by-step negate and add preset value and obtain handling, gain accumulated value after the described processing is exported to the input of described DAGC as the gain application value, so that described input is to the input signal adjustment that gains, wherein, described preset value is used for described gain accumulated value is adjusted in the described default gain ranging;
The input of described control module links to each other with described DAGC input, output links to each other with described gain accumulator with described loop filter, described control module is used for obtaining the input power of described DAGC input, and when described input power exceeded default power bracket, described DAGC resetted.
A kind of gain control method is applied among the digital gain control circuit DAGC, and this method comprises:
Control module is obtained the input power of described DAGC input, and when described input power exceeded default power bracket, described DAGC resetted;
Gain accumulated value processing module receives the current gain accumulated value of described gain accumulator computes from DAGC circuit gain accumulator;
If described gain accumulated value exceeds default gain ranging, gain accumulated value after the bit of representing described gain accumulated value carried out the step-by-step negate and add preset value and obtain handling, with the gain accumulated value after the described processing as the gain application value, wherein, described preset value is used for described gain accumulated value is adjusted in the described default gain ranging;
Export described gain application value to the input of described DAGC, so that described input is to the input signal adjustment that gains.
From above-mentioned technical scheme as can be seen, in the disclosed DAGC circuit of the embodiment of the invention, when the gain accumulated value exceeds default gain ranging, the bit of representing the gain accumulated value is carried out the step-by-step negate add the preset value processing, avoid causing because gain application value excessive or too small, the DAGC circuit that causes shakes, and the phenomenon that influences the rate of convergence of DAGC takes place, and has guaranteed the job stability of DAGC.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the structural representation of the disclosed a kind of DAGC of the embodiment of the invention;
Fig. 2 is the structural representation of the disclosed another DAGC of the embodiment of the invention;
Fig. 3 is the structural representation of the disclosed another DAGC of the embodiment of the invention;
Fig. 4 is the structural representation of the disclosed gain accumulated value of embodiment of the invention processing module;
Fig. 5 is the disclosed a kind of structural representation that overflows processing unit of the embodiment of the invention;
Fig. 6 is the schematic flow sheet of the disclosed processing method of the embodiment of the invention;
Fig. 7 is the disclosed another process flow schematic diagram of the embodiment of the invention;
Fig. 8 is the disclosed another process flow schematic diagram of the embodiment of the invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
The embodiment of the invention discloses a kind of DAGC circuit, its structure comprises as shown in Figure 1: instantaneous power calculator 11, loop filter 12, gain accumulator 13 and gain accumulated value processing module 14.
Wherein, instantaneous power calculator 11 is used for calculating the instantaneous output of DAGC output, and instantaneous output inputed to loop filter 12, loop filter 12 is used for instantaneous output is carried out filtering, and filtered instantaneous output is inputed to gain accumulator 13; The filtered power output that gain accumulator 13 is used for receiving adds up, calculate current gain accumulated value according to filtered instantaneous output, and the accumulated value that will gain inputs to gain accumulated value processing module 14, gain accumulated value processing module 14, be used for the receiving gain accumulated value, if the gain accumulated value exceeds default gain ranging, gain accumulated value after the bit of expression gain accumulated value carried out the step-by-step negate and add preset value and obtain handling, gain accumulated value after handling is exported to the input of DAGC as the gain application value, so that input is to the input signal adjustment that gains, wherein, preset value is adjusted in the default gain ranging for the accumulated value that will gain.
The disclosed DAGC circuit of present embodiment, when the gain accumulated value exceeds default gain ranging, gain accumulated value after the bit of expression gain accumulated value carried out the step-by-step negate and add preset value and obtain handling, with the gain accumulated value after handling as the gain application value, avoid causing because gain application value excessive or too small, and causing the DAGC circuit to shake, the phenomenon that influences the rate of convergence of DAGC takes place, and has guaranteed the stability of DAGC work.Default gain ranging is relevant with the bit wide of the bit of expression gain accumulated value in this example, and for example, when the bit wide of the bit of the accumulated value of representing to gain is 4 bits, its gain ranging is 0000-1111.
The structure of the disclosed DAGC circuit of another embodiment of the present invention as shown in Figure 2, except comprising each module shown in Figure 1 and device, can also comprise being arranged at and make bat output module 15 between input and output side, make bat output module 15 and be generally shift register, after the power signal of input input carried out buffer memory, export to output again, after instantaneous power calculator 11 calculates instantaneous power, instantaneous power value and power adjustment desired value are compared, if adjust desired value greater than power, then comparative result is for negative, adjusting gain diminishes gradually, if adjust desired value less than power, then comparative result is adjusted gain and is become big gradually for just, gain accumulator 13 carries out one by one add operation or reducing according to comparative result to yield value, calculate current gain accumulated value, after guaranteeing that current gain accumulated value outputed to the input of circuit as the gain application value, the yield value that can realize adjusting circuit reaches the purpose of power target value.
Further, the DAGC circuit structure in above-described embodiment can also be as shown in Figure 3, wherein, can also comprise control module 31 except comprising shown in Fig. 1 each module.Control module 31 is used for, and obtains the input power of DAGC, and when input power exceeded default power bracket, DAGC resetted.The input of control module 31 links to each other with the input of DAGC circuit in the present embodiment, and output links to each other with loop filter 12 with gain accumulator 13.
Preset range in the present embodiment can be set according to the application scenarios of reality is different.
The DAGC that resets of indication is in the present embodiment, and the yield value in the loop is reset to 0, makes input/output signal power can not be subjected to the influence of loop.Reset behind the DAGC, input signal is directly exported by output, need not through the loop adjustment that gains, specific implementation can for: the output of control module 31 is linked to each other with gain accumulated value processing module 14,0 yield value of ride gain accumulated value processing module 14 outputs makes loop can not carry out any processing to input signal.
In the present embodiment, behind the DAGC that resets, control module 31 sends reset signal to gain accumulator 13 and loop filter 12, make the value in gain accumulator and the loop filter return to initial value, to guarantee after starting DAGC, gain accumulator 13 and loop filter 14, are adjusted power as the basis with initial value.
In the present embodiment, by control module input power range is detected, when input power range has exceeded normal input signal power scope, with the DAGC circuit reset, make the DAGC circuit working in a metastable power bracket, avoid the excessive concussion that causes circuit of power, reduce convergence rate, further guaranteed the job stability of DAGC.
Further, the structure of the disclosed gain accumulated value of embodiment of the invention processing module comprises as shown in Figure 4: gain accumulated value acquiring unit 41, overflow processing unit 42 and output unit 43, wherein:
Gain accumulated value acquiring unit 41 is used for the receiving gain accumulated value; Be used for the gain accumulated value and exceed default gain ranging if overflow processing unit 42, the gain accumulated value after the bit of expression gain accumulated value is carried out the step-by-step negate and adds preset value and obtain handling, with the gain accumulated value after handling as the gain application value; Output unit 43 is used for the output gain applicable value to the input of DAGC, so that input is to the input signal adjustment that gains.
Further, each unit in above-mentioned module and the module, both can adopt and utilize program language to programme its function realization thought, program burn writing is gone in Programmable Logic Controller or the internal memory, and then the form of passing through software realizes, equally, can also adopt hardware mode to realize, as described below:
Overflow the structure of processing unit 42 as shown in Figure 5, comprise inverter 51, adder 52 and signal generator 53, the input of inverter 51 links to each other with the output of gain accumulated value acquiring unit 41, the output of inverter 51 links to each other with the first input end of adder 52, second input of adder 52 links to each other with the output of the signal generator 53 that produces preset value, and the output of adder 52 links to each other with the input of output unit 43.
The preset value of the output of the signal generator in the present embodiment can be set according to actual conditions.
Present embodiment does not limit the implementation of above-mentioned software or hardware, can adopt way of hardware and software combination equally, finish the partial function of this device by software, finish all the other functions of this device by hardware, both cooperatively interact, the final realization realized purpose of the present invention to the processing of gain accumulated value.
The present invention discloses a kind of gain control method, this method is applied in the DAGC circuit shown in above-described embodiment, and its flow process comprises as shown in Figure 6:
Step S61, gain accumulated value processing module are obtained the current gain accumulated value of gain accumulator computes in the DAGC circuit;
Gain accumulator from the DAGC circuit obtains current gain accumulated value.
If step S62 gain accumulated value exceeds default gain ranging, the gain accumulated value after the bit of expression gain accumulated value carried out the step-by-step negate and add preset value and obtain handling;
When the gain accumulated value exceeds default gain ranging, the gain accumulated value is handled, guarantee the gain application value of output along with the changing inversely of gain accumulated value change direction, avoid the excessive or too small rate of convergence to circuit of gain application value to impact.Preset value in the present embodiment can be the value of setting according to actual conditions, and selective value is 1 usually, can not have greatly changed to guarantee the gain accumulated value after the adjustment as far as possible, avoids undergoing mutation.
Step S63, the gain accumulated value after will handling be as the gain application value, and export the DAGC input to.
Gain accumulated value after adjusting is outputed in the DAGC circuit as the gain application value.
In the disclosed gain accumulated value of the present embodiment processing method, when the gain accumulated value exceeds default gain ranging, gain accumulated value after the bit of expression gain accumulated value carried out the step-by-step negate and add preset value and obtain handling, with the gain accumulated value after handling as the gain application value, avoid causing the excessive or too small of gain application value, thereby avoid taking place because the phenomenon of concussion takes place the excessive or too small DAGC circuit that causes of applicable value, influence the rate of convergence of DAGC, guaranteed the job stability of DAGC.
This method does not limit the type that gain is overflowed, and no matter is just to overflow or negative overflowing, and adopts said method can both realize identical effect.
Followingly provided a kind of example: the accumulated value of supposing to gain utilizes binary number to represent, the bit wide of the bit of expression gain accumulated value is 4 bits, and preset value can be 1, and its gain ranging is 0000-1111.Current gain accumulated value is in decrement states, the gain application value also is in decrement states, when gain last of accumulated value is output as 0000, currently be output as at 1111 o'clock, show that then the gain accumulated value has taken place by negative overflowing, the gain accumulated value of this moment has reached the lower limit of default gain ranging, if continue to reduce according to its direction of successively decreasing, then can influence the operate as normal of circuit, at this moment, the gain application value is because time delay, currently be output as 0000, in order to guarantee that its output next time can not continue to reduce, directly jump to 1111, to guarantee the service behaviour of circuit, what then will need to export 1111 carries out negate and adds 1 next time, obtain 0001, output again, then to the overflow value 1110 of subsequent gain accumulated value, 1101 grades adopt negate to add 1 mode equally and handle and obtain 0010,0011, this shows that gain application value after treatment increases gradually, guarantee effect is after the gain application value of DAGC circuit is reaching the lower limit of normal gain scope, return to normal scope gradually, make circuit working in normal gain ranging, make service behaviour more stable.
Negative sense for the gain accumulated value overflows, and this method can also can not undergone mutation to the gain application value of DAGC circuit input end by guarantee effect, has guaranteed the stable of circuit performance in this case.
Following another example that provided:
The bit wide of supposing the bit of expression gain accumulated value is 4 bits, and preset value can be 1, and its gain ranging is 0000-1111.Current gain accumulated value is in and increases progressively state, the gain application value also is in and increases progressively state, when gain last of accumulated value is output as 1111, currently be output as at 0000 o'clock, show that then the gain accumulated value has taken place just to overflow, the gain accumulated value of this moment has reached the upper limit of default gain ranging, if continue to increase according to its direction of successively decreasing, then can influence the operate as normal of circuit, at this moment, the gain application value is because time delay, currently is output as 1111, in order to guarantee that its output next time can not increase always, to guarantee the service behaviour of circuit, what then will need to export 0000 carries out negate and adds 1 next time, obtains 0000, output again, then the overflow value 0001 of subsequent gain accumulated value is carried out negate and add 1, obtain 1111, then to 0010,0011 grade adopts negate to add 1 mode equally and handles and obtain 1110,1101, and the like, then can reduce gradually continue the gain application value of increase originally according to the order that increases progressively, return to normal range (NR), guarantee the stability of circuit working.
Do not limit among above-mentioned two embodiment and adopt 1 the mode that adds in its processing procedure, can also be other numerical value of setting according to actual conditions, for example, if currently need within a short period of time and make the gain application value return to normal range (NR), then need this value to be set to 2 or other bigger values, make it when gradually changing, improve the speed that changes, make the gain application value of circuit return to as early as possible in the normal scope.
The flow process of another gain control method disclosed by the invention as shown in Figure 7, its idiographic flow comprises:
Step S71, control module are obtained the input power among the DAGC;
Obtain input power from the DAGC circuit input end.
Step S72, judge input power whether in default power bracket, if, execution in step S73a then, if not, execution in step S73b then.
Step S73a, startup DAGC, execution in step S74;
Step S73b, the DAGC that resets finish;
Step S74, gain accumulated value processing module are obtained the gain accumulated value among the DAGC;
Step S75, judge whether the gain accumulated value exceeds default gain ranging, if, execution in step S76 then, if not, execution in step S78 then;
Step S76, the bit of expression gain accumulated value is carried out the step-by-step negate add preset value and handle;
Gain accumulated value after step S77, the definite processing is the gain application value, and output;
Step S78, the accumulated value of determining to gain are the gain application value, and output.
Increased the judgement to the DAGC input power in the present embodiment, when input power range has exceeded normal input signal power scope, with the DAGC circuit reset, make the DAGC circuit working in a metastable power bracket, the power of avoiding causes the concussion of circuit, reduces convergence rate.
The flow process of another gain control method disclosed by the invention comprises as shown in Figure 7:
Step S81, gain accumulated value processing module are obtained the gain accumulated value among the DAGC;
Step S82, judge whether the overflow bit position in the bit of expression gain accumulated value is 1, if 1, execution in step S83a then, if be not 1, execution in step S83b then;
Yield value is unsigned number, if the bit wide of the bit of expression yield value is 4bit, namely represents the accumulated value that gains with four bits, and first is the overflow bit position, the numerical value representative gain accumulated value of back triad number.When the overflow bit position is 1, prove that then current generation gain overflows.
Step S83a, the accumulated value of determining to gain exceed default gain ranging, execution in step S34;
Step S83b, the accumulated value of determining to gain do not exceed default gain ranging, execution in step S36;
Step S84, the bit of expression gain accumulated value is carried out the step-by-step negate add 1 and handle;
Gain accumulated value after step S85, the definite processing is the gain application value, and output;
Step S86, the accumulated value of determining to gain are the gain application value, and output.
In the disclosed gain accumulated value of the present embodiment processing method, specifically disclose by the overflow bit position and judged the method whether the gain accumulated value overflows, present embodiment does not limit and adopts this method to judge whether the gain accumulated value overflows.When not comprising the overflow bit position in the bit of expression yield value bit wide, can determine directly whether the gain accumulated value overflows and overflow direction by the variation of highest order, for example, when it becomes 0 by 1, can determine that it overflows, and, it overflows direction for just overflowing, and when it becomes 1 by 0, can determine that it overflows, and it overflows direction and overflows for negative.
Can comprise control module in the present embodiment equally to the process of the judgement of DAGC input power.
Each embodiment adopts the mode of going forward one by one to describe in this specification, and what each embodiment stressed is and the difference of other embodiment that identical similar part is mutually referring to getting final product between each embodiment.For the disclosed device of embodiment, because it is corresponding with the embodiment disclosed method, so description is fairly simple, relevant part partly illustrates referring to method and gets final product.
The professional can also further recognize, unit and the algorithm steps of each example of describing in conjunction with embodiment disclosed herein, can realize with electronic hardware, computer software or the combination of the two, for the interchangeability of hardware and software clearly is described, composition and the step of each example described in general manner according to function in the above description.These functions still are that software mode is carried out with hardware actually, depend on application-specific and the design constraint of technical scheme.The professional and technical personnel can specifically should be used for using distinct methods to realize described function to each, but this realization should not thought and exceeds scope of the present invention.
The method of describing in conjunction with embodiment disclosed herein or the step of algorithm can directly use the software module of hardware, processor execution, and perhaps the combination of the two is implemented.Software module can place the storage medium of any other form known in random asccess memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or the technical field.
To the above-mentioned explanation of the disclosed embodiments, make this area professional and technical personnel can realize or use the present invention.Multiple modification to these embodiment will be apparent concerning those skilled in the art, and defined General Principle can realize under the situation that does not break away from the spirit or scope of the present invention in other embodiments herein.Therefore, the present invention will can not be restricted to these embodiment shown in this article, but will meet the wideest scope consistent with principle disclosed herein and features of novelty.
Claims (4)
1. a digital gain control circuit DAGC is characterized in that, comprising: instantaneous power calculator, loop filter, gain accumulator, gain accumulated value processing module and control module, wherein:
Described instantaneous power calculator be used for to calculate the instantaneous output of DAGC output, and described instantaneous output is inputed to described loop filter;
Described loop filter is used for described instantaneous output is carried out filtering, and filtered instantaneous output is inputed to described gain accumulator;
Described gain accumulator is used for calculating current gain accumulated value according to described filtered instantaneous output, and described gain accumulated value is inputed to described gain accumulated value processing module;
Described gain accumulated value processing module, be used for receiving described gain accumulated value, if described gain accumulated value exceeds default gain ranging, gain accumulated value after the bit of representing described gain accumulated value carried out the step-by-step negate and add preset value and obtain handling, gain accumulated value after the described processing is exported to the input of described DAGC as the gain application value, so that described input is to the input signal adjustment that gains, wherein, described preset value is used for described gain accumulated value is adjusted in the described default gain ranging;
The input of described control module links to each other with described DAGC input, output links to each other with described gain accumulator with described loop filter, described control module is used for obtaining the input power of described DAGC input, and when described input power exceeded default power bracket, described DAGC resetted.
2. DAGC according to claim 1 is characterized in that, described gain accumulated value processing module comprises:
Gain accumulated value acquiring unit is used for receiving described gain accumulated value;
Overflow processing unit, exceed default gain ranging if be used for described gain accumulated value, gain accumulated value after the bit of representing described gain accumulated value carried out the step-by-step negate and add preset value and obtain handling, with the gain accumulated value after the described processing as the gain application value;
Output unit is used for the described gain application value of output to the input of described DAGC, so that described input is to the input signal adjustment that gains.
3. DAGC according to claim 2, it is characterized in that, the described processing unit that overflows comprises: the signal generator of inverter, adder and the described preset value of generation, the input of described inverter links to each other with the output of described gain accumulated value acquiring unit, the output of described inverter links to each other with the first input end of described adder, the output of described signal generator links to each other with second input of described adder, and the output of described adder links to each other with the input of described output unit.
4. gain control method is applied to it is characterized in that among the digital gain control circuit DAGC that this method comprises:
Control module is obtained the input power of described DAGC input, and when described input power exceeded default power bracket, described DAGC resetted;
Gain accumulated value processing module receives the current gain accumulated value of described gain accumulator computes from DAGC circuit gain accumulator;
If described gain accumulated value exceeds default gain ranging, gain accumulated value after the bit of representing described gain accumulated value carried out the step-by-step negate and add preset value and obtain handling, with the gain accumulated value after the described processing as the gain application value, wherein, described preset value is used for described gain accumulated value is adjusted in the described default gain ranging;
Export described gain application value to the input of described DAGC, so that described input is to the input signal adjustment that gains.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101257319A (en) * | 2008-04-09 | 2008-09-03 | 浙江大学 | Complete digital logarithm automatic gain control device and method |
| CN101692601A (en) * | 2009-06-03 | 2010-04-07 | 北京中星微电子有限公司 | Automatic gain control device and audio control system comprising same |
| CN101826855A (en) * | 2010-05-12 | 2010-09-08 | 四川和芯微电子股份有限公司 | Signal regulation system having summing-delta regulator |
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| US7701371B2 (en) * | 2006-04-04 | 2010-04-20 | Qualcomm Incorporated | Digital gain computation for automatic gain control |
| JP4436854B2 (en) * | 2007-06-21 | 2010-03-24 | シャープ株式会社 | Automatic gain control circuit, receiver, automatic gain control method, automatic gain control program, and recording medium recording the program |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101257319A (en) * | 2008-04-09 | 2008-09-03 | 浙江大学 | Complete digital logarithm automatic gain control device and method |
| CN101692601A (en) * | 2009-06-03 | 2010-04-07 | 北京中星微电子有限公司 | Automatic gain control device and audio control system comprising same |
| CN101826855A (en) * | 2010-05-12 | 2010-09-08 | 四川和芯微电子股份有限公司 | Signal regulation system having summing-delta regulator |
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