CN102185807A - Equalizer and equalization signal method - Google Patents
Equalizer and equalization signal method Download PDFInfo
- Publication number
- CN102185807A CN102185807A CN2011100925193A CN201110092519A CN102185807A CN 102185807 A CN102185807 A CN 102185807A CN 2011100925193 A CN2011100925193 A CN 2011100925193A CN 201110092519 A CN201110092519 A CN 201110092519A CN 102185807 A CN102185807 A CN 102185807A
- Authority
- CN
- China
- Prior art keywords
- oversampling
- equalizer
- direct current
- clock pulse
- terms
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
The invention discloses an equalizer and an equalization signal method. The equalizer comprises a super-sampling logical unit, a DC setting unit and an AC setting unit. The super-sampling action of the data from a channel is executed according to a super-sampling clock pulse by the super-sampling logical unit and a plurality of DC items and a plurality of AC items are generated. A plurality of DC items and a plurality of AC items are outputted related to an output clock pulse according to the output clock pulse. A plurality of DC items are inputted according to a first setting time by the DC setting unit and the DC setting of the equalizer is adjusted. A plurality of AC items are inputted according to a first setting time by the AC setting unit and the AC setting of the equalizer is adjusted.
Description
Technical field
The present invention relates to the method for a kind of equalizer and equalizing signal, refer to a kind of DC terms that produces according to the oversampling logical block especially and exchanges, with the direct current setting of adjusting equalizer and exchange the equalizer of setting and the method for equalizing signal.
Background technology
Please refer to Fig. 1, Fig. 1 is the schematic diagram of DESCRIPTION OF THE PRIOR ART equalizer 100.Equalizer 100 comprises a direct current estimation unit 102, a direct current logic processor 104, exchanges an estimation unit 106 and an alternating current logic processor 108.After equalizer 100 receives data from a channel, by the data that receive from channel in direct current estimation unit 102 average one first scheduled time T1, to produce a direct current parameter, and the data that receive from channel in 106 couples first scheduled time T1 of interchange estimation unit are carried out a discrete cosine transform (discrete cosine transform, DCT) and discrete sine conversion (discrete sine transform, DST), to produce an alternating-current parameter.DCL processor 104 is coupled to direct current estimation unit 102, and according to a plurality of dc parameters in one second scheduled time T2, judges whether to adjust the direct current setting of equalizer 100.Alternating current logic processor 108 is coupled to and exchanges estimation unit 106, and according to a plurality of alternating-current parameters in second scheduled time T2, judges whether to adjust the interchange setting of equalizer 100.
In the prior art, the operation principle of equalizer 100 is pinned based on clock pulse data return signal phase place, but actual conditions have promptly received the data from channel for when clock pulse data return signal phase place is not pinned as yet.In addition, direct current estimation unit 102 with exchange estimation unit 106 and must be operated at the data frequency that is received, for example the frequency of received data is 10GHz, then direct current estimation unit 102 with exchange estimation unit 106 and also must be operated at 10GHz.In addition, if just the data that received within a period of time all are the interchange values, then direct current estimation unit 102 can think that D. C. value is not enough in the data that received, and sets to such an extent as to tendency increases the direct current of equalizer 100.But actual conditions may be that the data of having only that time to receive all are the interchange values, and other periods are really not so, cause the direct current of equalizer 100 to set mistake.
Summary of the invention
One embodiment of the invention provide a kind of equalizer.This equalizer comprises an oversampling logical block, a direct current setup unit and exchanges setup unit.This oversampling logical block is in order to according to an oversampling (oversampling) clock pulse, to carry out oversampling action from the data of a channel, to produce a plurality of DC terms (DC term) and a plurality of interchange (AC term), and according to an output clock pulse, a plurality of DC terms that output is relevant with this output clock pulse from these a plurality of DC terms and from this a plurality of exchanges, export a plurality of items that exchange of being correlated with this output clock pulse; This direct current setup unit in order to according to a plurality of DC terms of being imported by this oversampling logical block in one first scheduled time, is adjusted a direct current of this equalizer and is set; And this interchange setup unit, in order to according to a plurality of interchanges items of importing by this oversampling logical block in this first scheduled time, adjust an interchange of this equalizer and set.
Another embodiment of the present invention provides a kind of method of equalizing signal.This method comprises according to an oversampling clock pulse, to carry out oversampling action from the data of a channel, to produce a plurality of DC terms and a plurality of interchange item; According to an output clock pulse, a plurality of DC terms to direct current setup units that output is relevant with this output clock pulse from these a plurality of DC terms and from this a plurality of exchanges, export a plurality of Xiang Zhiyi of interchange interchange setup units of being correlated with this output clock pulse; Be pursuant to a plurality of DC terms of output in one first scheduled time, adjust the direct current of an equalizer and set; And be pursuant to a plurality of interchanges items of exporting in this first scheduled time, adjust the interchange of this equalizer and set.
The method of a kind of equalizer provided by the present invention and equalizing signal is moved to carry out an oversampling from the data of a channel according to an oversampling logical block, to produce a plurality of DC terms and a plurality of interchange item.And this oversampling logical block can be according to an output clock pulse, and a plurality of Xiang Zhiyi that exchange that a plurality of DC terms to direct current setup units that output is relevant with this output clock pulse and output are relevant with this output clock pulse exchange setup unit.Therefore, equalizer of the present invention needn't operate situation about being lockable in clock pulse data return signal phase place, and this direct current estimation unit exchanges estimation unit and need not operate in a high-frequency clock pulse with this.In addition, this oversampling logical block is to carry out this oversampling action from the data of this channel, to produce a plurality of DC terms and a plurality of interchange item.Therefore, all be to exchange or the situation of DC terms for the data that received within a certain period, the present invention keeps last time the direct current of equalizer and sets or exchange and set, and sets or exchange the situation of the mistake of setting so as to the direct current that improves equalizer.
Description of drawings
Fig. 1 is the schematic diagram of DESCRIPTION OF THE PRIOR ART equalizer;
Fig. 2 is the schematic diagram of one embodiment of the invention explanation equalizer;
Fig. 3 A is explanation oversampling logical block DC terms of being exported and the schematic diagram that exchanges item with Fig. 3 B;
Fig. 4 illustrates the oversampling logical block according to the output clock pulse, DC terms that output is correlated with the output clock pulse and the schematic diagram that exchanges item;
Fig. 5 is the flow chart of the method for another embodiment of the present invention explanation equalizing signal.
Wherein, Reference numeral
100,200 equalizers, 102,2042 direct current estimation units
104,2044 DCL processors 106,2062 exchange estimation unit
108,2064 alternating current logic processors, 202 oversampling logical blocks
204 direct current setup units 206 exchange setup unit
The 500-512 step
Embodiment
Please refer to Fig. 2, Fig. 2 is the schematic diagram of one embodiment of the invention explanation equalizer 200.Equalizer 200 comprises an oversampling logical block 202, a direct current setup unit 204 and exchanges setup unit 206.Oversampling logical block 202 is in order to according to an oversampling (over sampling) clock pulse Cov, to carry out oversampling action from the data of a channel, to produce a plurality of DC terms (DC term) and a plurality of interchange (AC term), and according to an output clock pulse Co, a plurality of DC terms that output is relevant with output clock pulse Co from a plurality of DC terms and output a plurality of the exchange items relevant from a plurality of exchanges with output clock pulse Co.In addition, the frequency of oversampling clock pulse Cov must be greater than two times of data frequency.In the present embodiment, oversampling clock pulse Cov is 10GHz, and data frequency is 2.5GHz, is 10GHz but the present invention is not limited to oversampling clock pulse Cov, and data frequency is 2.5GHz.
Please refer to Fig. 3 A and Fig. 3 B, Fig. 3 A is explanation oversampling logical block 202 DC terms of being exported and the schematic diagrames that exchange item with Fig. 3 B.Because oversampling clock pulse Cov is 10GHz and data frequency is 2.5GHz, so the DC terms that oversampling logical block 202 is exported must be 4 bit term (10GHz/2.5GHz=4) with exchanging item.When 4 bit term are not " 0 " or entirely when " 1 " entirely, then oversampling logical block 202 these 4 bit term of record are one to exchange.As shown in Figure 3A, 4 bit term are " 0111 ", and then oversampling logical block 202 record 4 bit term " 0111 " are an interchange item.In like manner, when 4 bit term are " 0 " or full during for " 1 " entirely, then oversampling logical block 202 these 4 bit term of record are a DC terms.Shown in Fig. 3 B, 4 bit term are " 1111 ", and then oversampling logical block 202 record 4 bit term " 1111 " are a DC terms.
Please refer to Fig. 4, Fig. 4 illustrates oversampling logical block 202 according to output clock pulse Co, DC terms that output is correlated with the output clock pulse and the schematic diagram that exchanges item.Oversampling logical block 202 is constantly utilized oversampling (over sampling) clock pulse Cov, to carry out oversampling action from the data of a channel, to produce a plurality of DC terms and a plurality of interchange item.But only when exporting clock pulse Co rising edge, output is 4 bit term of record (might be DC terms, also might be to exchange item) recently for oversampling logical block 202.But the present invention is not limited to export clock pulse Co rising edge, and oversampling logical block 202 also can be when output clock pulse Co trailing edge, and output is 4 bit term of record recently.Therefore, oversampling logical block 202 can be according to output clock pulse Co, output a plurality of DC terms relevant with output clock pulse Co to direct current setup unit 204 and output a plurality of exchanges items relevant with output clock pulse Co to exchanging setup unit 206.
Direct current setup unit 204 comprises a direct current estimation unit 2042 and a direct current logic processor 2044.Direct current estimation unit 2042 is coupled to oversampling logical block 202, in order to a plurality of DC terms of being imported by oversampling logical block 202 in average first scheduled time T1, to produce a direct current parameter DCP; DCL processor 2044 is coupled to direct current estimation unit 2042, in order to according to a plurality of dc parameter DCP in second scheduled time T2, judges whether the D. C. value of equalizer 200 is enough, adjusts a direct current of equalizer 200 according to this and sets DCS.Exchange setup unit 206 and comprise an interchange estimation unit 2062 and an alternating current logic processor 2064.Exchange estimation unit 2062 and be coupled to oversampling logical block 202, in order to a plurality of interchanges items to importing by oversampling logical block 202 in first scheduled time T1, carry out a discrete cosine transform (discrete cosine transform, DCT) and discrete sine conversion (discrete sine transform, DST), to produce an alternating-current parameter ACP; Alternating current logic processor 2064 is coupled to and exchanges estimation unit 2062, in order to according to a plurality of alternating-current parameter ACP in second scheduled time T2, judges whether the interchange value of equalizer 200 is enough, adjusts the interchange of equalizer 200 according to this and sets ACS.
Please refer to Fig. 5, Fig. 5 is the flow chart of the method for another embodiment of the present invention explanation equalizing signal.The method of Fig. 5 is utilized equalizer 200 explanations of Fig. 2, and detailed step is as follows:
Step 500: beginning;
Step 502: according to oversampling clock pulse Cov, to carrying out the oversampling action, to produce a plurality of DC terms and a plurality of interchange item from the data of a channel;
Step 504: according to output clock pulse Co, a plurality of DC terms that output is relevant with output clock pulse Co from a plurality of DC terms are to direct current setup unit 204, carry out step 506, and a plurality of items that exchange that output is relevant with output clock pulse Co from a plurality of interchange items carry out steps 510 to exchanging setup unit 206;
Step 506: a plurality of DC terms of importing by oversampling logical block 202 in direct current estimation unit 2042 average first scheduled time T1, to produce dc parameter DCP;
Step 508: DCL processor 2044 is adjusted the direct current of equalizer 200 and is set DCS, rebound step 502 according to a plurality of dc parameter DCP that receive in second scheduled time T2;
Step 510: exchange a plurality of interchanges items of importing by oversampling logical block 202 in 2062 couples first scheduled time T1 of estimation unit, carry out the conversion of discrete cosine transform and discrete sine, to produce alternating-current parameter ACP;
Step 512: alternating current logic processor 2064 is adjusted the interchange of equalizer 200 and is set ACS, rebound step 502 according to a plurality of alternating-current parameter ACP that receive in second scheduled time T2.
In step 502, oversampling logical block 202 is according to oversampling clock pulse Cov, to carrying out the oversampling action from the data of a channel, to produce a plurality of DC terms and a plurality of interchange item.The frequency of oversampling clock pulse Cov must be greater than two times of data frequency.In the embodiment of Fig. 5, oversampling clock pulse Cov is 10GHz, and data frequency is 2.5GHz, is 10GHz but the present invention is not limited to oversampling clock pulse Cov, and data frequency is 2.5GHz.In step 504, oversampling logical block 202 can be according to rising edge or the trailing edge of output clock pulse Co, output a plurality of DC terms relevant with output clock pulse Co to direct current setup unit 204 and output a plurality of exchanges items relevant with output clock pulse Co to exchanging setup unit 206.In step 508, DCL processor 2044 judges according to a plurality of dc parameter DCP in second scheduled time T2 whether the D. C. value of equalizer 200 is enough, adjusts the direct current of equalizer 200 according to this and sets DCS.In step 512, alternating current logic processor 2064 judges according to a plurality of alternating-current parameter ACP in second scheduled time T2 whether the interchange value of equalizer 200 is enough, adjusts the interchange of equalizer 200 according to this and sets ACS.
In sum, the method for equalizer provided by the present invention and equalizing signal is moved to carrying out oversampling from the data of a channel according to the oversampling logical block, to produce a plurality of DC terms and a plurality of interchange item.And the oversampling logical block can be according to the output clock pulse, output a plurality of DC terms relevant with the output clock pulse to direct current setup unit and output a plurality of exchanges items relevant with the output clock pulse to exchanging setup unit.Therefore, equalizer of the present invention needn't operate situation about being lockable in clock pulse data return signal phase place, and the direct current estimation unit with exchange estimation unit and need not operate in high-frequency clock pulse.In addition, the oversampling logical block to produce a plurality of DC terms and a plurality of interchange item, is not as direct D. C. value and the interchange value of obtaining from data of prior art to carrying out the oversampling action from the data of a channel.Therefore, all be the situation of interchange item or DC terms for the data that received within a certain period, the present invention keeps last time the direct current setting or the interchange of equalizer and sets, so as to improving the mistake that prior art causes the direct current setting or the interchange setting of equalizer.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.
Claims (8)
1. an equalizer is characterized in that, comprises:
One oversampling logical block, in order to according to an oversampling clock pulse, to carry out oversampling action from the data of a channel, to produce a plurality of DC terms and a plurality of interchange item, and according to an output clock pulse, a plurality of DC terms that output is relevant with this output clock pulse from these a plurality of DC terms and from this a plurality of exchanges, export a plurality of items that exchange of being correlated with this output clock pulse;
One direct current setup unit in order to according to a plurality of DC terms of being imported by this oversampling logical block in one first scheduled time, is adjusted a direct current of this equalizer and is set; And
One exchanges setup unit, in order to according to a plurality of interchanges items of being imported by this oversampling logical block in this first scheduled time, adjusts one of this equalizer and exchanges setting.
2. equalizer according to claim 1 is characterized in that, this direct current setup unit comprises:
One direct current estimation unit is coupled to this oversampling logical block, in order to a plurality of DC terms of being imported by this oversampling logical block in average this first scheduled time, to produce a direct current parameter; And
One direct current logic processor is coupled to this direct current estimation unit, in order to according to a plurality of dc parameters, adjusts this direct current and sets.
3. equalizer according to claim 1 is characterized in that, this interchange setup unit comprises:
One exchanges estimation unit, is coupled to this oversampling logical block, in order to a plurality of interchanges items to being imported by this oversampling logical block in this first scheduled time, carries out the conversion of a discrete cosine transform and a discrete sine, to produce an alternating-current parameter; And
One alternating current logic processor is coupled to this interchange estimation unit, in order to according to a plurality of these alternating-current parameters, adjusts this interchange and sets.
4. equalizer according to claim 1 is characterized in that, the frequency of this oversampling clock pulse is greater than two times of this data frequency.
5. the method for an equalizing signal is characterized in that, comprises:
According to an oversampling clock pulse, to carry out oversampling action from the data of a channel, to produce a plurality of DC terms and a plurality of interchange item;
According to an output clock pulse, a plurality of DC terms to direct current setup units that output is relevant with this output clock pulse from these a plurality of DC terms and from this a plurality of exchanges, export a plurality of Xiang Zhiyi of interchange interchange setup units of being correlated with this output clock pulse;
Be pursuant to a plurality of DC terms of output in one first scheduled time, adjust the direct current of an equalizer and set; And
Be pursuant to a plurality of interchanges items of output in this first scheduled time, adjust the interchange of this equalizer and set.
6. method according to claim 5 is characterized in that, is pursuant to a plurality of DC terms of output in this first scheduled time, and the direct current setting of adjusting this equalizer comprises:
Average a plurality of DC terms of importing in this first scheduled time are to produce a direct current parameter; And
According to a plurality of dc parameters, adjust this direct current and set.
7. method according to claim 5 is characterized in that, is pursuant to a plurality of interchanges items of output in this first scheduled time, and the interchange setting of adjusting this equalizer comprises:
To these a plurality of interchanges items in this first scheduled time, carry out the conversion of a discrete cosine transform and a discrete sine, to produce an alternating-current parameter; And
According to a plurality of alternating-current parameters, adjust this interchange and set.
8. method according to claim 5 is characterized in that, the frequency of this oversampling clock pulse is greater than two times of this data frequency.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US35002910P | 2010-06-01 | 2010-06-01 | |
| US61/350,029 | 2010-06-01 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102185807A true CN102185807A (en) | 2011-09-14 |
| CN102185807B CN102185807B (en) | 2014-07-02 |
Family
ID=44571878
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110092519.3A Active CN102185807B (en) | 2010-06-01 | 2011-04-08 | Equalizer and equalization signal method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102185807B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006106473A2 (en) * | 2005-04-06 | 2006-10-12 | Nxp B.V. | Multi-user equalization method and device for wireless communication system |
| CN101019393A (en) * | 2004-07-12 | 2007-08-15 | 艾利森电话股份有限公司 | Equalizers for multi-branch receiver |
| CN101310493A (en) * | 2005-11-15 | 2008-11-19 | 高通股份有限公司 | Equalizer for a receiver in a wireless communication system |
-
2011
- 2011-04-08 CN CN201110092519.3A patent/CN102185807B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101019393A (en) * | 2004-07-12 | 2007-08-15 | 艾利森电话股份有限公司 | Equalizers for multi-branch receiver |
| WO2006106473A2 (en) * | 2005-04-06 | 2006-10-12 | Nxp B.V. | Multi-user equalization method and device for wireless communication system |
| CN101310493A (en) * | 2005-11-15 | 2008-11-19 | 高通股份有限公司 | Equalizer for a receiver in a wireless communication system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102185807B (en) | 2014-07-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8489037B2 (en) | Power amplifying apparatus with bandwidth limitation processing on variable power supply | |
| KR102207599B1 (en) | Block-based crest factor reduction (cfr) | |
| CN101232477B (en) | Method and device for compensating baseline dissociation as well as Ethernet circuit device | |
| CN103843296B (en) | Receiving device of ofdm communication system and method for alleviating phase noise thereof | |
| CN101827047B (en) | Frequency domain interference signal eliminating method and device | |
| US8582635B2 (en) | Sparse and reconfigurable floating tap feed forward equalization | |
| CN103916164B (en) | Process the method for the baseband signal in direct current suppression system, system and smart card | |
| JP6846120B2 (en) | Clock recovery devices and methods and programs for executing clock recovery methods | |
| CN102185807B (en) | Equalizer and equalization signal method | |
| CN101162920A (en) | Decision feedback equalizer and implementing method thereof | |
| EP3024141B1 (en) | Interpolator systems and methods | |
| US20150098496A1 (en) | Method and associated processing module for interconnection system | |
| US20140025350A1 (en) | Statistical modeling based on bit-accurate simulation of an electronic device | |
| US9628060B2 (en) | Semiconductor device and operating method thereof | |
| CN101510866A (en) | Method, apparatus and transmitter for restraining signal peak-equal power ratio | |
| CN110581711A (en) | Equalizer and transmitter including the same | |
| US9112763B1 (en) | Device, system and method for bi-phase modulation decoding | |
| JP7035913B2 (en) | Peak suppression circuit, peak suppression method, and transmitter | |
| CN103873402B (en) | System and method for high-performance coherence peak Shrinkage estimation | |
| CN105245480B (en) | digital signal processing method and device | |
| CN110071883A (en) | Microwave pre-distortion parameters estimation method, device and equipment, storage medium | |
| CN103338058A (en) | Multi-frequency programmable matching filter | |
| WO2011048555A1 (en) | A method and a system for signal processing | |
| US8330535B2 (en) | Equalizer and method of equalizing signals | |
| TWI425765B (en) | Equalizer and method of equalizing signals |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20160203 Address after: Taipei City, Taiwan, China Patentee after: ETRON TECHNOLOGY, INC. Address before: China Taiwan Hsinchu Science Park, Hsinchu Patentee before: Etron Technology, Inc. |