TWI425765B - Equalizer and method of equalizing signals - Google Patents

Equalizer and method of equalizing signals Download PDF

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TWI425765B
TWI425765B TW99147195A TW99147195A TWI425765B TW I425765 B TWI425765 B TW I425765B TW 99147195 A TW99147195 A TW 99147195A TW 99147195 A TW99147195 A TW 99147195A TW I425765 B TWI425765 B TW I425765B
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setting
equalizer
items
oversampling
unit
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TW99147195A
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TW201145818A (en
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Kuo Cyuan Kuo
Yu Chiun Lin
Ming Kia Chen
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Etron Technology Inc
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等化器與等化訊號的方法Equalizer and equalization signal method

本發明係有關於一種等化器與等化訊號的方法，尤指一種根據超取樣邏輯單元產生的直流項和交流項，以調整等化器的直流設定與交流設定的等化器與等化訊號的方法。The invention relates to a method for equalizing and equalizing signals, in particular to a DC term and an AC term generated by an oversampling logic unit, to adjust an equalizer and equalization of the DC setting and AC setting of the equalizer. The method of the signal.

請參照第1圖，第1圖係為先前技術說明等化器100的示意圖。等化器100包含一直流估計單元102、一直流邏輯處理器104、一交流估計單元106及一交流邏輯處理器108。當等化器100從一頻道接收資料後，由直流估計單元102平均一第一預定時間T1內從頻道接收的資料，以產生一直流參數，以及交流估計單元106對第一預定時間T1內從頻道接收的資料執行一離散餘弦轉換(discrete cosine transform,DCT)及一離散正弦轉換(discrete sine transform,DST)，以產生一交流參數。直流邏輯處理器104係耦接於直流估計單元102，並根據一第二預定時間T2內的複數個直流參數，判斷是否調整等化器100的直流設定。交流邏輯處理器108係耦接於交流估計單元106，並根據第二預定時間T2內的複數個交流參數，判斷是否調整等化器100的交流設定。Please refer to FIG. 1 , which is a schematic diagram of the prior art equalizer 100 . The equalizer 100 includes a DC current estimation unit 102, a DC logic processor 104, an AC estimation unit 106, and an AC logic processor 108. After the equalizer 100 receives the data from a channel, the DC estimation unit 102 averages the data received from the channel within a first predetermined time T1 to generate a DC parameter, and the AC estimation unit 106 for the first predetermined time T1. The data received by the channel performs a discrete cosine transform (DCT) and a discrete sine transform (DST) to generate an alternating current parameter. The DC logic processor 104 is coupled to the DC estimation unit 102 and determines whether to adjust the DC setting of the equalizer 100 according to a plurality of DC parameters in a second predetermined time T2. The AC logic processor 108 is coupled to the AC estimation unit 106 and determines whether to adjust the AC setting of the equalizer 100 according to the plurality of AC parameters in the second predetermined time T2.

在先前技術中，等化器100的運作原理係基於時脈資料回復訊號相位鎖住，但實際情況係在時脈資料回復訊號相位尚未鎖住時，即已接收來自頻道的資料。另外，直流估計單元102和交流估計單元106必須操作在所接收的資料的頻率，例如所接收資料的頻率為10GHz，則直流估計單元102和交流估計單元106亦必須操作在10GHz。此外，如果剛好一段時間之內所接收的資料都是交流值，則直流估計單元102會認為所接收的資料中直流值不夠，以致於傾向增加等化器100的直流設定。但實際情況可能是只有那段時間所接收的資料都是交流值，而其他時段並非如此，造成等化器100的直流設定錯誤。In the prior art, the operating principle of the equalizer 100 is based on the clock signal recovery signal phase lock, but the actual situation is that when the clock data reply signal phase has not been locked, the data from the channel has been received. In addition, the DC estimation unit 102 and the AC estimation unit 106 must operate at the frequency of the received data, for example, the frequency of the received data is 10 GHz, and the DC estimation unit 102 and the AC estimation unit 106 must also operate at 10 GHz. In addition, if the received data is an AC value for a certain period of time, the DC estimation unit 102 considers that the DC value in the received data is insufficient, so as to tend to increase the DC setting of the equalizer 100. However, the actual situation may be that only the data received during that time is an AC value, and other time periods are not the same, causing the DC setting of the equalizer 100 to be incorrect.

本發明的一實施例提供一種等化器。該等化器包含一超取樣邏輯單元、一直流設定單元及一交流設定單元。該超取樣邏輯單元係用以根據一超取樣(oversampling)時脈，對來自一頻道的資料執行一超取樣動作，以產生複數個直流項(DC term)及複數個交流項(AC term)，以及根據一輸出時脈，從該複數個直流項中輸出和該輸出時脈相關的複數個直流項及從該複數個交流項中輸出和該輸出時脈相關的複數個交流項；該直流設定單元，用以根據一第一預定時間內由該超取樣邏輯單元輸入之複數個直流項，調整該等化器的一直流設定；及該交流設定單元，用以根據該第一預定時間內由該超取樣邏輯單元輸入之複數個交流項，調整該等化器的一交流設定。An embodiment of the invention provides an equalizer. The equalizer includes an oversampling logic unit, a DC current setting unit, and an AC setting unit. The oversampling logic unit is configured to perform an oversampling operation on data from a channel according to an oversampling clock to generate a plurality of DC terms and a plurality of AC terms. And outputting, according to an output clock, a plurality of DC items related to the output clock from the plurality of DC items and outputting a plurality of AC items related to the output clock from the plurality of AC items; the DC setting a unit, configured to adjust a DC current setting of the equalizer according to a plurality of DC items input by the oversampling logic unit in a first predetermined time; and the AC setting unit is configured to be used according to the first predetermined time The oversampling logic unit inputs a plurality of alternating items to adjust an alternating current setting of the equalizer.

本發明的另一實施例提供一種等化訊號的方法。該方法包含根據一超取樣時脈，對來自一頻道的資料執行一超取樣動作，以產生複數個直流項及複數個交流項；根據一輸出時脈，從該複數個直流項中輸出和該輸出時脈相關的複數個直流項至一直流設定單元及從該複數個交流項中輸出和該輸出時脈相關的複數個交流項至一交流設定單元；根據於一第一預定時間內輸出之複數個直流項，調整一等化器的直流設定；及根據於該第一預定時間內輸出之複數個交流項，調整該等化器的交流設定。Another embodiment of the present invention provides a method of equalizing a signal. The method includes performing an oversampling operation on data from a channel according to an oversampling clock to generate a plurality of DC items and a plurality of AC items; and outputting from the plurality of DC items according to an output clock Outputting a plurality of DC items related to the clock to the DC setting unit and outputting a plurality of AC items related to the output clock from the plurality of AC items to an AC setting unit; outputting according to a first predetermined time a plurality of DC items, adjusting a DC setting of the equalizer; and adjusting an AC setting of the equalizer according to the plurality of AC items outputted in the first predetermined time.

本發明所提供的一種等化器和等化訊號的方法，係根據一超取樣邏輯單元對來自一頻道的資料執行一超取樣動作，以產生複數個直流項及複數個交流項。且該超取樣邏輯單元可根據一輸出時脈，輸出和該輸出時脈相關的複數個直流項至一直流設定單元及輸出和該輸出時脈相關的複數個交流項至一交流設定單元。因此，本發明的等化器不必運作在時脈資料回復訊號相位被鎖住的情況，且該直流估計單元和該交流估計單元不需操作在一高頻時脈。另外，該超取樣邏輯單元係對來自該頻道的資料執行該超取樣動作，以產生複數個直流項及複數個交流項。因此，對於某一段時間之內所接收的資料都是交流項或直流項的情況，本發明係以維持前次等化器的直流設定或交流設定，藉以改善等化器的直流設定或交流設定的錯誤的情形。An equalizer and equalization signal method provided by the present invention performs an oversampling operation on data from a channel according to an oversampling logic unit to generate a plurality of DC items and a plurality of AC items. And the oversampling logic unit outputs, according to an output clock, a plurality of DC items related to the output clock to the DC setting unit and outputs a plurality of AC items related to the output clock to an AC setting unit. Therefore, the equalizer of the present invention does not have to operate in the case where the clock data recovery signal phase is locked, and the DC estimation unit and the AC estimation unit do not need to operate at a high frequency clock. Additionally, the oversampling logic unit performs the oversampling action on data from the channel to generate a plurality of DC terms and a plurality of AC terms. Therefore, in the case that the data received during a certain period of time is an AC item or a DC item, the present invention maintains the DC setting or AC setting of the previous equalizer to improve the DC setting or AC setting of the equalizer. The wrong situation.

請參照第2圖，第2圖係為本發明的一實施例說明等化器200的示意圖。等化器200包含一超取樣邏輯單元202、一直流設定單元204及一交流設定單元206。超取樣邏輯單元202係用以根據一超取樣(over sampling)時脈Cov，對來自一頻道的資料執行一超取樣動作，以產生複數個直流項(DC term)及複數個交流項(AC term)，以及根據一輸出時脈Co，從複數個直流項中輸出和輸出時脈Co相關的複數個直流項及從複數個交流項中輸出和輸出時脈Co相關的複數個交流項。另外，超取樣時脈Cov的頻率必須大於資料的頻率的二倍。在本實施例中，超取樣時脈Cov係為10GHz，資料的頻率係為2.5GHz，但本發明並不受限於超取樣時脈Cov係為10GHz，資料的頻率係為2.5GHz。Please refer to FIG. 2, which is a schematic diagram of the equalizer 200 according to an embodiment of the present invention. The equalizer 200 includes an oversampling logic unit 202, a DC current setting unit 204, and an AC setting unit 206. The oversampling logic unit 202 is configured to perform an oversampling operation on data from a channel according to an over sampling clock Cov to generate a plurality of DC terms and a plurality of AC terms (AC term). And, according to an output clock Co, outputting and outputting a plurality of DC terms related to the clock Co from the plurality of DC terms and a plurality of AC terms related to outputting and outputting the clock Co from the plurality of AC terms. In addition, the frequency of the oversampled clock Cov must be greater than twice the frequency of the data. In the present embodiment, the oversampling clock Cov is 10 GHz, and the frequency of the data is 2.5 GHz. However, the present invention is not limited to the supersampling clock Cov system being 10 GHz, and the frequency of the data is 2.5 GHz.

請參照第3A圖和第3B圖，第3A圖和第3B圖係說明超取樣邏輯單元202所輸出的直流項和交流項的示意圖。因為超取樣時脈Cov為10GHz以及資料的頻率為2.5GHz，所以超取樣邏輯單元202所輸出的直流項和交流項必須是4位元項(10GHz/2.5GHz=4)。當4位元項不全為“0”或不全為“1”時，則超取樣邏輯單元202記錄此4位元項為一交流項。如第3A圖所示，4位元項係為“0111”，則超取樣邏輯單元202記錄4位元項“0111”為一交流項。同理，當4位元項全為“0”或全為“1”時，則超取樣邏輯單元202記錄此4位元項為一直流項。如第3B圖所示，4位元項係為“1111”，則超取樣邏輯單元202記錄4位元項“1111”為一直流項。Please refer to FIG. 3A and FIG. 3B . FIG. 3A and FIG. 3B are schematic diagrams illustrating the DC term and the AC term output by the oversampling logic unit 202. Since the oversampling clock Cov is 10 GHz and the frequency of the data is 2.5 GHz, the DC term and the AC term output by the oversampling logic unit 202 must be a 4-bit term (10 GHz / 2.5 GHz = 4). When the 4-bit entry is not all "0" or not all "1", the oversampling logic unit 202 records the 4-bit entry as an exchange term. As shown in FIG. 3A, the 4-bit item is "0111", and the oversampling logic unit 202 records the 4-bit item "0111" as an alternating item. Similarly, when the 4-bit item is all "0" or all "1", the oversampling logic unit 202 records the 4-bit item as a DC item. As shown in FIG. 3B, the 4-bit item is "1111", and the oversampling logic unit 202 records the 4-bit item "1111" as a DC item.

請參照第4圖，第4圖係說明超取樣邏輯單元202根據輸出時脈Co，輸出和輸出時脈相關的直流項及交流項的示意圖。超取樣邏輯單元202不斷地利用超取樣(over sampling)時脈Cov，對來自一頻道的資料執行一超取樣動作，以產生複數個直流項及複數個交流項。但超取樣邏輯單元202僅在輸出時脈Co正緣時，輸出最近記錄的4位元項(有可能是直流項，亦有可能是交流項)。但本發明並不受限於輸出時脈Co正緣，超取樣邏輯單元202亦可在輸出時脈Co負緣時，輸出最近記錄的4位元項。因此，超取樣邏輯單元202可根據輸出時脈Co，輸出和輸出時脈Co相關的複數個直流項至直流設定單元204及輸出和輸出時脈Co相關的複數個交流項至交流設定單元206。Referring to FIG. 4, FIG. 4 is a schematic diagram showing the DC term and the AC term related to the output and output clocks of the oversampling logic unit 202 according to the output clock Co. The oversampling logic unit 202 continually utilizes an over sampling clock Cov to perform an oversampling action on data from a channel to generate a plurality of DC terms and a plurality of AC terms. However, the oversampling logic unit 202 outputs the most recently recorded 4-bit item (possibly a DC term or an AC term) only when the clock pulse Co positive edge is output. However, the present invention is not limited to the output clock Co positive edge, and the oversampling logic unit 202 may also output the most recently recorded 4-bit item when the output clock Co is negative. Therefore, the oversampling logic unit 202 can output a plurality of DC terms related to the clock Co to the DC setting unit 204 and the output and output clock Co related to the AC setting unit 206 according to the output clock Co.

直流設定單元204包含一直流估計單元2042及一直流邏輯處理器2044。直流估計單元2042係耦接於超取樣邏輯單元202，用以於平均第一預定時間T1內由超取樣邏輯單元202輸入之複數個直流項，以產生一直流參數DCP；直流邏輯處理器2044係耦接於直流估計單元2042，用以根據第二預定時間T2內的複數個直流參數DCP，判斷等化器200的直流值是否足夠，據以調整等化器200的一直流設定DCS。交流設定單元206包含一交流估計單元2062及一交流邏輯處理器2064。交流估計單元2062係耦接於超取樣邏輯單元202，用以對第一預定時間T1內由超取樣邏輯單元202輸入之複數個交流項，執行一離散餘弦轉換(discrete cosine transform,DCT)及一離散正弦轉換(discrete sine transform,DST)，以產生一交流參數ACP；交流邏輯處理器2064係耦接於交流估計單元2062，用以根據第二預定時間T2內的複數個交流參數ACP，判斷等化器200的交流值是否足夠，據以調整等化器200的交流設定ACS。The DC setting unit 204 includes a DC current estimating unit 2042 and a DC logic processor 2044. The DC estimation unit 2042 is coupled to the oversampling logic unit 202 for averaging a plurality of DC terms input by the oversampling logic unit 202 during the first predetermined time T1 to generate a DC parameter DCP; the DC logic processor 2044 is The DC estimation unit 2042 is configured to determine whether the DC value of the equalizer 200 is sufficient according to the plurality of DC parameters DCP in the second predetermined time T2, and adjust the DCS of the equalizer 200 to adjust the DCS. The AC setting unit 206 includes an AC estimating unit 2062 and an AC logic processor 2064. The AC estimation unit 2062 is coupled to the oversampling logic unit 202 for performing a discrete cosine transform (DCT) and a plurality of AC terms input by the oversampling logic unit 202 during the first predetermined time T1. Discrete sine transform (DST) to generate an AC parameter ACP; the AC logic processor 2064 is coupled to the AC estimation unit 2062 for determining, according to the plurality of AC parameters ACP in the second predetermined time T2, Whether or not the AC value of the chemist 200 is sufficient is adjusted to adjust the AC setting ACS of the equalizer 200.

請參照第5圖，第5圖係為本發明的另一實施例說明等化訊號的方法的流程圖。第5圖之方法係利用第2圖的等化器200說明，詳細步驟如下：步驟500：開始；步驟502：根據超取樣時脈Cov，對來自一頻道的資料執行超取樣動作，以產生複數個直流項及複數個交流項；步驟504：根據輸出時脈Co，從複數個直流項中輸出和輸出時脈Co相關的複數個直流項至直流設定單元204，進行步驟506，及從複數個交流項中輸出和輸出時脈Co相關的複數個交流項至交流設定單元206，進行步驟510；步驟506：直流估計單元2042平均第一預定時間T1內由超取樣邏輯單元202輸入之複數個直流項，以產生直流參數DCP；步驟508：直流邏輯處理器2044根據第二預定時間T2內接收之複數個直流參數DCP，調整等化器200的直流設定DCS，跳回步驟502；步驟510：交流估計單元2062對第一預定時間T1內由超取樣邏輯單元202輸入之複數個交流項，執行離散餘弦轉換及離散正弦轉換，以產生交流參數ACP；步驟512：交流邏輯處理器2064根據第二預定時間T2內接收之複數個交流參數ACP，調整等化器200的交流設定ACS，跳回步驟502。Please refer to FIG. 5. FIG. 5 is a flow chart showing a method for equalizing signals according to another embodiment of the present invention. The method of FIG. 5 is illustrated by the equalizer 200 of FIG. 2, and the detailed steps are as follows: Step 500: Start; Step 502: Perform an oversampling action on data from a channel according to the oversampling clock Cov to generate a complex number a DC term and a plurality of AC terms; Step 504: Output and output a plurality of DC terms related to the clock Co from the plurality of DC terms to the DC setting unit 204 according to the output clock Co, proceed to step 506, and from the plurality of And outputting a plurality of AC items related to the output clock Co to the AC setting unit 206 in the AC term, proceeding to step 510; Step 506: The DC estimating unit 2042 averages the plurality of DCs input by the oversampling logic unit 202 within the first predetermined time T1. And the DC logic processor 2044 adjusts the DC setting DCS of the equalizer 200 according to the plurality of DC parameters DCP received in the second predetermined time T2, and jumps back to step 502; Step 510: AC The estimating unit 2062 performs discrete cosine transform and discrete sine transform on the plurality of alternating entries input by the oversampling logic unit 202 in the first predetermined time T1 to generate a cross Parameters of the ACP; Step 512: the AC receives the plurality of logical processor 2064 according to a second predetermined time T2 alternating current parameter ACP, the AC 200 is set to adjust the equalizer ACS, jumps back to step 502.

在步驟502中，超取樣邏輯單元202根據超取樣時脈Cov，對來自一頻道的資料執行超取樣動作，以產生複數個直流項及複數個交流項。超取樣時脈Cov的頻率必須大於資料的頻率的二倍。在第5圖的實施例中，超取樣時脈Cov係為10GHz，資料的頻率係為2.5GHz，但本發明並不受限於超取樣時脈Cov係為10GHz，資料的頻率係為2.5GHz。在步驟504中，超取樣邏輯單元202可根據輸出時脈Co的正緣或負緣，輸出和輸出時脈Co相關的複數個直流項至直流設定單元204及輸出和輸出時脈Co相關的複數個交流項至交流設定單元206。在步驟508中，直流邏輯處理器2044係根據第二預定時間T2內的複數個直流參數DCP，判斷等化器200的直流值是否足夠，據以調整等化器200的直流設定DCS。在步驟512中，交流邏輯處理器2064係根據第二預定時間T2內的複數個交流參數ACP，判斷等化器200的交流值是否足夠，據以調整等化器200的交流設定ACS。In step 502, the oversampling logic unit 202 performs an oversampling operation on the data from a channel based on the oversampling clock Cov to generate a plurality of DC terms and a plurality of AC items. The frequency of the oversampled clock Cov must be greater than twice the frequency of the data. In the embodiment of Fig. 5, the oversampling clock Cov is 10 GHz, and the frequency of the data is 2.5 GHz, but the present invention is not limited to the supersampling clock Cov system is 10 GHz, and the frequency of the data is 2.5 GHz. . In step 504, the oversampling logic unit 202 may output a plurality of DC terms related to the output clock Co to the DC setting unit 204 and the complex and related output clock Co according to the positive or negative edge of the output clock Co. The exchange item is connected to the exchange setting unit 206. In step 508, the DC logic processor 2044 determines whether the DC value of the equalizer 200 is sufficient according to the plurality of DC parameters DCP in the second predetermined time T2, thereby adjusting the DC setting DCS of the equalizer 200. In step 512, the AC logic processor 2064 determines whether the AC value of the equalizer 200 is sufficient according to the plurality of AC parameters ACP in the second predetermined time T2, thereby adjusting the AC setting ACS of the equalizer 200.

綜上所述，本發明所提供的等化器和等化訊號的方法，係根據超取樣邏輯單元對來自一頻道的資料執行超取樣動作，以產生複數個直流項及複數個交流項。且超取樣邏輯單元可根據輸出時脈，輸出和輸出時脈相關的複數個直流項至直流設定單元及輸出和輸出時脈相關的複數個交流項至交流設定單元。因此，本發明的等化器不必運作在時脈資料回復訊號相位被鎖住的情況，且直流估計單元和交流估計單元不需操作在高頻時脈。另外，超取樣邏輯單元係對來自一頻道的資料執行超取樣動作，以產生複數個直流項及複數個交流項，並非像先前技術一樣直接從資料中得到直流值及交流值。因此，對於某一段時間之內所接收的資料都是交流項或直流項的情況，本發明係以維持前次等化器的直流設定或交流設定，藉以改善先前技術造成等化器的直流設定或交流設定的錯誤。In summary, the equalizer and the equalization signal provided by the present invention perform an oversampling operation on data from a channel according to the oversampling logic unit to generate a plurality of DC items and a plurality of AC items. And the oversampling logic unit can output a plurality of DC items related to the clock related to the DC setting unit and the output and output clock related to the AC setting unit according to the output clock, the output and the output clock. Therefore, the equalizer of the present invention does not have to operate in the case where the clock data recovery signal phase is locked, and the DC estimation unit and the AC estimation unit do not need to operate at the high frequency clock. In addition, the oversampling logic unit performs an oversampling operation on data from a channel to generate a plurality of DC terms and a plurality of AC terms, and does not directly obtain DC values and AC values from the data as in the prior art. Therefore, for the case that the data received during a certain period of time is an AC item or a DC item, the present invention maintains the DC setting or the AC setting of the previous equalizer to improve the DC setting of the equalizer caused by the prior art. Or exchange settings errors.

以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100、200．．．等化器100, 200. . . Equalizer

102、2042．．．直流估計單元102, 2042. . . DC estimation unit

104、2044．．．直流邏輯處理器104, 2044. . . DC logic processor

106、2062．．．交流估計單元106, 2062. . . AC estimation unit

108、2064．．．交流邏輯處理器108, 2064. . . AC logic processor

202．．．超取樣邏輯單元202. . . Oversampling logic unit

204．．．直流設定單元204. . . DC setting unit

206．．．交流設定單元206. . . AC setting unit

500-512．．．步驟500-512. . . step

第1圖係為先前技術說明等化器的示意圖。Figure 1 is a schematic diagram of a prior art equalizer.

第2圖係為本發明的一實施例說明等化器的示意圖。Fig. 2 is a schematic view showing an equalizer according to an embodiment of the present invention.

第3A圖和第3B圖係說明超取樣邏輯單元所輸出的直流項和交流項的示意圖。Figures 3A and 3B are schematic diagrams illustrating DC and AC terms output by the oversampling logic unit.

第4圖係說明超取樣邏輯單元根據輸出時脈，輸出和輸出時脈相關的直流項及交流項的示意圖。Figure 4 is a schematic diagram showing the DC and AC terms of the output and output clocks of the oversampling logic unit based on the output clock.

第5圖係為本發明的另一實施例說明等化訊號的方法的流程圖。Figure 5 is a flow chart showing a method of equalizing a signal according to another embodiment of the present invention.

200．．．等化器200. . . Equalizer

2042．．．直流估計單元2042. . . DC estimation unit

2044．．．直流邏輯處理器2044. . . DC logic processor

2062．．．交流估計單元2062. . . AC estimation unit

2064．．．交流邏輯處理器2064. . . AC logic processor

202．．．超取樣邏輯單元202. . . Oversampling logic unit

204．．．直流設定單元204. . . DC setting unit

206．．．交流設定單元206. . . AC setting unit

Claims (8)

一種等化器，包含：一超取樣邏輯單元，用以根據一超取樣(over sampling)時脈，對來自一頻道的資料執行一超取樣動作，以產生複數個直流項(DC term)及複數個交流項(AC term)，以及根據一輸出時脈，從該複數個直流項中輸出和該輸出時脈相關的複數個直流項及從該複數個交流項中輸出和該輸出時脈相關的複數個交流項；一直流設定單元，用以根據一第一預定時間內由該超取樣邏輯單元輸入之複數個直流項，調整該等化器的一直流設定；及一交流設定單元，用以根據該第一預定時間內由該超取樣邏輯單元輸入之複數個交流項，調整該等化器的一交流設定。An equalizer comprising: an oversampling logic unit for performing an oversampling operation on data from a channel according to an over sampling clock to generate a plurality of DC terms and complex numbers An AC term, and according to an output clock, outputting a plurality of DC terms associated with the output clock from the plurality of DC terms and outputting from the plurality of AC terms and the output clock a plurality of alternating current items; a constant current setting unit configured to adjust a constant current setting of the equalizer according to a plurality of DC items input by the oversampling logic unit in a first predetermined time; and an alternating current setting unit And adjusting an AC setting of the equalizer according to the plurality of AC items input by the oversampling logic unit in the first predetermined time. 如請求項1所述之等化器，其中該直流設定單元包含：一直流估計單元，耦接於該超取樣邏輯單元，用以平均該第一預定時間內由該超取樣邏輯單元輸入之複數個直流項，以產生一直流參數；及一直流邏輯處理器，耦接於該直流估計單元，用以根據複數個直流參數，調整該直流設定。The equalizer of claim 1, wherein the DC setting unit comprises: a DC current estimating unit coupled to the oversampling logic unit for averaging the plurality of inputs by the oversampling logic unit in the first predetermined time a DC term to generate a DC parameter; and a DC logic processor coupled to the DC estimation unit for adjusting the DC setting according to the plurality of DC parameters. 如請求項1所述之等化器，其中該交流設定單元包含：一交流估計單元，耦接於該超取樣邏輯單元，用以對該第一預定時間內由該超取樣邏輯單元輸入之複數個交流項，執行一離散餘弦轉換(discrete cosine transform,DCT)及一離散正弦轉換(discrete sine transform,DST)，以產生一交流參數；及一交流邏輯處理器，耦接於該交流估計單元，用以根據複數個該交流參數，調整該交流設定。The equalizer of claim 1, wherein the AC setting unit comprises: an AC estimating unit coupled to the oversampling logic unit for inputting the plurality of the oversampling logic unit for the first predetermined time a communication term, performing a discrete cosine transform (DCT) and a discrete sine transform (DST) to generate an AC parameter; and an AC logic processor coupled to the AC estimation unit, The method is used to adjust the AC setting according to a plurality of the AC parameters. 如請求項1所述之等化器，其中該超取樣時脈的頻率大於該資料的頻率的二倍。The equalizer of claim 1, wherein the frequency of the oversampled clock is greater than twice the frequency of the data. 一種等化訊號的方法，包含：根據一超取樣時脈，對來自一頻道的資料執行一超取樣動作，以產生複數個直流項及複數個交流項；根據一輸出時脈，從該複數個直流項中輸出和該輸出時脈相關的複數個直流項至一直流設定單元及從該複數個交流項中輸出和該輸出時脈相關的複數個交流項至一交流設定單元；根據於一第一預定時間內輸出之複數個直流項，調整一等化器的直流設定；及根據於該第一預定時間內輸出之複數個交流項，調整該等化器的交流設定。A method for equalizing a signal includes: performing an oversampling operation on data from a channel according to an oversampling clock to generate a plurality of DC items and a plurality of AC items; and according to an output clock, from the plurality of And outputting, in the DC term, a plurality of DC items related to the output clock to the DC setting unit and outputting a plurality of AC items related to the output clock from the plurality of AC items to an AC setting unit; And adjusting a DC setting of the first equalizer by a plurality of DC items outputted within a predetermined time; and adjusting an AC setting of the equalizer according to the plurality of AC items outputted in the first predetermined time. 如請求項5所述之方法，其中根據於該第一預定時間內輸出之複數個直流項，調整該等化器的直流設定包含：平均於該第一預定時間內輸入之複數個直流項，以產生一直流參數；及根據複數個直流參數，調整該直流設定。The method of claim 5, wherein adjusting the DC setting of the equalizer according to the plurality of DC items outputted during the first predetermined time comprises: multiplexing a plurality of DC items input in the first predetermined time, To generate a DC parameter; and adjust the DC setting according to a plurality of DC parameters. 如請求項5所述之方法，其中根據於該第一預定時間內輸出之複數個交流項，調整該等化器的交流設定包含：對該第一預定時間內該複數個交流項，執行一離散餘弦轉換及一離散正弦轉換，以產生一交流參數；及根據複數個交流參數，調整該交流設定。The method of claim 5, wherein adjusting the alternating current setting of the equalizer according to the plurality of alternating items outputted in the first predetermined time comprises: performing one of the plurality of alternating items in the first predetermined time Discrete cosine transform and a discrete sinusoidal transform to generate an AC parameter; and adjust the AC setting according to a plurality of AC parameters. 如請求項5所述之方法，其中該超取樣時脈的頻率大於該資料頻率的二倍。The method of claim 5, wherein the frequency of the oversampled clock is greater than twice the frequency of the data.
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