CN102169860B - Semiconductor structure with passive component structure and manufacturing method thereof - Google Patents
Semiconductor structure with passive component structure and manufacturing method thereof Download PDFInfo
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- CN102169860B CN102169860B CN 201110037396 CN201110037396A CN102169860B CN 102169860 B CN102169860 B CN 102169860B CN 201110037396 CN201110037396 CN 201110037396 CN 201110037396 A CN201110037396 A CN 201110037396A CN 102169860 B CN102169860 B CN 102169860B
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Abstract
Provided is a semiconductor structure with a passive component structure and a manufacturing method thereof. The semiconductor structure comprises an interposer substrate, a first dielectric layer, a passive component layer, a second dielectric layer and a re-distribution layer. The first dielectric layer is arranged on the interposer substrate which is provided with a via. The first dielectric layer is provided with a first aperture and the conductive via is exposed from the first aperture. The passive component layer is arranged on the first dielectric layer and is provided with a second aperture. The first aperture is exposed from the second aperture. The second dielectric layer is disposed at the passive component layer. The re-distribution layer is disposed at the passive component layer and is electrically connected with the conductive via through a second aperture of the second dielectric layer, the second aperture of the passive component layer and the first aperture of the first dielectric layer.
Description
Technical field
The invention relates to a kind of semiconductor structure and manufacture method thereof, and particularly relevant for a kind of semiconductor structure and manufacture method thereof with passive component structure.
Background technology
Traditional intermediary layer comprises silicon substrate, the first insulating barrier, the second insulating barrier and line layer.The first insulating barrier and the second insulating barrier are formed at respectively on relative two of silicon substrate.Silicon substrate has at least one via, and line layer is formed at the first insulating barrier and the second insulating barrier wherein on the one, and is electrically connected at via.
Yet the line layer of traditional intermediary layer is simple effect as being electrically connected via only, in addition there is no other purposes, so that the purposes of line layer is restricted.
Summary of the invention
The present invention is relevant for a kind of semiconductor structure and manufacture method thereof, on the make in the process of interlayer, utilizes the line layer of intermediary layer to form passive component structure, with the purposes of the line layer that increases intermediary layer, the application of expansion intermediary layer.
According to a first aspect of the invention, a kind of semiconductor structure is proposed.Semiconductor structure comprises an interposer substrate, one first dielectric layer, a passive component layer, a passive component layer, one second dielectric layer and a rerouting layer (re-distribution layer, RDL).Interposer substrate has a via (conductive via).The first dielectric layer is formed at interposer substrate, and wherein the first dielectric layer has one first perforate, and via is exposed in the first perforate.The passive component layer is formed on the first dielectric layer, and wherein the passive component layer has one second perforate, and wherein the first perforate is exposed in the second perforate.The second dielectric layer is formed at the passive component layer.The rerouting layer is formed at the second dielectric layer, and the rerouting layer is electrically connected at via via the second perforate of the second dielectric layer, passive component layer and the first perforate of the first dielectric layer.
A kind of manufacture method of semiconductor structure is proposed according to a second aspect of the invention.Manufacture method may further comprise the steps.One interposer substrate is provided, and interposer substrate has a via; Form one first dielectric layer in interposer substrate; Form a passive component layer in the first dielectric layer; Contiguous the first dielectric layer forms the positive photoresist layer of a patterning; As shielding (mask), form one first perforate in the first dielectric layer with the positive photoresist layer of patterning, wherein, via is exposed in the first perforate; Remove the positive photoresist layer of patterning; Form one second dielectric layer in the passive component layer; And, form a rerouting layer in the second dielectric layer, wherein the rerouting layer is electrically connected at via via the first perforate of the first dielectric layer.
For there is better understanding above-mentioned and other aspect of the present invention, at least one embodiment cited below particularly, and cooperate accompanying drawing, be described in detail below:
Description of drawings
Fig. 1 illustrates the cutaway view according to the semiconductor structure of one embodiment of the invention.
Fig. 2 illustrates the top view of induction structure among Fig. 1, capacitance structure and electric resistance structure.
Fig. 3 illustrates the cutaway view according to the semiconductor structure of another embodiment of the present invention.
Fig. 4 A to 4L illustrates the manufacturing schematic diagram of the semiconductor structure of Fig. 1.
Fig. 5 A to 5E illustrates the manufacturing schematic diagram of the semiconductor structure of Fig. 3.
The primary clustering symbol description:
100,200: semiconductor structure
102: interposer substrate
102a: first surface
102b: second
104,204: the first dielectric layers
104a, 204a: the first perforate
106,206: the passive component layer
106a, 206a: the second perforate
106a1,206a1: the first sub-perforate
106a2,206a2: the second sub-perforate
108,208: the second dielectric layers
108a, 208a: the 3rd perforate
108b, 108b: the first electrode
108c, 208c: the second electrode
110,210: the rerouting layer
110a, 210a: the first electrical junction
110b, 210b: the second electrical junction
110c, 210c: the 3rd electrical junction
112: via
114,214: the first metal layer
114 ': the first metal material
114s, 116s, 204s, 214s, 216s, 218s, 220s: side
116,216: the second metal levels
116a, 216a: resistance electrode
116b: the first capacitance electrode
116c, 204b: a part
116 ': the second metal material
118,218: capacitance dielectric layer
118 ': the electric capacity dielectric material
120,220: the three metal levels
120 ': the 3rd metal material
122: the first electrical contact
124: the second electrical contact
126: the first dielectric protection layer
126a: the 4th perforate
132,232: the positive photoresist layer of patterning
132a, 232a: perforate
134: the second dielectric protection layer
134a: the 5th perforate
136: support plate
C: capacitance structure
D1, D2: internal diameter
L: induction structure
R: electric resistance structure
Embodiment
Please refer to Fig. 1, it illustrates the cutaway view according to the semiconductor structure of one embodiment of the invention.Semiconductor structure 100 comprises interposer substrate 102, the first dielectric layer 104, passive component layer 106, the second dielectric layer 108 and rerouting layer (re-distribution layer, RDL) 110.
The via of interposer substrate extends between the first surface of interposer substrate and second.For example, via 112 extends to second 102b from the first surface 102a of interposer substrate 102, and namely via 112 runs through interposer substrate 102.The material of the first dielectric layer 104 for example is macromolecular material, and its first surface 102a that is formed at interposer substrate 102 goes up and has at least one the first perforate 104a, and the first perforate 104a exposes corresponding via 112.
The rerouting layer is formed at the passive component layer and is electrically connected at the via of interposer substrate via the second dielectric layer, passive component layer and the first dielectric layer.For example, the second dielectric layer 108 has at least one the 3rd perforate 108a, and rerouting layer 110 is electrically connected at the via 112 of interposer substrate 102 via the first perforate 104a of the second perforate 106a of the 3rd perforate 108a of the second dielectric layer 108, passive component layer 106 and the first dielectric layer 104.
The first perforate, the second perforate, the 3rd perforate and via overlap.For example, the first perforate 104a, the second perforate 106a, the 3rd perforate 108a and via 112 overlap along the bearing of trend of via 112.So, the first perforate 104a, the second perforate 106a and the 3rd perforate 108a can expose via 112 jointly, and so this is non-in order to limit present embodiment.
The second dielectric layer is formed at the passive component layer.For example, the second dielectric layer 108 covers capacitance dielectric layer 118 and the 3rd metal level 120 of passive component layer 106 at least.
In addition, the second dielectric layer 108 has more the first electrode 108b and the second electrode 108c.The 3rd metal level 120 exposes from the first electrode 108b, and the second metal level 116 exposes from the second electrode 108c.
The rerouting layer is formed on the passive component layer and has induction structure.For example, rerouting layer 110 has induction structure L, and rerouting layer 110 has more the first electrical junction 110a, the second electrical junction 110b and the 3rd electrical junction 110c.The first electrical junction 110a of rerouting layer 110 via the 3rd perforate 108a and the second perforate 106a electrical contact in the first metal layer 114 and second metal level 116 of passive component layer 106, and more via the first perforate 104a electrical contact of the first dielectric layer 104 in via 112.The second electrical junction 110b of rerouting layer 110 is via three metal level 120 of the first electrode 108b electrical contact in passive component layer 106, and the 3rd electrical junction 110c of rerouting layer 110 is via second metal level 116 of the second electrode 108c electrical contact in passive component layer 106.
The first metal layer 114 has at least one first sub-perforate 106a1, and the second metal level 116 has at least one second sub-perforate 106a2.Above-mentioned the second perforate 106a comprises the first sub-perforate 106a1 of the first metal layer 114 and the second sub-perforate 106a2 of the second metal level 116.
The material high resistance material of the first metal layer 114, for example the first metal layer 114 is selected from the group that tantalum nitride (TaN), PbTiO3, ruthenic oxide (RuO2), nickel phosphide (NiP), chromaking nickel (NiCr), NCAlSi and combination thereof consist of.The material of the second metal level 116 and the 3rd metal level 120 is the good material of conductivity for example, for example is copper aluminium (AlCu).The material insulator of capacitance dielectric layer 118 for example is tantalum pentoxide (Ta2O5).Although figure does not illustrate, a right tantalum (Ta) layer can be formed on the first metal layer 114, and this tantalum layer is after anodic oxidation, and its at least a portion forms tantalum pentoxide, and namely capacitance dielectric layer 118.
In addition, semiconductor structure 100 more comprises the first dielectric protection layer 126, the second dielectric protection layer 134, at least one the first electrical contact 122 and at least one the second electrical contact 124.
The first dielectric protection layer is exposed the rerouting layer.For example, the first dielectric protection layer 126 is formed on the rerouting layer 110 and has at least one the 4th perforate 126a.The 4th perforate 126a exposes rerouting layer 110, and for example, the 4th perforate 126a exposes the first electrical junction 110a of rerouting layer 110.
The first electrical contact of semiconductor structure is electrically connected at the rerouting layer, makes an external circuit be electrically connected at semiconductor structure by the first electrical contact.For example, the first electrical contact 122 is formed on the first electrical junction 110a of rerouting layer 110, uses to be electrically connected in rerouting layer 110 and the passive component layer 106 at least one.
The second dielectric protection layer of semiconductor structure is exposed via.For example, it is upper and have at least one the 5th perforate 134a that the second dielectric protection layer 134 is formed at second 102b of interposer substrate 102, and the 5th perforate 134a exposes corresponding via 112.
The second electrical contact 124 of semiconductor structure 100 is formed at the interior also electrical contact of the 5th perforate 134a in via 112.
Please refer to Fig. 3, it illustrates the cutaway view according to the semiconductor structure of another embodiment of the present invention.Semiconductor structure 200 is with one of not existing together of above-mentioned semiconductor structure 100, the side of the second dielectric layer 208 isolation rerouting layers 210 and passive component layer 206.Say that further rerouting layer 210 does not touch the side of passive component layer 206, for example do not touch the side 214s of the first metal layer 214 of passive component layer 206 and the side 216s of the second metal level 216.
The second dielectric layer 208 has at least one the 3rd perforate 208a, and the 3rd perforate 208a exposes corresponding the second perforate 206a, the first perforate 204a and via 112.
The second dielectric layer coats the side of the first metal layer and the second metal level, and it is not exposed.For example, passive component layer 206 comprises the first metal layer 214, the second metal level 216, capacitance dielectric layer 218 and the 3rd metal level 220.The second dielectric layer 208 covers side 214s, the side 216s of the second metal level 216, the side 220s of the 3rd metal level 220 and the side 218s of capacitance dielectric layer 218 of the first metal layer 214 of passive component layer 206, and the side of the first metal layer 214, the second metal level 216, the 3rd metal level 220 and capacitance dielectric layer 218 is not exposed from the 3rd perforate 208a.In other enforcement aspect, the second dielectric layer 208 more can cover the side of the first dielectric layer 204, and the side 204s that makes the first dielectric layer 204 does not expose from the 3rd perforate 208a of the second dielectric layer 208 or from the first perforate 204a of the first dielectric layer 204.
Below with the manufacture method of Fig. 4 A to 4L explanation semiconductor structure 100.Fig. 4 A to 4L illustrates the manufacturing schematic diagram of the semiconductor structure of Fig. 1.
Then, shown in Fig. 4 A, form the first dielectric layer in interposer substrate.For example, with such as being that printing (printing), spin coating (spinning) or spraying coating methods such as (spraying) form the first dielectric layer 104 on the first surface 102a of interposer substrate 102.Wherein, the material of the first dielectric layer 104 for example is the minus photoresistance.
Then, form passive component layer 106 on the first dielectric layer 104.The formation method of passive component layer 106 has a variety of, below enumerates wherein a kind of explaining.
At first, form the first metal material on the first dielectric layer.For example, for example to be any of several materials method, form the first metal material 114 ' shown in Fig. 4 B on the first dielectric layer 104.The material resistance material of the first metal material 114 ' makes the first metal material 114 ' can be used as the resistive layer material of follow-up electric resistance structure R.
Above-mentioned material formation method for example is chemical vapour deposition (CVD), electroless plating method (electroless plating), metallide (electrolytic plating), printing, spin coating, spraying, sputter (sputtering) or vacuum deposition method (vacuum deposition).
Then, shown in Fig. 4 B, form the second metal material 116 ' on the first metal material 114 '.The second metal material 116 ' can be used as the electrode of the electric resistance structure R of the electrode of capacitance structure C of follow-up formation and follow-up formation.The formation method of the second metal material 116 ' is held this and is repeated no more similar in appearance to the first metal material 114 '.
Then, shown in Fig. 4 B, form electric capacity dielectric material 118 ' on the second metal material 116 '.
The electric capacity dielectric material can be oxide layer.For example, before the step that forms electric capacity dielectric material 118 ', can form a tantalum layer (not illustrating) on the second metal material 116 '; Then, for example to be anode oxidation method, this tantalum layer of oxidation forms oxide layer with the surface in this tantalum layer, and this oxide layer is electric capacity dielectric material 118 '.
Then, shown in Fig. 4 C, form the 3rd metal material 120 ' on electric capacity dielectric material 118 '.The 3rd metal material 120 ' can be used as the electrode material of follow-up capacitance structure C.
Then, shown in Fig. 4 D, patterning the first metal material 114 ', the second metal material 116 ', electric capacity dielectric material 118 ' and the 3rd metal material 120 ' are to form respectively the first metal layer 114, the second metal level 116, capacitance dielectric layer 118 and the 3rd metal level 120.Wherein, the first metal layer 114 and the second metal level 116 form at least one electric resistance structure R, and the second metal level 116, capacitance dielectric layer 118 and the 3rd metal level 120 form at least one capacitance structure C.So far, form passive component layer 106.
The second metal level 116 comprises at least one resistance electrode 116a and at least one the first capacitance electrode 116b.Resistance electrode 116a can be used as the electrode of electric resistance structure R, the first capacitance electrode 116b is as the bottom electrode of capacitance structure C, the 3rd metal level 120 can be used as the top electrode of capacitance structure C, and capacitance dielectric layer 118 is located between the first capacitance electrode 116b and the 3rd metal level 120.
Above-mentioned patterning method for example is lithography process (photolithography), chemical etching (chemicaletching), laser drill (laser drilling) or machine drilling (mechanical drilling).
Then, shown in Fig. 4 E, contiguous the first dielectric layer 104 forms the positive photoresist layer 132 of patterning.For example, form the positive photoresist layer 132 of patterning in the passive component layer 206 of the first dielectric layer 104 tops, wherein the part of the positive photoresist layer 132 of patterning is positioned at the first dielectric layer 104, the first metal layer 114 and second metal level 116 of via 112 tops.
The positive photoresist layer of patterning exposes the part of passive component layer.For example, the positive photoresist layer 132 of patterning has at least one perforate 132a, and perforate 132a exposes a part of 116c of the second metal level 116 of passive component layer 106, this part 116c of the second metal level 116 be positioned at via 112 directly over.
Then, shown in Fig. 4 F,, form at least one the first perforate 104a and form at least one the second perforate 106a in passive component layer 106 in the first dielectric layer 104 as shielding (mask) with the positive photoresist layer 132 of patterning.Wherein, the first perforate 104a exposes via 112, and the second perforate 106a exposes the first perforate 104a.For example, in etching (etching) mode, the perforate 132a of etching solution by the positive photoresist layer 132 of patterning, etching the first dielectric layer 104 are forming the first perforate 104a, and etching passive component layer 106 is to form the second perforate 106a.Wherein, the first perforate 104a and the second perforate 106a can form in similar and different etching condition.
In other enforcement aspect,, only form the second perforate 106a and do not form the first perforate 104a in passive component layer 106 as shielding with the positive photoresist layer 132 of patterning.The first perforate 104a of the first dielectric layer 104 can (shown in Fig. 4 G) form after the second dielectric layer 108 forms, and for example, the first perforate 104a can form simultaneously with the 3rd perforate 108a (being illustrated in Fig. 4 G) of the second dielectric layer 108.After the first perforate 104a formed, via 112 exposed.
The second perforate 106a comprises the first sub-perforate 106a1 and the second sub-perforate 106a2, the first sub-perforate 106a1 runs through the first metal layer 114 of passive component layer 106, make the first metal layer 114 expose a side 114s, and the second sub-perforate 106a2 runs through the second metal level 116 of passive component layer 106, makes the second metal level 116 expose a side 116s.Wherein, the first sub-perforate 106a1 and the second sub-perforate 106a2 can form in similar and different etching condition.
The second perforate 106a forms prior to the first perforate 104a, and the first dielectric layer 104 is exposed from the first perforate 104a.Has the metal level (the first metal layer 114 and the second metal level 116) of the passive component layer 106 of the second perforate 106a just as a metallic shield.Because the characteristic of metallic shield, the first perforate 104a is formed after, it is also less just as straight hole or tapering very little hole and its aperture, for example, about in fact 10 microns of the minimum diameter D1 of the first perforate 104a (μ m).Say that further metallic shield has limited the reaming amount of the first perforate 204a, therefore can control accurately the size of the first perforate 204a.Thus, can form more the first perforate 104a, the quantity that increases more import and export contacts and the size of dwindling semiconductor structure.
Because the positive photoresistance characteristic of the positive photoresist layer 132 of patterning is so that under wet etching process, after the first perforate 204a formed, D2 was less for its minimum diameter.Say that further the positive photoresist layer 232 of patterning has limited the reaming amount of the first perforate 204a, therefore can control accurately the size of the first perforate 204a.Thus, can form more the first perforate 104a, the quantity that increases more import and export contacts and the size of dwindling semiconductor structure.
Then, remove the positive photoresist layer 132 of patterning, the structure after removing is shown in Fig. 4 F.
Then, shown in Fig. 4 G, form the second dielectric layer in the passive component layer.For example, in the first metal layer 114, the second metal level 116, the 3rd metal level 120 that the second dielectric layer 108 covers passive component layers 106 and the capacitance dielectric layer 118 at least one, wherein the second dielectric layer 108 does not cover the side 114s of the first metal layer 114 and the side 116s of the second metal level 116, and namely the second dielectric layer 108 exposes the side 114s of the first metal layer 114 and the side 116s of the second metal level 116.The second dielectric layer 108 also has at least one the 3rd perforate 108a, and the 3rd perforate 108a exposes the first capacitance electrode 116b.
Form the mode of the second dielectric layer 108 similar in appearance to the mode that forms the first dielectric layer 104, hold this and repeat no more.The material of the second dielectric layer 108 can similar in appearance to the first dielectric layer 104, be held this and repeat no more.
The second dielectric layer has more at least one the first electrode and at least one the second electrode, to expose the passive component layer.For example, the first electrode 108b of the second dielectric layer 108 exposes the 3rd corresponding metal level 120.The second electrode 108c of the second dielectric layer 108 exposes the resistance electrode 116a of the second corresponding metal level 116.
Then, shown in Fig. 4 H, form rerouting layer 110 on the second dielectric layer 108.Wherein, rerouting layer 110 is electrically connected at via 112 via the 3rd perforate 108a of the second dielectric layer 108, the second perforate 106a of passive component layer 106 and the first perforate 104a of the first dielectric layer 104.In addition, rerouting layer 110 can have induction structure L, and so in other enforcement aspect, rerouting layer 110 also can omit induction structure L.
In the step that forms the rerouting layer, the rerouting layer is electrically connected at the passive component layer.For example, rerouting layer 110 comprises the first electrical junction 110a, the second electrical junction 110b and the 3rd electrical junction 110c.The first electrical junction 110a of rerouting layer 110 is covered in the side 114s of the first metal layer 114 of passive component layer 106 and the side 116s of the second metal level 116 via the second perforate 106a of the 3rd perforate 108a of the second dielectric layer 108 and passive component layer 106, and more via the first perforate 104a electrical contact of the first dielectric layer 104 in via 112.The second electrical junction 110b of rerouting layer 110 via the first electrode 108b electrical contact of the second dielectric layer 108 in the 3rd metal level 120 of passive component layer 106.The 3rd electrical junction 110c of rerouting layer 110 via the second electrode 108c electrical contact of the second dielectric layer 108 in the second metal level 116 of passive component layer 106.
Then, form the first dielectric protection layer on the rerouting layer, with protection rerouting layer.For example, for example to be lithography process, first dielectric protection layer 126 of formation shown in Fig. 4 I is on rerouting layer 110.Wherein, the first dielectric protection layer 126 has at least one the 4th perforate 126a, and the 4th perforate 126a exposes the first corresponding in the rerouting layer 110 electrical junction 110a.
Then, form the first electrical contact and be electrically connected at the rerouting layer.For example, for example to be electro-plating method, first electrical contact 122 of formation shown in Fig. 4 I is on the first electrical junction 110a of rerouting layer 110, so that the first electrical contact 122 electrical contacts are in rerouting layer 110.
After this step is finished (Fig. 4 I), namely form the semiconductor structure that has passive component layer 106 and can externally be electrically connected.Among one embodiment, can further form electrical contact in second 102b of interposer substrate 102 by following steps, can make many sides of semiconductor structure have electrical contact, so this is non-in order to limit the embodiment of the invention.
Be inverted the semiconductor structure 100 ' of Fig. 4 I, make interposer substrate 102 up, shown in Fig. 4 J.
Then, shown in Fig. 4 J, the semiconductor structure 100 ' of Fig. 4 J is set to the adhesive layer (not illustrating) of a support plate 136.
Then, for example to be grinding method, reduce the thickness of interposer substrate 102, and expose second 102b of interposer substrate 102, shown in Fig. 4 J.Wherein, via 112 extends to second 102b from first surface 102a.
In another enforcement aspect, also can omit this grinding step.For example, as long as in the step that interposer substrate 102 is provided, the via 112 of interposer substrate 102 extends to second 102b from first surface 102a, then can omit this grinding step.
Then, second dielectric protection layer 134 of formation shown in Fig. 4 K is in second 102b of interposer substrate 102.
Then, shown in Fig. 4 K, form at least one the 5th perforate 134a on the second dielectric protection layer 134, the 5th perforate 134a exposes corresponding via 112.
Form the mode of the second dielectric protection layer 134 similar in appearance to the mode that forms the first dielectric protection layer 126, hold this and no longer repeat to give unnecessary details.
Then, shown in Fig. 4 L, for example to be electro-plating method, form at least one the second electrical contact 124 in the 5th perforate 134a of correspondence, so that the second electrical contact 124 is electrically connected at via 112.
Then, remove the support plate 136 of Fig. 4 L.So far form semiconductor structure shown in Figure 1 100.
Below with the manufacture method of Fig. 5 A to 5E explanation semiconductor structure 200.Fig. 5 A to 5E illustrates the manufacturing schematic diagram of the semiconductor structure of Fig. 3.In the manufacture method of semiconductor structure 200, the step that interposer substrate is provided is 100 manufacture method to the step that forms the 3rd metal material similar in appearance to semiconductor structure, holds this and repeats no more.Below begin explanation from the step of patterning the first metal material, the second metal material, electric capacity dielectric material and the 3rd metal material.
Shown in Fig. 5 A, patterning the first metal material 114 ', the second metal material 116 ', electric capacity dielectric material 118 ' and the 3rd metal material 120 ' are to form respectively the first metal layer 214, the second metal level 216, capacitance dielectric layer 218 and the 3rd metal level 220.So far, form passive component layer 206.Wherein, the second perforate of passive component layer overlaps across the first dielectric layer and via, and namely the via of interposer substrate is only covered by the first dielectric layer.For example, passive component layer 206 has the second perforate 206a, and it comprises the first sub-perforate 206a1 and the second sub-perforate 206a2.The first metal layer 214 has the first sub-perforate 206a1, the second metal level 216 has the second sub-perforate 206a2, the position of the position of the first sub-perforate 206a1 and the second sub-perforate 206a2 overlaps and corresponding via 112, to expose the first dielectric layer 204 of via 112 tops.
The first metal layer 214 and the second metal level 216 form at least one electric resistance structure R, and the second metal level 216, capacitance dielectric layer 218 and the 3rd metal level 220 form at least one capacitance structure C.
The second metal level 216 comprises at least one resistance electrode 216a and at least one the first capacitance electrode 216b.Resistance electrode 216a can be used as the electrode of electric resistance structure R, the first capacitance electrode 216b is as the bottom electrode of capacitance structure C, the 3rd metal level 220 can be used as the top electrode of capacitance structure C, and capacitance dielectric layer 218 is located between the first capacitance electrode 216b and the 3rd metal level 220.
Then, shown in Fig. 5 B, contiguous the first dielectric layer 204 forms the positive photoresist layer 232 of patterning.For example, form the positive photoresist layer 232 of patterning and cover the first dielectric layer 204 and passive component layer 206, wherein the part of the positive photoresist layer 232 of patterning is positioned on the first dielectric layer 204 of via 112 tops.
The positive photoresist layer 232 of patterning exposes the part of the first dielectric layer 204.For example, the positive photoresist layer 232 of patterning has at least one perforate 232a, and perforate 232a exposes a part of 204b of the first dielectric layer 204, this part 204b of the first dielectric layer 204 be positioned at via 112 directly over.
Then, shown in Fig. 5 C, as shielding, form at least one first perforate 204a in the first dielectric layer 204 with the positive photoresist layer 232 of patterning.Wherein, the first perforate 204a exposes corresponding via 112.For example, with etching mode, etching solution is by perforate 232a etching first dielectric layer 204 of the positive photoresist layer 232 of patterning, to form the first perforate 204a.
Because the characteristic of the positive photoresistance of the positive photoresist layer 232 of patterning is so that under wet etching process, after the first perforate 204a formed, its minimum diameter D2 can be controlled in the 10 μ m approximately.Say that further the positive photoresist layer 232 of patterning has limited the reaming amount of the first perforate 204a, therefore can control accurately the size of the first perforate 204a.
Then, remove the positive photoresist layer 232 of patterning, the structure after removing is shown in Fig. 5 C.
Then, form the second dielectric layer in the passive component layer.For example, shown in Fig. 5 D, in the first metal layer 214, the second metal level 216, the 3rd metal level 220 that the second dielectric layer 208 covers passive component layers 206 and the capacitance dielectric layer 218 at least one.The second dielectric layer 208 also has at least one the 3rd perforate 208a, and the 3rd perforate 208a exposes the first corresponding in the first dielectric layer 204 perforate 204a.Form the mode of the second dielectric layer 208 similar in appearance to the mode that forms the first dielectric layer 204, hold this and repeat no more.
The second dielectric layer has more at least one the first electrode and at least one the second electrode, to expose the passive component layer.For example, the first electrode 208b of the second dielectric layer 208 exposes the 3rd corresponding metal level 220.The second electrode 208c of the second dielectric layer 208 exposes the resistance electrode 216a of the second corresponding metal level 216.
In another enforcement aspect, the second dielectric layer 208 also can coat the side 204s of the first dielectric layer 204, and the side 204s of the first dielectric layer 204 is not exposed from the 3rd perforate 208a or the first perforate 204a.
Then, shown in 5E figure, form rerouting layer 210 on passive component layer 206.Wherein, rerouting layer 210 is electrically connected at via 112 via the 3rd perforate 208a of the second dielectric layer 208 and the first perforate 204a of the first dielectric layer 204.In addition, rerouting layer 210 has induction structure L.
The rerouting layer is electrically connected at the passive component layer, and for example, rerouting layer 210 comprises the first electrical junction 210a, the second electrical junction 210b and the 3rd electrical junction 210c.The first electrical junction 210a of rerouting layer 210 via the first perforate 204a electrical contact of the 3rd perforate 208a of the second dielectric layer 208 and the first dielectric layer 204 in via 112.The second electrical junction 210b of rerouting layer 210 via the first electrode 208b electrical contact of the second dielectric layer 208 in the 3rd metal level 220 of passive component layer 206.The 3rd electrical junction 210c of rerouting layer 210 via the second electrode 208c electrical contact of the second dielectric layer 208 in the second metal level 216 of passive component layer 206.
In aspect an enforcement, the next manufacturing step of semiconductor structure 200 can similar in appearance to the manufacturing step of the semiconductor structure 100 of Fig. 1, hold this and no longer repeat to give unnecessary details.
The semiconductor structure of the above embodiment of the present invention and manufacture method thereof have multinomial feature, and it is as follows to enumerate the part feature description:
(1). on the make in the process of interlayer, form in the lump passive component structure, to increase the purposes of intermediary layer, the application of expansion intermediary layer.
(2). expose the perforate of the via of interposer substrate, it is just as straight hole or the very little hole of tapering.
In sum, although the present invention discloses as above with a plurality of embodiment, so it is not to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (13)
1. semiconductor structure with passive component structure comprises:
One interposer substrate has a via;
One first dielectric layer is formed on this interposer substrate, and wherein this first dielectric layer has one first perforate, and this via is exposed in this first perforate;
One passive component layer is formed on this first dielectric layer, and this passive component layer comprises:
One the first metal layer is formed on this first dielectric layer;
One second metal level is formed on this first metal layer;
One capacitance dielectric layer is formed on this second metal level; And
One the 3rd metal level is formed on this capacitance dielectric layer;
Wherein, this the first metal layer and this second metal level consist of at least one electric resistance structure, and this second metal level, this capacitance dielectric layer and the 3rd metal level consist of at least one capacitance structure, and wherein this passive component layer has one second perforate, and wherein this first perforate is exposed in this second perforate;
One second dielectric layer is formed at this passive component layer, and wherein this second dielectric layer has one the 3rd perforate; And
One rerouting layer is formed on this second dielectric layer, and this rerouting layer is electrically connected at this via via the 3rd perforate of this second dielectric layer, this second perforate of this passive component layer and this first perforate of this first dielectric layer.
2. semiconductor structure as claimed in claim 1, wherein this rerouting layer has an induction structure.
3. semiconductor structure as claimed in claim 1, wherein this first perforate, this second perforate, the 3rd perforate and this via overlap.
4. semiconductor structure as claimed in claim 1, wherein the material of this first metal layer is selected from tantalum nitride (TaN), PbTiO
3, ruthenic oxide (RuO
2), the group that consists of of nickel phosphide (NiP), chromaking nickel (NiCr), NCAlSi and combination thereof.
5. semiconductor structure as claimed in claim 1, wherein this passive component layer exposes from this second perforate, and this rerouting layer covers this passive component layer that exposes from this second perforate.
6. semiconductor structure as claimed in claim 1, wherein this second dielectric layer covers a side of this passive component layer, and this second dielectric layer is isolated this side of this rerouting layer and this passive component layer.
7. manufacture method with semiconductor structure of passive component structure comprises:
One interposer substrate is provided, and this interposer substrate has a via;
Form one first dielectric layer on this interposer substrate;
Form a passive component layer on this first dielectric layer, comprising:
Form one first metal material on this first dielectric layer;
Form one second metal material on this first metal material;
Form an electric capacity dielectric material on this second metal material;
Form one the 3rd metal material on this electric capacity dielectric material; And
This first metal material of patterning, this second metal material, this electric capacity dielectric material and the 3rd metal material, to form respectively a first metal layer, one second metal level, a capacitance dielectric layer and one the 3rd metal level, wherein, this the first metal layer and this second metal level form an electric resistance structure, and this second metal level, this capacitance dielectric layer and the 3rd metal level form a capacitance structure;
Contiguous this first dielectric layer forms the positive photoresist layer of a patterning;
As shielding, form one first perforate in this first dielectric layer with the positive photoresist layer of this patterning, wherein, this via is exposed in this first perforate;
Remove the positive photoresist layer of this patterning;
Form one second dielectric layer on this passive component layer; And
Form a rerouting layer on this second dielectric layer, wherein this rerouting layer is electrically connected at this via via this first perforate of this first dielectric layer.
8. manufacture method as claimed in claim 7, wherein the material of this first metal layer is resistance material.
9. manufacture method as claimed in claim 8, wherein the material of this first metal layer is selected from tantalum nitride, PbTiO
3, the group that consists of of ruthenic oxide, nickel phosphide, chromaking nickel and NCAlSi.
10. manufacture method as claimed in claim 7, wherein after this step of this patterning, this passive component layer forms one second perforate, and this second perforate overlaps across this first dielectric layer and this via;
In this step that forms this second dielectric layer, this second dielectric layer covers a side of this passive component layer, makes in this step that forms this rerouting layer, and this second dielectric layer is isolated this side of this rerouting layer and this passive component layer.
11. manufacture method as claimed in claim 7, wherein after this step of this patterning, this via is covered by this first metal layer, this second metal level and this first dielectric layer;
In this step that runs through this first dielectric layer with the positive photoresist layer of this patterning as this first perforate of shielding formation, more comprise:
Form one second perforate and run through this first metal layer and this second metal level, wherein this first metal layer and this second metal level respectively expose a side;
In this step that forms this rerouting layer, this rerouting layer covers this side of this first metal layer and this side of this second metal level.
12. manufacture method as claimed in claim 11, wherein in this step that forms this second dielectric layer, this second dielectric layer has one the 3rd perforate; In this step that forms this rerouting layer, this rerouting layer is electrically connected at this via via the 3rd perforate, this second perforate and this first perforate.
13. manufacture method as claimed in claim 12, wherein this first perforate, this second perforate, the 3rd perforate and this via overlap.
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| CN102779807A (en) * | 2012-01-16 | 2012-11-14 | 中国科学院上海微***与信息技术研究所 | RDL (radiological defense laboratory) technology-compatible inductive component and manufacture method |
| TW201405758A (en) * | 2012-07-19 | 2014-02-01 | 矽品精密工業股份有限公司 | Anti-EMI semiconductor element |
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| CN1289432A (en) * | 1998-11-26 | 2001-03-28 | 精工爱普生株式会社 | Electro-optical device and production method thereof and electronic equipment |
| CN101151729A (en) * | 2005-03-30 | 2008-03-26 | 富士通株式会社 | Semiconductor device and its making method |
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