CN102169718A - Anti-single event upset performance reinforced static memory unit - Google Patents
Anti-single event upset performance reinforced static memory unit Download PDFInfo
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- CN102169718A CN102169718A CN 201110031853 CN201110031853A CN102169718A CN 102169718 A CN102169718 A CN 102169718A CN 201110031853 CN201110031853 CN 201110031853 CN 201110031853 A CN201110031853 A CN 201110031853A CN 102169718 A CN102169718 A CN 102169718A
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Abstract
The invention discloses an anti-single event upset performance reinforced static memory unit. An up-drawing pipe and a down-drawing pipe in an interlocked phase inverter are divided, namely two up-drawing pipes connected in series replace an up-drawing pipe in a pipe unit 6, and two down-drawing pipes connected in series replace a down-drawing pipe; and the grids of the up-drawing pipes connected in series and the down-drawing pipes connected in series are connected together to form the phase inverter. Another phase inverter is implemented in the same way and is connected with the phase inverter end to end to form an interlocked memory unit. In the invention, the parasitic bipolar transistor effect is relieved effectively, an upset threshold value of the unit is increased, and the anti-single event upset performance reinforced static memory unit is particularly suitable for a silicon-on-insulator (SOI) process.
Description
Technical field:
The invention belongs to the static store field, relate to a kind of static storage cell, the static storage cell that especially a kind of anti-single particle overturn is reinforced.
Background technology:
CMOS (Complementary Metal Oxide Semiconductor) CMOS (Complementary Metal OxideSemiconductor) technology is a kind of semiconductor technology of making VLSI (very large scale integrated circuit).In the many decades in the past, be subjected to the driving of speed, area, power consumption, semiconductor process techniques is updated, and makes the semiconductor structure size lasting scaled.Yet the reduction that cmos device size, voltage continue but will face great reliability challenge.
The challenge of one of them is exactly the single-particle inversion of storage unit.When the proton in alpha particle, cosmic-ray particle or the ground environment and neutron incide the sensitizing range (normally closing the drain region of NMOS or PMOS pipe) of storage unit; can produce electric charge along particle incident track; these electric charges can be collected; when the electric charge of collecting is too much; the logical value of circuit can be changed, and can become 1 or become 0 from 1 from 0 as the logical value of electric capacity or circuit.And in static RAM SRAM (Static RandomAccess Memory) or other storeies, take place thisly when wrong, and then claim storage unit that single-particle inversion has taken place, the data of storage are made mistakes.
Along with device size continues to reduce, the parasitic bipolar transistor effect that causes after the particle incident is also serious more, the easier SEU that causes storage unit.So-called parasitic bipolar transistor is meant the bipolar transistor that is in parallel with the MOS device, is the inevitable a kind of parasitism of MOS device.When particle incident, no matter whether have the body contact, all can cause grid below tagma current potential local dip, trigger the parasitic bipolar transistor conducting, cause the memory node charge-trapping.Channel length is short more, and this charge-trapping is serious more.Along with device size is scaled, supply voltage constantly reduces, and the charge-trapping amount of anti-PN junction is partially descended, and the charge-trapping amount that parasitic bipolar transistor causes is but rising, quite even surpass, become the dominant mechanism of SEU with anti-PN junction charge-trapping amount partially.For SOI technology, anti-inclined to one side PN junction area is little, and the charge-trapping volume is little, but floating empty tagma makes the parasitic bipolar transistor effect serious.Even have the body contact, because silicon fiml is thin, the body contact resistance is big, makes the body contact also not obvious to the effect that reduces the parasitic bipolar transistor effect.
Summary of the invention:
Technical matters to be solved by this invention is: store integrated circuit fields at highly reliable, anti-single particle CMOS, need a kind of anti-single particle storage unit that can reduce the parasitic bipolar transistor effect.The present invention proposes a kind of improved static storage cell, its basic thought is that the sensing crystal pipe in the storage unit is cut apart, and becomes the transistor of two series connection, and an individual district is divided into two tagmas.This new-type unit is applicable to various semiconductor technologies, especially SOI technology.In SOI technology, this unit can adopt floating body transistor, reduces area, has stronger anti-single particle performance simultaneously.
The objective of the invention is to overcome the shortcoming of above-mentioned prior art, the static storage cell that provides a kind of anti-single particle overturn to reinforce comprises the interlocking phase inverter that is made of first phase inverter and second phase inverter:
Described first phase inverter is pulled up transistor by first series connection and the first series connection pull-down transistor constitutes, and first series connection pulls up transistor and the grid of the first series connection pull-down transistor links together constitutes first phase inverter; Described first the series connection pull up transistor by first pull up transistor and second pull up transistor the series connection constitute; The described first series connection pull-down transistor group is made of first pull-down transistor and the series connection of second pull-down transistor;
Described second phase inverter is pulled up transistor by second series connection and the second series connection pull-down transistor constitutes, and second series connection pulls up transistor and the grid of the second series connection pull-down transistor links together constitutes second phase inverter; Described second the series connection pull up transistor by the 3rd pull up transistor and the 4th pull up transistor the series connection constitute; The described second series connection pull-down transistor is made of the 3rd pull-down transistor and the series connection of the 4th pull-down transistor;
Described first phase inverter and the end to end formation interlocking of second phase inverter phase inverter.
Described first source that pulls up transistor terminates at V
CcUpward, drain terminal is connected on the second source end that pulls up transistor; Described second drain terminal that pulls up transistor is connected on the memory node, and first pulls up transistor and second pull up transistor to form and be connected in series.
The source of described second pull-down transistor terminates at V
SsThe source end that go up, drain terminal is connected on first pull-down transistor; The drain terminal of described first pull-down transistor is connected on the memory node, and first pull-down transistor and second pull-down transistor form and be connected in series.
The described the 3rd source that pulls up transistor terminates at V
CcUpward, drain terminal is connected on the 4th source end that pulls up transistor; The described the 4th drain terminal that pulls up transistor is connected on the memory node, and the 3rd pulls up transistor and the 4th pull up transistor to form and be connected in series.
The source of described the 4th pull-down transistor terminates at V
SsThe source end that go up, drain terminal is connected on the 3rd pull-down transistor; The drain terminal of described the 3rd pull-down transistor is connected on the memory node, and the 3rd pull-down transistor and the 4th pull-down transistor form and be connected in series.
Implementation of the present invention and ultimate principle are as follows.Improved static storage cell, on former storage unit basis, with in the interlocking phase inverter pull up transistor and pull-down transistor cut apart.Dividing method is to replace pulling up transistor in traditional 6 pipe units with pulling up transistor of two series connection, replaces former pull-down transistor with the pull-down transistor of two series connection, connects to pull up transistor and connect the grid of the pull-down transistor formation phase inverter that links together.The realization that uses the same method of another phase inverter, end to end with previous phase inverter, realized the interlocking storage unit.
When the sufficiently high particle hits of energy in the sensitizing range of storage unit, the drain region or the tagma of the NMOS that promptly closes pipe or PMOS pipe, 6 common pipe units can take place and the anti-PN junction charge-trapping relevant with parasitic bipolar transistor partially, cause that the unit overturns.
In this unit, when particle hits be connected with power supply close on the transistor time, it only can influence voltage on the intermediate node, can not impact memory node.When particle hits be connected with memory node close on the transistor time, for bulk silicon technological, anti-inclined to one side PN junction can be collected electric charge, and parasitic bipolar transistor only can be collected seldom electric charge, because hit transistorized source end is floating empty, is not connected on the power supply potential.Thereby reduced the charge-trapping amount, effectively raised linear energy transmission LET (Linear Energy Transfer) threshold value.For SOI technology, main charge-trapping mode is the parasitic bipolar transistor effect.In this unit, it is floating empty to be hit transistorized source end, is not connected on the power supply potential, only be that the electric charge with the intermediate node capacitance stores partly is discharged on the memory node, and the electric capacity of memory node is much larger than intermediate node electric capacity.So only can make memory node generation minor swing, but can not cause upset, thereby prevent the upset of SOI static storage cell.Have only when two particles to impinge upon simultaneously on the SOI transistor that two series connection close, or wide-angle influences two series connection simultaneously and close transistorized particle incident, just can cause the upset of this unit.At this weakness, can increase the distance between serial transistor, both can effectively reduce particle influences two series connection simultaneously and closes transistorized possibility.More than analyze as seen, the present invention especially is fit to the static storage cell in the SOI technology, can eliminate single-particle inversion fully.
Description of drawings:
Fig. 1 is a traditional unit storage unit synoptic diagram.
Fig. 2 is a unit storage unit principal diagram intention,
Fig. 3 is a unit storage unit domain synoptic diagram.
Fig. 4 is a unit dual port memory unit structural representation, is used to illustrate another embodiment of the invention;
Fig. 5 is the schematic diagram of the dual-port 12T-SRAM of further embodiment of this invention.
Embodiment:
Below in conjunction with accompanying drawing the present invention is done and to describe in further detail:
Referring to Fig. 1-4, the design of this preferred embodiment will under do and be described in detail, and many contents provided by the present invention can be widely used in the particular range, comprise single port storage unit, multiport storage unit and SRAM storer.The personage who is familiar with this skill can form the unit of other form by feature of the present invention, the design of specific embodiment provided herein and size, domain is in order to feature of the present invention to be described, the user can design according to actual needs voluntarily, is not in order to limit scope of the present invention.
At first see also Fig. 1, this synoptic diagram is traditional 6T-SRAM unit, and has provided satisfied read-write constraint transistor size.Generally speaking, 6 pipe units comprise the first access transistor PG-1, the second access transistor PG-2, first pull up transistor PU-1, second pull up transistor PU-2, the first pull-down transistor PD-1, the second pull-down transistor PD-2.
When operation, storage unit can form two complementary nodes: node 1 (Q) and node 2 (QB), because two phase inverter interlockings can keep complimentary to one another so be stored in the value of each node, and either party disturbance all can be withdrawn into correct level by the signal of complementation.The grid of the first access transistor PG-1 and the second access transistor PG-2 links to each other with word line (WL), reads or write data with control from storage unit.When reading of data, bit line BL and paratope line BLB are charged to high level and disconnect then and being connected.At this moment word line is elevated to high level, opens visit pipe PG-1 and PG-2.Be without loss of generality, what establish the storage of Q point is 0, and the QB point is stored as 1, and then BL discharges by PG-1 and PD-1.In the process of discharge, the level of node Q can raise, and causes unit upset in order to prevent that level is too high, and this moment, the driving force of PD-1 was better than PG-1, and PD-1's is 2 times of PG-1 driving force usually, as shown in Figure 1.Above-mentioned is exactly to read the scleronomic constraint condition.Under situation about writing, all BL and BLB charge to high level earlier, and selected BL and BLB are driven into corresponding level by write circuit, and word line is elevated to high level then, open visit pipe PG-1 and PG-2.Be without loss of generality, what establish the storage of Q point is 0, and what the QB point was stored is 1, and BL and BLB are 1 and 0 by the write circuit driving respectively.Because trombone slide is better than the visit pipe down, so data can not write data by raising Q point current potential, and to 0 on the BLB be write QB, and then feed back to the Q point by last trombone slide and visit pipe, making its rising is 1.The driving force of therefore visiting pipe is better than trombone slide, because the carrier mobility of NMOS is 2-3 times of PMOS, so get the last trombone slide and visit pipe of same size usually.Above-mentionedly can write constraint condition exactly.
The mechanism that single event takes place is as follows.Be without loss of generality, suppose Q=1, QB=0, PD-1, PU-2 close, and PD-2, PU-1 open.On the drain region or tagma of NMOS that particle hits is being closed or PMOS pipe, anti-PN junction partially can be collected a large amount of electric charges.The tagma current potential is raised temporarily, and the parasitic bipolar transistor effect also can increase the charge-trapping amount.For SOI technology, occupy an leading position for back one.Be without loss of generality, hypothetical particle impinges upon sensitizing range, unit, the drain region of PD-1.The electric charge of these collections can change the current potential of memory node Q, promptly becomes low level by high level.This moment, the state of storage unit was unsettled.On the one hand, power supply V
CcBy the PU-1 that opens memory node Q is charged, current potential is risen, return to original state; On the other hand, PD-1 drain region current potential reduces, and is coupled to the grid of PU-2, PD-2, the conducting of PU-2 pipe, PD-2 pipe are ended, and memory node QB current potential raises, and feeds back to the grid of PU-1, PD-1 pipe, make PU-1 pipe manage conducting by, PD-1, at this moment, state of memory cells thoroughly becomes 0 by 1.Therefore, in charged particle incident, make the memory node current potential be reduced to low level after, have the competition of two processes.If required time (tr release time) of rejuvenation is less than the required time of feedback procedure (feedback time tf), when transient current duration that charged particle produces during less than (tf-tr), charged particle incident can not cause the single-particle inversion effect; When transient current duration that charged particle produces during greater than (tf-tr), charged particle can cause the single-particle inversion effect.If release time, tr was greater than feedback time tf, charged particle can cause the single-particle inversion effect.
By above analysis as seen, the key that SEU takes place is that charge stored changes on the memory node electric capacity, causes that storage node voltage changes, and after this voltage propagation and the feedback upset has taken place just.The present invention is directed to main charge-trapping mode at present, promptly parasitic bipolar transistor charge-trapping mode has proposed to improve one's methods, and embodiment is as follows.
Fig. 2 is the schematic diagram of 10T-SRAM of one embodiment of the invention and preferable transistor size.This element comprises first pull up transistor PU-1, second pull up transistor PU-2, the 3rd pull up transistor PU-3, the 4th pull up transistor PU-4, the first pull-down transistor PD-1, the second pull-down transistor PD-2, the 3rd pull-down transistor PD-3, the 4th pull-down transistor PD-4, the first access transistor PG-1 and the second access transistor PG-2.Wherein the grid of the first access transistor PG-1 and the second access transistor PG-2 is connected on the access control signal WL.
Basic operation mode of the present invention is as follows.When read operation, bit line BL and paratope line BLB are charged to high level and disconnect then and being connected.At this moment access control signal WL is elevated to high level, opens visit pipe PG-1 and PG-2.Be without loss of generality, what establish the storage of Q point is 0, and then BL discharges by PG-1, PD-1 and PD-2.In the process of discharge, the level of node Q can raise, and overturns in order to prevent the too high unit that causes of level, and the PD-1 of series connection this moment and the driving force of PD-2 are better than PG-1, and the tandem drive ability of common PD-1 and PD-2 is 2 times of PG-1, as shown in Figure 2.Under situation about writing, all BL and BLB charge to high level earlier, and write circuit opens and drive selected BL and BLB arrives corresponding level, and the access control signal is elevated to high level, open visit pipe PG-1 and PG-2, begin to write.Be without loss of generality, establish the Q point and be stored as 0, the QB point is stored as 1, and BL and BLB are 1 and 0 by the write circuit driving respectively.At this moment, because the driving force of PG-1 is weaker than the following trombone slide PD-1 and the PD-2 of series connection, the Q node can not be drawn high V
CcNear the level, can not realize writing.This is last trombone slide PU-3 and PU-4 that the driving force of requirement PG-2 is better than series connection, and the QB node is dragged down V
SsNear the level, again Q is drawn high after QB is dragged down, realized writing of data.
Fig. 3 is the compact domain implementation of a kind of SOI of first embodiment of the invention, and it is applicable to common reinforcing and the big situation of characteristic dimension.For convenience of description, the figure that includes tiny stain is an active area, the figure that includes empty oblique line is a polysilicon, the interconnection line of unfilled thick line diagrammatic representation ground floor metal M 1, the square of right-angled intersection is polycrystalline and active contact hole to the first metal layer, the square of dotted line right-angled intersection is the contact hole of the first metal layer to second metal level, and finer and closely woven dotted line is second metal level, and more sparse dotted line is the housing of unit.As seen from the figure, this is a kind of very compact implementation, and cellar area is less.Pull up transistor PU-1 and the PU-2 of series connection realized leaking without the source of contact hole multiplexing, and the PU-3 of series connection and PU-4 have realized leaking without the source of contact hole multiplexing, and the source end of PU-1 and PU-3 all is connected on V
CcOn, also can be multiplexing.This several pulling up transistor is drawn without body, and the transistor of series connection has been realized leaking without the source of contact hole multiplexing, reaches the multiplexing of power end, and the unit is diminished.The pull-down transistor PD-1 of series connection and PD-2 have realized leaking without the source of contact hole multiplexing, and the PD-3 of series connection and PD-4 have realized leaking without the source of contact hole multiplexing, and the source end of PD-1 and PD-3 all is connected on V
SsOn, also can be multiplexing.These several pull-down transistors are drawn without body, and the transistor of series connection has been realized leaking without the source of contact hole multiplexing, reaches the multiplexing of power end, and the unit is diminished.Transfer tube PG-1 adopts with PG-2 and has the H shape grid structure that single-ended body contacts.The grid of PG-1 is connected to the first metal layer by contact hole, forms the connection of word line WL.The source electrode of PG-1 is connected to the first metal layer by contact hole, forms the connection of bit line BL.The drain electrode active area of PG-1 links to each other with the drain electrode active area of following trombone slide PD-1, is connected to the first metal layer by contact hole, forms the connection of memory node Q.The drain electrode active area of PG-2 links to each other with the drain electrode active area of following trombone slide PD-3, is connected to the first metal layer by contact hole, forms the connection of memory node QB.
Though little, little for the characteristic dimension technology of above-mentioned domain implementation area, being easy to occur a particle influences two series connection simultaneously and closes transistorized situation, causes upset.At this situation, Fig. 4 has provided mitigation strategy, can realize high anti-SEU performance, is applicable to the high reliability occasion.As seen from the figure, separate with a pull-down transistor between the pulling up transistor of two series connection, pulling up transistor with one between the pull-down transistor of two series connection separates.And use oxygen is kept apart between each transistor, does not have the shared of source leakage, and effectively having alleviated a particle influences two transistorized situations simultaneously, has increased the anti-single particle performance of unit.
Fig. 5 is the schematic diagram of dual-port 12T-SRAM of further embodiment of this invention and preferable transistor size.This 12T-SRAM unit comprises first pull up transistor PU-1, second pull up transistor PU-2, the 3rd pull up transistor PU-3, the 4th pull up transistor PU-4, the first pull-down transistor PD-1, the second pull-down transistor PD-2, the 3rd pull-down transistor PD-3, the 4th pull-down transistor PD-4, the upper port first access transistor UPG-1, the upper port second access transistor UPG-2, the lower port first access transistor DPG-1 and the lower port second access transistor DPG-2.Its working principles is identical with dual port memory unit, and same domain also can adopt compact way or high anti-SEU mode, gives an example no longer in detail here.
According to above-mentioned description to the embodiment circuit, those skilled in the art can be easy to adjust each design parameter and reach needed performance according to concrete applicable cases, does not repeat them here.
Above content is to further describing that the present invention did in conjunction with concrete preferred implementation; can not assert that the specific embodiment of the present invention only limits to this; for the general technical staff of the technical field of the invention; without departing from the inventive concept of the premise; can also make some simple deduction or replace, all should be considered as belonging to the present invention and determine scope of patent protection by claims of being submitted to.
Claims (5)
1. the static storage cell that anti-single particle overturn is reinforced comprises the interlocking phase inverter that is made of first phase inverter and second phase inverter, it is characterized in that:
Described first phase inverter is pulled up transistor by first series connection and the first series connection pull-down transistor constitutes, and first series connection pulls up transistor and the grid of the first series connection pull-down transistor links together constitutes first phase inverter; Described first the series connection pull up transistor by first pull up transistor and second pull up transistor the series connection constitute; The described first series connection pull-down transistor is made of first pull-down transistor and the series connection of second pull-down transistor;
Described second phase inverter is pulled up transistor by second series connection and the second series connection pull-down transistor constitutes, and second series connection pulls up transistor and the grid of the second series connection pull-down transistor links together constitutes second phase inverter; Described second the series connection pull up transistor by the 3rd pull up transistor and the 4th pull up transistor the series connection constitute; The described second series connection pull-down transistor is made of the 3rd pull-down transistor and the series connection of the 4th pull-down transistor;
Described first phase inverter and the end to end formation interlocking of second phase inverter phase inverter.
2. the static storage cell that a kind of according to claim 1 anti-single particle overturn is reinforced, it is characterized in that: described first source that pulls up transistor terminates at V
CcUpward, drain terminal is connected on the second source end that pulls up transistor; Described second drain terminal that pulls up transistor is connected on the memory node, and first pulls up transistor and second pull up transistor to form and be connected in series.
3. the static storage cell that a kind of according to claim 1 anti-single particle overturn is reinforced, it is characterized in that: the source of described second pull-down transistor terminates at V
SsThe source end that go up, drain terminal is connected on first pull-down transistor; The drain terminal of described first pull-down transistor is connected on the memory node, and first pull-down transistor and second pull-down transistor form and be connected in series.
4. the static storage cell that a kind of according to claim 1 anti-single particle overturn is reinforced, it is characterized in that: the described the 3rd source that pulls up transistor terminates at V
CcUpward, drain terminal is connected on the 4th source end that pulls up transistor; The described the 4th drain terminal that pulls up transistor is connected on the memory node, and the 3rd pulls up transistor and the 4th pull up transistor to form and be connected in series.
5. the static storage cell that a kind of according to claim 1 anti-single particle overturn is reinforced, it is characterized in that: the source of described the 4th pull-down transistor terminates at V
SsThe source end that go up, drain terminal is connected on the 3rd pull-down transistor; The drain terminal of described the 3rd pull-down transistor is connected on the memory node, and the 3rd pull-down transistor and the 4th pull-down transistor form and be connected in series.
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| CN104851451A (en) * | 2015-03-27 | 2015-08-19 | 中国科学院自动化研究所 | Memory cell of static random access memory on basis of resistance reinforcement |
| CN105448327A (en) * | 2015-11-16 | 2016-03-30 | 哈尔滨工业大学 | Storage unit resistant to multi-node inversion |
| CN105448328A (en) * | 2014-05-27 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | SRAM memory cell and SRAM memory and control method thereof |
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| CN108806742A (en) * | 2017-05-04 | 2018-11-13 | 汤朝景 | Random access memory and having circuitry, methods and systems related thereto |
| CN111128271A (en) * | 2019-12-25 | 2020-05-08 | 安徽大学 | RHPD-12T radiation-resistant SRAM memory cell circuit |
| CN111354394A (en) * | 2018-12-24 | 2020-06-30 | 上海新微技术研发中心有限公司 | Memory cell, construction method thereof and static random access memory |
| CN113284545A (en) * | 2020-02-19 | 2021-08-20 | 美光科技公司 | Fuse latch circuit and related apparatus, system and method |
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| CN103366802A (en) * | 2013-06-26 | 2013-10-23 | 清华大学 | Static random storage unit |
| CN103366802B (en) * | 2013-06-26 | 2016-06-29 | 清华大学 | A kind of static ram cell |
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| CN104409093B (en) * | 2014-12-09 | 2017-07-28 | 复旦大学 | The transistor memory unit of difference 10 of anti-single particle reversion |
| CN104409093A (en) * | 2014-12-09 | 2015-03-11 | 复旦大学 | Differential ten-tube storage cell resistant to single-event upset |
| CN104851451B (en) * | 2015-03-27 | 2018-03-06 | 中国科学院自动化研究所 | The memory cell for the static random-access memory reinforced based on resistance |
| CN104851451A (en) * | 2015-03-27 | 2015-08-19 | 中国科学院自动化研究所 | Memory cell of static random access memory on basis of resistance reinforcement |
| CN105448327A (en) * | 2015-11-16 | 2016-03-30 | 哈尔滨工业大学 | Storage unit resistant to multi-node inversion |
| CN105448327B (en) * | 2015-11-16 | 2018-03-16 | 哈尔滨工业大学 | The memory cell of anti-multiple node upset |
| CN108806742A (en) * | 2017-05-04 | 2018-11-13 | 汤朝景 | Random access memory and having circuitry, methods and systems related thereto |
| CN111354394A (en) * | 2018-12-24 | 2020-06-30 | 上海新微技术研发中心有限公司 | Memory cell, construction method thereof and static random access memory |
| CN111128271A (en) * | 2019-12-25 | 2020-05-08 | 安徽大学 | RHPD-12T radiation-resistant SRAM memory cell circuit |
| CN113284545A (en) * | 2020-02-19 | 2021-08-20 | 美光科技公司 | Fuse latch circuit and related apparatus, system and method |
| CN113284545B (en) * | 2020-02-19 | 2022-08-23 | 美光科技公司 | Fuse latch circuit and related apparatus, system and method |
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| CN102169718B (en) | 2012-11-21 |
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