CN102169261B - Thin film transistor substrate of liquid crystal display panel - Google Patents
Thin film transistor substrate of liquid crystal display panel Download PDFInfo
- Publication number
- CN102169261B CN102169261B CN 201110009594 CN201110009594A CN102169261B CN 102169261 B CN102169261 B CN 102169261B CN 201110009594 CN201110009594 CN 201110009594 CN 201110009594 A CN201110009594 A CN 201110009594A CN 102169261 B CN102169261 B CN 102169261B
- Authority
- CN
- China
- Prior art keywords
- storage electrode
- line segment
- metal layer
- patterned metal
- area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 46
- 239000000758 substrate Substances 0.000 title claims abstract description 26
- 239000004973 liquid crystal related substance Substances 0.000 title abstract description 4
- 239000002184 metal Substances 0.000 claims description 46
- 238000009413 insulation Methods 0.000 claims description 6
- 230000012447 hatching Effects 0.000 description 12
- 102100038387 Cystatin-SN Human genes 0.000 description 6
- 101000884768 Homo sapiens Cystatin-SN Proteins 0.000 description 6
- 102100028007 Cystatin-SA Human genes 0.000 description 5
- 101000722958 Homo sapiens Cystatin-SA Proteins 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 240000001439 Opuntia Species 0.000 description 1
Images
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention discloses a thin film transistor substrate of a liquid crystal display panel, which comprises a substrate, a plurality of grid lines, a plurality of data lines, a plurality of storage electrode lines, a plurality of shielding wires and a plurality of pixel electrodes. The data lines and the gate lines define a plurality of pixel regions arranged in an array on the substrate. Each storage electrode line penetrates through the corresponding pixel area and divides the pixel areas into a first area and a second area. The shielding wires are respectively arranged in the pixel regions, wherein each shielding wire comprises a first shielding wire section positioned in the first region and a second shielding wire section positioned in the second region. The pixel electrodes are respectively arranged in each pixel area and are respectively electrically connected with the corresponding first shielding lead section and the second shielding lead section.
Description
Technical field
The present invention relates to a kind of thin film transistor base plate of display panels, espespecially a kind of thin film transistor base plate of the display panels that covers wire that in pixel region, is provided with the storage electrode line that runs through pixel region and the both sides that are positioned at the storage electrode line and is electrically connected with pixel electrode.
Background technology
Please refer to Fig. 1, Fig. 1 has illustrated the thin film transistor base plate synoptic diagram of known display panels.As shown in Figure 1, the thin film transistor base plate 1 of known display panels comprises a substrate 10, many gate lines 11, many data lines 12 and many storage electrode lines 13.Each gate line 11 extends along a first direction S1 (a for example horizontal direction), and gate line 11 is set parallel to each other on substrate 10, each data line 12 is along extending along a second direction S2 (a for example vertical direction) substantially, second direction S2 is perpendicular to first direction S1, and data line 12 is set parallel to each other on substrate 10.In addition, gate line 11 is crisscross arranged on substrate 10 with data line 12, and defines a plurality of pixel region P.In addition, storage electrode line 13 and data line 12 parallel being arranged alternately on substrate 10, and each storage electrode line 13 runs through adjacent two data lines 12 and gate line 11 defined pixel region P.Wherein, storage electrode line 13 has many first storage electrode line segments 131 and many second storage electrode line segments 132.
In the thin film transistor base plate of known display panels, the both sides of gate line 11 can produce horizontal component of electric field and affect the arrangement of liquid crystal molecule, and then cause the light leak problem.Because the consideration of storage capacitors value, the second storage electrode line segment 132 only is positioned at a wherein side of gate line 11, therefore the light leak that is positioned at the wherein zone of a side of gate line 11 can stop by the second storage electrode line segment 132, and the light leak in zone that is positioned at the opposite side of gate line 11 must stop by the black matrix" (not shown) on the colored filter substrate of display panels.Yet, because the fineness of black matrix" is low than the fineness of storage electrode line 13, add the generation that when assembling, has bit errors between thin film transistor base plate and the colored filter substrate, therefore can cause the zone of the opposite side of gate line 11 to produce the light leak problem.
Summary of the invention
One of purpose of the present invention is to provide a kind of thin film transistor base plate of the display panels that covers wire that is provided with the storage electrode line that runs through pixel region and the both sides that are positioned at the storage electrode line and is electrically connected with pixel electrode in pixel region, avoids whereby the light leak problem of the thin film transistor base plate of display panels.
A preferred embodiment of the present invention provides a kind of thin film transistor base plate of display panels, comprise a substrate, many gate lines, many data lines, many storage electrode lines, many cover wire and a plurality of pixel electrode.Wherein gate line extends and is set parallel to each other on this substrate along a first direction, data line extends and is set parallel to each other on this substrate along a second direction, second direction is vertical first direction substantially, and data line and gate line are arranged in a crossed manner and define a plurality of pixel regions that are arrayed.Each storage electrode line runs through corresponding pixel region and corresponding pixel region is divided into a first area and a second area.Respectively cover wire and be arranged at respectively in each pixel region, wherein respectively cover wire and comprise that one is positioned at first of first area and covers conducting line segment and and be positioned at second of second area and cover conducting line segment.Pixel electrode is arranged at respectively in each pixel region, and cover wire with corresponding this respectively this first cover conducting line segment and this second and cover conducting line segment and be electrically connected.
The thin film transistor base plate of display panels provided by the present invention, in the pixel region that is defined by gate line and data line, arrange and run through the storage electrode line of pixel region and be positioned at the both sides of storage electrode line and cover wire with pixel electrode is electrically connected, reach whereby the shaded effect that promotes thin film transistor base plate and reach simultaneously the effect of the resistance value that reduces the storage electrode line.
In order to make those skilled in the art can further understand feature of the present invention and technology contents, see also following about detailed description of the present invention and accompanying drawing.Yet appended accompanying drawing is only for reference and aid illustration usefulness, and the present invention is limited.
Description of drawings
Fig. 1 has illustrated the thin film transistor base plate synoptic diagram of known display panels;
Fig. 2 A has illustrated the schematic top plan view of thin film transistor base plate of the display panels of a preferred embodiment of the present invention;
Fig. 2 B has illustrated the diagrammatic cross-section of the thin film transistor base plate of the display panels that illustrates along the A-A ' hatching line of Fig. 2 A and B-B ' hatching line;
Fig. 3 has illustrated the diagrammatic cross-section of another preferred embodiment of the present invention;
Fig. 4 A illustrated another preferred embodiment of the present invention display panels thin film transistor base plate overlook intention;
Fig. 4 B has illustrated the diagrammatic cross-section of the thin film transistor base plate of the display panels that illustrates along the A-A ' hatching line of Fig. 4 A and B-B ' hatching line;
Fig. 5 A has illustrated the schematic top plan view of thin film transistor base plate of the display panels of the second preferred embodiment of the present invention;
Fig. 5 B has illustrated the diagrammatic cross-section of the thin film transistor base plate of the display panels that illustrates along the A-A ' hatching line of Fig. 5 A and B-B ' hatching line.
Wherein, Reference numeral
Thin film transistor base plate 10 substrates of 1 display panels
Thin film transistor base plate 21 substrates of 20 display panels
13, CS storage electrode line 22 pixel electrodes
CST T shape storage electrode line segment CSS linear storage electrode line segment
CST1 the first linear storage electrode line CST2 the second linear storage electrode line
11, GL gate line 12, DL data line
131 first storage electrode line segments, 132 second storage electrode line segments
M1 the first patterned metal layer M2 the second patterned metal layer
M3 the 3rd patterned metal layer TH contact hole
SM covers wire SM1 first and covers conducting line segment
SM2 second covers conducting line segment S1, D1 first direction
S2, D2 second direction P pixel region
P1 first area P2 second area
23 insulation course TFT thin film transistor (TFT)s
The D drain electrode
Embodiment
For make those of ordinary skills can be nearer a step understand the present invention, hereinafter the spy enumerates preferred embodiment of the present invention, and cooperates appended accompanying drawing, describes constitution content of the present invention and the effect wanting to reach in detail.
Please refer to Fig. 2 A and Fig. 2 B, Fig. 2 A has illustrated the schematic top plan view of thin film transistor base plate of the display panels of a preferred embodiment of the present invention, and Fig. 2 B has illustrated the diagrammatic cross-section of the thin film transistor base plate of the display panels that illustrates along the A-A ' hatching line of Fig. 2 A and B-B ' hatching line.Shown in Fig. 2 A and Fig. 2 B, the thin film transistor base plate 20 of the display panels of present embodiment comprise a substrate 21, many gate lines G L, many data line DL, many storage electrode line CS, many cover wire SM and a plurality of pixel electrode 22.Gate lines G L extends (for example horizontal direction of Fig. 2 A) along a first direction D1, and gate lines G L is arranged in parallel with each other and is arranged on the substrate 21, data line DL extends (for example vertical direction of Fig. 2 A) along second direction D2, second direction D2 is vertical first direction D1 substantially, and data line DL is arranged in parallel with each other and is arranged on the substrate 21.In addition, data line DL and gate lines G L are crisscross arranged and define a plurality of pixel region P that are substantially rectangle and are arrayed, and each pixel region P is provided with a thin film transistor (TFT) TFT.In the present embodiment, take three grids (tri-gate) type display panels as the example explanation, that is to say, be under the situation of n*m at resolution, the number of data line DL is m, and the number of gate lines G L is 3n, and each data line DL is corresponding to the minor face of each pixel region P, and each gate lines G L is corresponding to the long limit of each pixel region P.
In the present embodiment, storage electrode line CS is parallel with data line DL and alternately be arranged on the substrate 20.In other words, storage electrode line CS also extends and is arranged on the substrate 21 along second direction D2.In addition, each storage electrode line CS runs through the pixel region P that adjacent two data line DL and all gate lines G L consist of, and the pixel region P that will be run through is divided into a first area P1 and a second area P2.In the present embodiment, each storage electrode line CS comprises many T shape storage electrode line segment CST, lays respectively in each pixel region P.Wherein, each T shape storage electrode line segment CST more comprises one first vertical bar shaped storage electrode line segment CST1 and one second vertical bar shaped storage electrode line segment CST2.The first vertical bar shaped storage electrode line segment CST1 is along second direction D2 extension setting and between the first area of each pixel region P P1 and second area P2, the first vertical bar shaped storage electrode line segment CST1 is arranged in parallel with each other along second direction D2, and the first vertical bar shaped storage electrode line segment CST1 in the adjacent pixel region P is electrically connected to each other.The second vertical bar shaped storage electrode line segment CST2 arranges and is positioned at the side of each pixel region P along first direction D1, and the second vertical bar shaped storage electrode line segment CST2 and corresponding the first vertical bar shaped storage electrode line segment CST1 electric connection.The second vertical bar shaped storage electrode line segment CST2 is except the function with storage capacitors, because it is arranged at the side of gate lines G L, therefore also can stop the light leak that the horizontal component of electric field that produces because of gate lines G L causes, and promote the light shielding ability of the thin film transistor base plate 20 of display panels.
Cover wire SM and be arranged at respectively in each pixel region P, wherein respectively cover wire SM and comprise that one is positioned at first of first area P1 and covers conducting line segment SM1 and and be positioned at second of second area P2 and cover conducting line segment SM2.In the present embodiment, each first covers conducting line segment SM1 and is arranged at substantially in each first area P1 with respect in addition two limits outside the T shape storage electrode line segment CST, and each second covers conducting line segment SM2 and be arranged at substantially in addition two limits that correspond among each second area P2 outside the T shape storage electrode line segment CST, but not as limit.Speak by the book, in the present embodiment, cover wire SM and be arranged at the side of gate lines G L and the side of data line DL, therefore can stop the light leak that this is regional.That is to say, T shape storage electrode line segment CST and first cover conducting line segment SM1 substantially jointly around first area P1 around, and can stop the light leak of the periphery of first area P1, and in like manner T shape storage electrode line segment CST and second cover conducting line segment SM2 substantially jointly around second area P2 around, and can stop the light leak of the periphery of first area P2.In addition, be electrically connected owing to cover wire SM and pixel electrode 22, so can not produce horizontal component of electric field and can avoid affecting the arrangement of liquid crystal molecule.
In the present embodiment, pixel electrode 22 is arranged at respectively on each pixel region P, and the thin film transistor base plate 20 of display panels comprises that in addition an insulation course 23 is arranged at pixel electrode 22 and covers between the wire SM.In each pixel region P, insulation course 23 comprises respectively at least two contact hole TH, and wherein each contact hole TH is arranged at respectively in the first area P1 and second area P2 of each pixel region P.In the present embodiment, each pixel electrode 22 respectively two contact hole TH by insulation course 23 and corresponding first cover conducting line segment SM1 and second and cover conducting line segment SM2 and be electrically connected.In addition, second covers the extension that conducting line segment SM2 can be the drain D of thin film transistor (TFT) TFT for example.
Refer again to Fig. 2 B, in the present embodiment, gate lines G L is made of one first patterned metal layer M1, data line DL, storage electrode line CS with cover wire SM and then consisted of by one second patterned metal layer M2, and the first patterned metal layer M1 is different retes from this second patterned metal layer M2.In the present embodiment, the first patterned metal layer M1 is below the second patterned metal layer M2, but not as limit.In addition and since gate lines G L with cover wire SM and consisted of by different rete, so cover the distance of wire SM and gate lines G L can be more close, and can increase aperture opening ratio.In the present invention, cover wire SM and do not limit by the second patterned metal layer M2 and consisted of, and the viewable design difference is changed.Please refer to Fig. 3, the diagrammatic cross-section of the thin film transistor base plate of the display panels of Fig. 3 another preferred embodiment of the present invention.As shown in Figure 3, in the present embodiment, gate lines G L with cover wire SM and consisted of by one first patterned metal layer M1, and data line DL and storage electrode line CS are made of one second patterned metal layer M2, and the first patterned metal layer M1 is different retes from the second patterned metal layer M2.In addition, in the present embodiment, the wire SM that covers that is made of the first patterned metal layer M1 is electrically connected by contact hole TH and pixel electrode 22.In addition, in the present embodiment, the first patterned metal layer M1 is positioned at the below of the second patterned metal layer M2, but not as limit.
Please be in addition with reference to figure 4A and Fig. 4 B.Fig. 4 A has illustrated the schematic top plan view of thin film transistor base plate of the display panels of another preferred embodiment of the present invention, Fig. 4 B has illustrated A-A ' hatching line and the B-B along Fig. 4 A, the diagrammatic cross-section of the thin film transistor base plate of the display panels that hatching line illustrates.Shown in Fig. 4 A and Fig. 4 B, in the present embodiment, gate lines G L is made of one first patterned metal layer M1, data line DL and storage electrode line CS are made of one second patterned metal layer M2, cover conducting line segment SM1 and be made of the 3rd a patterned metal layer M3 who is arranged on the pixel electrode 22 and cover first of wire SM, wherein the first patterned metal layer M1, the second patterned metal layer M2 are different retes from the 3rd patterned metal layer M3.For example in the present embodiment, the second patterned metal layer M2 is positioned on the first patterned metal layer M1, and the 3rd patterned metal layer M3 is positioned on the second patterned metal layer M2 and the pixel electrode 22 and directly contacts with pixel electrode 22.By above-mentioned configuration, in the present embodiment, respectively cover wire SM and can not must can be electrically connected with each pixel electrode 22 by contact hole, pixel electrode 22 then still is electrically connected by the drain D of contact hole TH and thin film transistor (TFT) TFT.What deserves to be explained is that the 3rd patterned metal layer M3 also can be positioned at the below of pixel electrode 22 for example and directly contacts with pixel electrode 22, cover whereby wire SM still can not must by contact hole and pixel electrode 22 electric connections.
The thin film transistor base plate of display panels of the present invention is not limited with above-described embodiment, and can have other different enforcement kenels.For the purpose of simplifying the description and be easy to comparison, in the second preferred embodiment hereinafter, continue to use identical symbolic representation for similar elements, and only the different place of two embodiment is described in detail.Please refer to Fig. 5 A and Fig. 5 B, Fig. 5 A and Fig. 5 B have illustrated the schematic top plan view of thin film transistor base plate of the display panels of the second preferred embodiment of the present invention, and Fig. 5 B has illustrated the diagrammatic cross-section of the thin film transistor base plate of the display panels that illustrates along the A-A ' hatching line of Fig. 5 A and B-B ' hatching line.Shown in Fig. 5 A and Fig. 5 B, in the present embodiment, storage electrode line CS comprises many vertical bar shaped storage electrode line segment CSS, vertical bar shaped storage electrode line segment CSS extend to arrange and is positioned at each the pixel region P that is made of two adjacent data line DL and all gate lines G L along second direction D2 respectively, and between the first area of each pixel region P P1 and second area P2, and the vertical bar shaped storage electrode line segment CSS in the adjacent pixel region P is electrically connected to each other.In addition, in the present embodiment, respectively covering first of wire SM covers in the first area P1 that conducting line segment SM1 is arranged at each pixel region P substantially, and be arranged at respect in addition three limits outside the vertical bar shaped storage electrode line segment CSS, and respectively cover second of wire SM and cover in the second area P2 that conducting line segment SM2 is arranged at each pixel region P substantially, and be arranged at respect in addition three limits outside the vertical bar shaped storage electrode line segment CSS.That is to say that first covers conducting line segment SM1 and second covers conducting line segment SM2 and have respectively the horseshoe-shaped pattern of a class.By this kind design, vertical bar shaped storage electrode line segment CSS and first cover conducting line segment SM1 substantially jointly around first area P1 around, and can stop the light leak of the periphery of first area P1, and in like manner vertical bar shaped storage electrode line segment CSS and second cover conducting line segment SM2 substantially jointly around first area P2 around, and can stop the light leak of the periphery of second area P2.What deserves to be explained is, in the present embodiment, gate lines G L is made of the first patterned metal layer M1, data line DL, storage electrode line CS with cover wire SM and then consisted of by the second patterned metal layer M2, and the first patterned metal layer M1 is different retes from this second patterned metal layer M2.In addition, gate lines G L, data line DL, storage electrode line CS and the rete that covers the wires such as wire SM be as limit, and can be changed shown in the embodiment of Fig. 3 and Fig. 4 A and Fig. 4 B, do not repeat them here.
In sum, the thin film transistor base plate of display panels of the present invention is arranged in pixel region and is provided with the storage electrode line that runs through pixel region and the both sides that are positioned at the storage electrode line in the pixel region and covers wire with pixel electrode is electrically connected, can reduce whereby the light leak situation of display panels.In addition, because the storage electrode line can comprise vertical bar shaped storage electrode line segment, therefore also can reduce the resistance value of storage electrode line, and can reduce the resistance-capacitance load.
Certainly; the present invention also can have other various embodiments; in the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make according to the present invention various corresponding changes and distortion, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.
Claims (7)
1. the thin film transistor base plate of a display panels comprises: a substrate; Many gate lines, respectively this gate line extends and is arranged on this substrate generally along a first direction; Many data lines, respectively this data line extends and is arranged on this substrate generally along a second direction, this second direction is substantially perpendicular to this first direction, these data lines and these gate lines are arranged in a crossed manner and define a plurality of pixel regions on substrate, and these pixel regions are arrayed; Many storage electrode lines, be arranged alternately with these data lines are parallel, and respectively this storage electrode line runs through these corresponding pixel regions and these corresponding pixel regions is divided into a first area and a second area, many cover wire, be arranged on this substrate and be arranged at respectively respectively in this pixel region, wherein respectively this covers wire and comprises that one first covers conducting line segment and is positioned at respectively this first area of this pixel region, and one second covers conducting line segment and is positioned at respectively this second area of this pixel region; And a plurality of pixel electrodes, be arranged at respectively respectively in this pixel region, and respectively this pixel electrode cover wire with corresponding this respectively this first cover conducting line segment and this second and cover conducting line segment and be electrically connected, it is characterized in that:
Respectively this storage electrode line comprises many T shape storage electrode line segments, be arranged at respectively respectively in this pixel region, respectively this T shape storage electrode line segment comprises one first vertical bar shaped storage electrode line segment and one second vertical bar shaped storage electrode line segment, this the first vertical bar shaped storage electrode line segment is along this second direction setting and between this first area and this second area, and these the first vertical bar shaped storage electrode line segments are electrically connected to each other, this the second vertical bar shaped storage electrode line segment is along this first direction setting and be positioned at a side of this first area and this second area, and the second vertical bar shaped storage electrode line segment and the first vertical bar shaped storage electrode line segment are electrically connected.
2. the thin film transistor base plate of display panels according to claim 1 is characterized in that, respectively this pixel region comprises a rectangle, and a long limit of this rectangle is parallel to this first direction, and a minor face of this rectangle is parallel to this second direction.
3. the thin film transistor base plate of display panels according to claim 1, it is characterized in that, respectively this cover wire this first cover conducting line segment substantially corresponding to this first area with respect to two limits outside this T shape storage electrode line segment, and respectively this cover wire this second cover conducting line segment substantially corresponding to this second area with respect to two limits outside this T shape storage electrode line segment.
4. the thin film transistor base plate of display panels according to claim 1, it is characterized in that, these gate lines and these storage electrode lines are made of one first patterned metal layer, and these data lines are made of one second patterned metal layer, and this first patterned metal layer is different retes from this second patterned metal layer.
5. the thin film transistor base plate of display panels according to claim 1, it is characterized in that, these gate lines are made of one first patterned metal layer, and these data lines and these storage electrode lines are made of one second patterned metal layer, and this first patterned metal layer is different retes from this second patterned metal layer.
6. the thin film transistor base plate of display panels according to claim 1, it is characterized in that, these gate lines are made of one first patterned metal layer, these data lines are made of one second patterned metal layer, and these storage electrode lines are made of one the 3rd patterned metal layer, and this first patterned metal layer, this second patterned metal layer are different retes from the 3rd patterned metal layer.
7. the thin film transistor base plate of display panels according to claim 1, it is characterized in that, other comprises that an insulation course is arranged at these pixel electrodes and these cover between the wire, and this insulation course has a plurality of contact holes, lay respectively in this first area and this second area of this pixel region respectively, cover conducting line segment and this second and cover conducting line segment in order to be electrically connected this pixel electrode respectively and corresponding this first.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW099143273 | 2010-12-10 | ||
| TW99143273A TWI422939B (en) | 2010-12-10 | 2010-12-10 | Thin film transistor substrate of liquid crystal display panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102169261A CN102169261A (en) | 2011-08-31 |
| CN102169261B true CN102169261B (en) | 2013-04-17 |
Family
ID=44490475
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201110009594 Expired - Fee Related CN102169261B (en) | 2010-12-10 | 2011-01-12 | Thin film transistor substrate of liquid crystal display panel |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN102169261B (en) |
| TW (1) | TWI422939B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102130545B1 (en) * | 2013-11-27 | 2020-07-07 | 삼성디스플레이 주식회사 | Liquid crystal display |
| CN105182647B (en) | 2015-10-16 | 2019-01-11 | 深圳市华星光电技术有限公司 | array substrate, liquid crystal display panel and driving method |
| KR102542186B1 (en) * | 2016-04-04 | 2023-06-13 | 삼성디스플레이 주식회사 | Display device |
| KR20170115133A (en) * | 2016-04-04 | 2017-10-17 | 삼성디스플레이 주식회사 | Liquid crystal display device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5844641A (en) * | 1996-10-16 | 1998-12-01 | Hyundai Electronics Industries Co., Ltd. | Liquid crystal display device having storage capacitors and additional opaque electrodes |
| CN101520580A (en) * | 2008-02-28 | 2009-09-02 | 北京京东方光电科技有限公司 | TFT-LCD array substrate structure and manufacturing method thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0815711A (en) * | 1994-06-28 | 1996-01-19 | Kyocera Corp | Active matrix substrate |
| KR100659912B1 (en) * | 2003-12-03 | 2006-12-20 | 엘지.필립스 엘시디 주식회사 | Liquid Crystal Display Device and Method for fabricating the same |
| KR20070031620A (en) * | 2005-09-15 | 2007-03-20 | 삼성전자주식회사 | Liquid crystal display |
| CN100419818C (en) * | 2007-04-23 | 2008-09-17 | 友达光电股份有限公司 | Liquid crystal display device and its driving method |
-
2010
- 2010-12-10 TW TW99143273A patent/TWI422939B/en not_active IP Right Cessation
-
2011
- 2011-01-12 CN CN 201110009594 patent/CN102169261B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5844641A (en) * | 1996-10-16 | 1998-12-01 | Hyundai Electronics Industries Co., Ltd. | Liquid crystal display device having storage capacitors and additional opaque electrodes |
| TW460735B (en) * | 1996-10-16 | 2001-10-21 | Hyundai Electronics Ind | Liquid crystal display device |
| CN101520580A (en) * | 2008-02-28 | 2009-09-02 | 北京京东方光电科技有限公司 | TFT-LCD array substrate structure and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102169261A (en) | 2011-08-31 |
| TWI422939B (en) | 2014-01-11 |
| TW201224618A (en) | 2012-06-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101359825B1 (en) | Liquid crystal display device | |
| CN106165005B (en) | Active-matrix substrate and display device | |
| CN107562270B (en) | Touch display panel and display device | |
| US20170192558A1 (en) | Array substrate, touch display panel and touch display device | |
| US20170031223A1 (en) | Array substrate, liquid crystal display panel and display device | |
| CN104698711A (en) | Array substrate, display panel and electronic equipment | |
| CN105372894A (en) | Array substrate and liquid crystal display device | |
| CN101364020B (en) | Display panel and pixel structure thereof | |
| CN105068344A (en) | Display panel and pixel array thereof | |
| US9625781B2 (en) | Array substrate, display panel and display device | |
| CN105425490A (en) | Array substrate and display device | |
| KR102582755B1 (en) | Pixel structure, array substrate, and display panel | |
| CN112654917A (en) | Display substrate, display device, manufacturing method of display substrate and driving method | |
| CN102169261B (en) | Thin film transistor substrate of liquid crystal display panel | |
| CN104076565A (en) | Array substrate and display device | |
| CN104483788A (en) | Pixel structure and manufacturing method thereof, array substrate, display panel and display device | |
| CN105629605A (en) | Array substrate, LCD (Liquid Crystal Display) panel and LCD device | |
| JP2022503264A (en) | Array board and display device | |
| CN110262689B (en) | Embedded touch display panel and array substrate thereof | |
| CN109061972B (en) | Display panel | |
| CN112689791A (en) | Display substrate and liquid crystal panel | |
| CN207249311U (en) | Array base palte and display device | |
| US20200159360A1 (en) | Display device | |
| CN201532513U (en) | Pixel array and homeotropic alignment LCD panel | |
| JP2013238820A (en) | Liquid crystal display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130417 Termination date: 20210112 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |