CN102163974A - Programmable anti-interference synchronizer trigger - Google Patents
Programmable anti-interference synchronizer trigger Download PDFInfo
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- CN102163974A CN102163974A CN2010106060366A CN201010606036A CN102163974A CN 102163974 A CN102163974 A CN 102163974A CN 2010106060366 A CN2010106060366 A CN 2010106060366A CN 201010606036 A CN201010606036 A CN 201010606036A CN 102163974 A CN102163974 A CN 102163974A
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- hysteresis comparator
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Abstract
The invention discloses a programmable anti-interference synchronizer trigger, which provides a reliable triggering signal for an analogue to digital converter (ADC) sampling system, thereby ensuring the synchronization accuracy of the sampling system. The programmable anti-interference synchronizer trigger comprises a reference point detection comparator, a positive hysteresis comparator and a negative hysteresis comparator, wherein the positive input ends of the reference point detection comparator, the positive hysteresis comparator and the negative hysteresis comparator are connected with one another, and the negative input ends of the reference point detection comparator, the positive hysteresis comparator and the negative hysteresis comparator are connected with one another; nodes of which the positive input ends are connected with one another are connected with an input signal; the output end of the reference point detection comparator is connected with a working power supply by a resistor, and is connected with a control logic circuit by a counter respectively; the output end of the positive hysteresis comparator is connected with one end of a first resistive network and the control logic circuit; the other end of the first resistive network is connected with the positive input end of the positive hysteresis comparator; the first resistive network is grounded by a grounding end, and is connected with the control logic circuit by a port; and the output end of the negative hysteresis comparator is connected with one end of a second resistive network and the control logic circuit.
Description
Technical field
The present invention relates to the triggering technique of sampling system, particularly a kind of jamproof synchronizer trigger able to programme.
Background technology
General sampling system needs triggering system to realize synchronizing process, and is because signal noise superimposed or interference etc. usually can not guarantee that normal single triggers, for changing low frequency signal slowly, particularly outstanding.And for portable set, applied environment is changeable, requires to have stable trigger mechanism to guarantee the synchronizing process of sampling system.Therefore, the inventor thinks, in the measuring system of low frequency, Ultra-low Frenquency Voltage, is necessary to develop a kind of jamproof synchronizer trigger able to programme, for the ADC sampling system provides reliable triggering signal, thus the synchronous accuracy of assurance sampling system.Described ADC (ADC:analog todigital converter) is meant analog to digital converter.
Summary of the invention
The present invention is directed to defective or deficiency that prior art exists, a kind of jamproof synchronizer trigger able to programme is provided, for the ADC sampling system provides reliable triggering signal, thus the synchronous accuracy of assurance sampling system.
Technical scheme of the present invention is as follows:
A kind of jamproof synchronizer trigger able to programme, it is characterized in that, comprise that positive input connects mutually and the interconnective reference point detection comparator of negative input, a positive hysteresis comparator and a negative hysteresis comparator, the node that described positive input connects mutually connects input signal; The output of described reference point detection comparator connects working power by resistance respectively and interconnects by counter and control logic circuit; The output of described positive hysteresis comparator connects an end and the described control logic circuit of first resistor network respectively, the other end of described first resistor network connects the positive input of described positive hysteresis comparator, and described first resistor network connects described control logic circuit by earth terminal ground connection and by port; The output of described negative hysteresis comparator connects an end and the described control logic circuit of second resistor network respectively, the other end of described second resistor network connects the positive input of described negative hysteresis comparator, and described second resistor network connects described control logic circuit by earth terminal ground connection and by port; The interconnective node linking number of described negative input weighted-voltage D/A converter, described digital to analog converter connects described control logic circuit.
Described digital to analog converter output reference point voltage is given the interconnective node of described negative input.
Described input signal forms many trigger impulses string by described rolling counters forward behind described reference point detection comparator, described control logic circuit disposes described first resistor network and second resistor network adjusting sluggish level according to described Counter Value, thereby guarantees the single trigger characteristic of described positive hysteresis comparator and negative hysteresis comparator.
Described first resistor network and second resistor network are by the digital programmable resistor network of pure resistance array and switch composition.
The reference point voltage of described digital to analog converter output disposes arbitrarily by described control logic circuit, thereby realizes digital controllable.
Positive and negative sluggish level digital is by described control logic circuit programming Control.
Technique effect of the present invention is as follows:
(1) this technology detects the trigger impulse number of reference point automatically, and adjusts automatically and trigger sluggish level.
(2) reference center point can dispose arbitrarily, digital controllable.
(3) positive and negative sluggish level digital control able to programme.
(4) practical application effect is: this technology is used for the measuring system of low frequency, Ultra-low Frenquency Voltage, for the ADC sampling system provides reliable triggering signal, has guaranteed the synchronous accuracy of sampling system.
Description of drawings
Fig. 1 is a theory structure schematic diagram of the present invention.
Embodiment
The present invention will be described below in conjunction with accompanying drawing (Fig. 1).
As shown in Figure 1, a kind of jamproof synchronizer trigger able to programme, it is characterized in that, comprise that positive input "+" connects mutually and the interconnective reference point detection comparator CM1 of negative input "-", a positive hysteresis comparator CM2 and a negative hysteresis comparator CM3, the node that described positive input "+" connects mutually connects input signal Vin; The output of described reference point detection comparator CM1 connects working power Vdd by resistance respectively and interconnects by counter and control logic circuit; The output of described positive hysteresis comparator CM2 connects an end and the described control logic circuit of first resistor network respectively, the other end of described first resistor network connects the positive input "+" of described positive hysteresis comparator, and described first resistor network connects described control logic circuit by earth terminal ground connection and by port; The output of described negative hysteresis comparator CM3 connects an end and the described control logic circuit of second resistor network respectively, the other end of described second resistor network connects the positive input "+" of described negative hysteresis comparator, and described second resistor network connects described control logic circuit by earth terminal ground connection and by port; The interconnective node linking number of described negative input "-" weighted-voltage D/A converter DAC (DAC:digitalto analog converter), described digital to analog converter connects described control logic circuit.Described digital to analog converter output reference point voltage Vref is that reference center is put to the interconnective node of described negative input "-".Described input signal Vin forms many trigger impulses string by described rolling counters forward behind described reference point detection comparator CM1, described control logic circuit disposes described first resistor network and second resistor network adjusting sluggish level according to described Counter Value, thereby guarantees the single trigger characteristic of described positive hysteresis comparator CM2 and negative hysteresis comparator CM3.Described first resistor network and second resistor network are by the digital programmable resistor network of pure resistance array and switch composition.The reference point voltage Vref of described digital to analog converter DAC output disposes arbitrarily by described control logic circuit, thereby realizes digital controllable.Positive and negative sluggish level digital is by described control logic circuit programming Control.
The ADC sampling system generally should be made of sampling holder, ADC, controlling of sampling circuit.The triggering signal related with analog input signal starts sampling holder after triggering the controlling of sampling circuit, ADC carries out sample conversion, and with storage or send to data/address bus.Described ADC (ADC:analog to digital converter) is meant analog to digital converter.
Stable trigger mechanism helps guaranteeing the synchronizing process of sampling system.When the input signal that is input to sampling system begins sampling is determined by circuits for triggering that generally the synchronizing process is here promptly controlled the process of sampling starting point.
So-called sluggish level is at comparator, i.e. the rising edge of the trigger impulse of comparator output is inconsistent with corresponding input triggering level with trailing edge.Sluggish level is exactly the level of so-called rising edge and trailing edge correspondence.The implication of de-noising is that noise level is inoperative to triggering because sluggishness exists rather than triggers with noise level repeatedly around central point.Single triggers and is for the oscillator signal around central point triggers repeatedly.
Technical characterstic of the present invention is as follows:
(1) this technology detects the trigger impulse number of reference point automatically, and adjusts automatically and trigger sluggish level;
(2) reference center point can dispose arbitrarily, digital controllable;
(3) positive and negative sluggish level digital control able to programme.
Effect of the present invention is as follows:
This technology is used for the measuring system of low frequency, Ultra-low Frenquency Voltage, for the ADC sampling system provides reliable triggering signal, has guaranteed the synchronous accuracy of sampling system.
Indicate at this, more than narration helps those skilled in the art to understand the invention, but and the protection range of unrestricted the invention.Any do not break away from the invention flesh and blood to being equal to replacement, modify improving and/or deleting numerous conforming to the principle of simplicity and the enforcement carried out of above narration, all fall into the protection range of the invention.
Claims (6)
1. jamproof synchronizer trigger able to programme, it is characterized in that, comprise that positive input connects mutually and the interconnective reference point detection comparator of negative input, a positive hysteresis comparator and a negative hysteresis comparator, the node that described positive input connects mutually connects input signal; The output of described reference point detection comparator connects working power by resistance respectively and interconnects by counter and control logic circuit; The output of described positive hysteresis comparator connects an end and the described control logic circuit of first resistor network respectively, the other end of described first resistor network connects the positive input of described positive hysteresis comparator, and described first resistor network connects described control logic circuit by earth terminal ground connection and by port; The output of described negative hysteresis comparator connects an end and the described control logic circuit of second resistor network respectively, the other end of described second resistor network connects the positive input of described negative hysteresis comparator, and described second resistor network connects described control logic circuit by earth terminal ground connection and by port; The interconnective node linking number of described negative input weighted-voltage D/A converter, described digital to analog converter connects described control logic circuit.
2. jamproof synchronizer trigger able to programme according to claim 1 is characterized in that, described digital to analog converter output reference point voltage is given the interconnective node of described negative input.
3. jamproof synchronizer trigger able to programme according to claim 1, it is characterized in that, described input signal forms many trigger impulses string by described rolling counters forward behind described reference point detection comparator, described control logic circuit disposes described first resistor network and second resistor network adjusting sluggish level according to described Counter Value, thereby guarantees the single trigger characteristic of described positive hysteresis comparator and negative hysteresis comparator.
4. jamproof synchronizer trigger able to programme according to claim 1 is characterized in that, described first resistor network and second resistor network are by the digital programmable resistor network of pure resistance array and switch composition.
5. jamproof synchronizer trigger able to programme according to claim 1 is characterized in that, the reference point voltage of described digital to analog converter output disposes arbitrarily by described control logic circuit, thereby realizes digital controllable.
6. jamproof synchronizer trigger able to programme according to claim 1 is characterized in that positive and negative sluggish level digital is by described control logic circuit programming Control.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010106060366A CN102163974B (en) | 2010-12-24 | 2010-12-24 | Programmable anti-interference synchronizer trigger |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010106060366A CN102163974B (en) | 2010-12-24 | 2010-12-24 | Programmable anti-interference synchronizer trigger |
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| CN102163974A true CN102163974A (en) | 2011-08-24 |
| CN102163974B CN102163974B (en) | 2013-09-25 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103297055A (en) * | 2013-03-19 | 2013-09-11 | 中国科学院声学研究所 | Device for achieving multipath serial ADC synchronization by adopting FPGA |
| CN117978136A (en) * | 2024-04-02 | 2024-05-03 | 深圳市鼎阳科技股份有限公司 | Hysteresis comparator and data acquisition system |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040145927A1 (en) * | 2002-10-29 | 2004-07-29 | Ordwin Haase | DC voltage chopper for DC voltage |
| CN101060320A (en) * | 2006-04-18 | 2007-10-24 | 钰创科技股份有限公司 | Comparator circuit with Schmitt trigger hysteresis character and its method |
-
2010
- 2010-12-24 CN CN2010106060366A patent/CN102163974B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040145927A1 (en) * | 2002-10-29 | 2004-07-29 | Ordwin Haase | DC voltage chopper for DC voltage |
| CN101060320A (en) * | 2006-04-18 | 2007-10-24 | 钰创科技股份有限公司 | Comparator circuit with Schmitt trigger hysteresis character and its method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103297055A (en) * | 2013-03-19 | 2013-09-11 | 中国科学院声学研究所 | Device for achieving multipath serial ADC synchronization by adopting FPGA |
| CN117978136A (en) * | 2024-04-02 | 2024-05-03 | 深圳市鼎阳科技股份有限公司 | Hysteresis comparator and data acquisition system |
| CN117978136B (en) * | 2024-04-02 | 2024-07-02 | 深圳市鼎阳科技股份有限公司 | Hysteresis comparator and data acquisition system |
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| CN102163974B (en) | 2013-09-25 |
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