CN102157455A - 形成用于多晶片集成电路的硅通孔 - Google Patents

形成用于多晶片集成电路的硅通孔 Download PDF

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CN102157455A
CN102157455A CN2011100451159A CN201110045115A CN102157455A CN 102157455 A CN102157455 A CN 102157455A CN 2011100451159 A CN2011100451159 A CN 2011100451159A CN 201110045115 A CN201110045115 A CN 201110045115A CN 102157455 A CN102157455 A CN 102157455A
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CN102157455B (zh
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谢斌
罗珮璁
徐逸杰
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Hong Kong Applied Science and Technology Research Institute ASTRI
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Abstract

本发明提供了一种用于形成三维晶片层叠的方法，该三维晶片层叠具有连续且同质的可导电的层叠通孔，所述层叠通孔具有可变的截面形状。本方法使用至少第一硅晶片和第二硅晶片。每个晶片具有在其上形成的一个或多个集成电路。在每个硅晶片中形成一个或多个通孔，接着在硅晶片的至少上表面和下表面上形成氧化物结构。将晶片对准，以使每个晶片通孔与相邻层叠晶片中对应的通孔对准。接合晶片以形成具有一个或多个层叠通孔的三维晶片层叠，所述一个或多个层叠通孔通过对准各个晶片通孔而形成。通过在每个层叠通孔中沉积金属种子层以执行通孔金属化，接着电镀铜以形成贯通三维晶片层叠的连续且同质的导电通路。

Description

形成用于多晶片集成电路的硅通孔
技术领域
本发明涉及三维集成电路制备，并且更特别地，涉及具有通孔的各个集成电路的接合，在各个集成电路中形成所述通孔之后，接着通孔金属化。
背景技术
随着集成电路尺寸逐步变小，它们正接近物理限度，低于这个物理限度，就不能够装配器件。因此，集成电路的传统的两维模式正经历向三维集成的转变。发展到三维样式有很多艰巨的问题需要克服。首先，大部分集成电路制造技术依赖于以一些方式对晶片表面进行修改来形成部件和导电通路。因此，三维集成将很可能依赖于多个层叠晶片，这些层叠晶片在每个单独的晶片内形成器件。
层叠多个晶片出现了很多问题。为了使多个晶片彼此粘接，晶片必须非常平坦以确保晶片-晶片接触。另一个问题是位于各个晶片上的器件之间的相互连接，这需要垂直金属化以将位于不同晶片上的器件集成起来。
美国专利No.7,385,283描述了一种制备三维集成电路的方法。在这种方法中，将金属相互连接对准，并在晶片层叠期间形成金属-金属接合。同时，在相邻的晶片之间形成非金属-非金属接合。虽然这种技术是一种垂直集成的方法，但是在晶片接合之前对通孔金属化会在晶片接合工序期间产生问题。如果利用加热来接合晶片，金属离子可能会扩散到晶片-晶片接合区域；对于铜通孔金属化，扩散的铜会使附近的器件发生短路。对于硅晶片，铜掺杂形成了深层陷阱，严重地影响整个三维层叠的电性能。如果在接合之前执行化学机械抛光，通孔中金属材料不可能与表面一样平整，导致难以在相邻的金属通孔之间形成金属-金属接合并可能导致器件级之间的“断路”。此外，在每个单独的晶片上执行通孔金属化之后对多晶片通孔接合的需要给整个工序增加了昂贵且耗时的加工步骤。
因此，本领域需要一种改进的技术，以垂直集成晶片，从而形成多层集成电路。
发明内容
本发明提供了一种用于形成三维晶片层叠的方法，该三维晶片层叠具有贯通层叠(“层叠通孔”)的连续且同质的导电通孔，所述层叠可以具有可变的截面形状。本方法使用至少第一硅晶片和第二硅晶片。每个晶片具有在其上形成的一个或多个集成电路。在每个硅晶片中形成一个或多个通孔，接着在硅晶片的至少上表面和下表面上形成氧化物结构。将晶片对准，以使每个晶片通孔与相邻的层叠晶片中对应的通孔对准。接合晶片以形成具有一个或多个层叠通孔的三维晶片层叠，所述一个或多个层叠通孔通过对准各个晶片通孔形成。通过在每个层叠通孔中形成金属种子层(可选地，铜种子层)执行通孔金属化，接着电镀铜以形成贯通三维晶片层叠的连续且同质的导电通路。
附图说明
图1A-1J图示了根据本发明的形成三维晶片层叠的工序，所述三维晶片层叠在通孔内具有连续且同质的导电通路。
图2A-2J图示了根据本发明的另一实施例的形成三维晶片层叠的工序，所述三维晶片层叠在通孔内具有连续且同质的导电通路。
图3A-3B图示了铜种子层溅射工序。
图4A-4B图示了另一个铜种子层溅射工序。
图5A-5D图示了能够根据本发明的工序形成的各个通孔的截面形状。
具体实施方式
详细地参照附图，图1A图示了本发明中形成三维接合晶片层叠的第一硅晶片100。晶片100包括各种部件、金属层、集成电路110等，它们在集成电路制造领域中是已知的并且可以通过任何已知的技术形成。沟槽120通过诸如深反应离子刻蚀(DRIE)的刻蚀工艺生成。在后续工序中，沟槽120将会变成通孔。
在图1B中，利用任何已知的技术，例如等离子增强化学汽相沉积(PECVD)、溅射等，沉积氧化硅层130(例如，二氧化硅)。该材料还覆盖沟槽120的侧壁，以作为通孔中金属材料和器件之间的阻当层。也可以使用其他的隔离材料(例如，聚合物)和沉积技术形成隔离层130。在图1C中，去除氧化硅的一部分，以暴露元件110。在图1D中，沉积金属层140，以将集成电路110与沟槽/通孔120连接。在示例性实施例中，金属是钛钨合金并且通过溅射沉积。金属层还形成防止铜扩散到硅中的阻挡层。硅中沉积铜导致深层陷阱的形成，将会降低电器件性能。也可以使用其他的金属合金和沉积技术来形成层140。
为了把沟槽120变成通孔，在图1E中执行晶片减薄，去除沟槽的底部，产生通孔。去除层140的一部分以隔离一个晶片中的某些相邻通孔之间的电连接。在图1F中，形成另一氧化硅层(例如，二氧化硅)。通过传统技术生长或沉积氧化硅。
在图1G中，去除在通孔120侧壁上形成的氧化硅，暴露出金属层140。因为构成多晶片层叠的晶片应该是非常平坦的，所以在图1H中对至少顶面的氧化硅执行抛光。抛光可以通过本领域中已知的化学、机械或化学-机械技术。
在图1I中，将其上形成有集成电路的多晶片100层叠，以使通孔120的中心对准，在多晶片层叠中形成连续通孔170。接着，金属化这样形成的连续通孔，以形成贯通层叠的均匀的金属通路，并且因为这个连续通孔是在晶片层叠中形成的连续通路，所以被称为“层叠通孔”。在图1I的示例性实施例中，图示了5个晶片100；但是，应该理解两个或多个晶片在本发明的实施例的预料中。因为在每个晶片的上表面和下表面上都出现了氧化物，所以每个晶片氧化物表面接触相邻的晶片氧化物表面。这种结构使晶片能够形成三维晶片层叠。在接合工序中，在相邻层的硅和氧原子之间形成了共价键，在不需要在晶片之间添加接合剂的情况下使晶片与晶片产生了接合。稍稍加热(低于大约200℃)和/或压力帮助接合形成，但是也可以在环境温度下执行接合，例如，利用带有NH4OH的等离子体沾在晶片表面进行预处理。每个晶片对的接合工序时间大约为3-6分钟，这个时间小于常规接合方法的时间。一个优点在于，因为在接合工序期间没有出现铜，就不会出现铜扩散导致的短路问题。此外，低温接合使得多晶片结构中的残余应力最小化。
在接合工序之后，在多晶片层叠通孔170的至少一部分侧壁上形成金属种子层160。可选地，这个金属种子层可以是通过溅射形成的铜种子层，但是也可以使用其他金属种子层材料和方法，例如其他金属的化学镀沉积或者其他通用连接器材料的溅射，如铝。虽然层170以连续的形式示出，但是金属种子层实质上是薄的，沿着通孔侧壁可能会有些中断。如果在铜种子层中有中断，可以通过各种种子层修复工艺来修复这种中断，例如将接合的晶片层叠放到种子层修复溶液中，这种种子层修复溶液具有例如100mg/L含量的钯、2mol/L含量的盐酸、大约30℃的浴槽温度和大约1分钟的浸泡时间。在图1J中，对铜的种子层使用电镀工序，以给层叠孔170填充连续且同质的铜层180。在优选实施例中，铜层180具有均匀的晶格和粒度。
图2图示了根据本发明的另一实施例的形成三维接合晶片层叠的工序。图2A-2H基本上与图1A-1H的工序相似，在这里将不再进一步描述。在图2的工序中，堆叠通孔170的截面可以沿着多晶片层叠的厚度变化。为了改变截面，如图2I中所示，基于通孔中心点，将具有不同通孔尺寸120的各个晶片100对准，即，将通孔的中心对准。用这种方式，可以形成具有各种截面形状的通孔(在图5中更详细地图示)。在图2I中，通过氧化物层150使晶片100相互接合。将例如铜的种子层160溅射到层叠通孔170侧壁的一部分上。在图示的实施例中，仅仅第一晶片接收溅射的铜种子层。在图2J中，使用电镀来给层叠通孔170填充连续且同质的铜层180，优选地，该铜层具有均匀的晶格和粒度。因为仅仅第一晶片接收溅射的铜种子层，所以电镀以“自底向上”方式进行，即，首先将铜沉积在具有铜种子层的部分上，接着向上沉积直到填充整个多晶片层叠通孔。“自底向上”工序可以帮助提高电镀质量并获得无空隙的铜通孔。
图3A-3B和4A-4B分别图示了当包含IC的层面朝上或朝下时，从多层层叠的顶部和从多层层叠的底部溅射的铜种子层。根据方向，晶片120的外表面也在氧化物层150上接收溅射的铜。可以根据外表面铜层的期望位置选择任何技术，外表面铜层可以被图案化并被用作接合焊盘/电极/连接元件。可选地，可以在电镀之后去除外表面上的铜层。
图5A-5D图示了能够根据本发明的通孔中心对准技术形成的各个截面结构。通过对准通孔中心，可以将具有不同截面厚度的通孔120的晶片接合起来，根据多晶片层叠的应用形成任意形状的整个层叠通孔170结构。图5A和5B分别对应于图1J和2J。图5A适合于低和中深宽比应用，而图5B适合于低、中和高深宽比应用，因为它采用了“自底向上”电镀工艺。
图5C图示了适于高深宽比应用的实施例，该应用使层叠通孔170具有“哑铃”截面形状。在图5D中示出了高深宽比应用的另一实施例，该应用使通孔170具有“沙漏”截面形状。对于图5C和5D所示的实施例，因为中间晶片的通孔尺寸小于其他晶片的通孔尺寸，在其他晶片之前就给中间晶片的通孔完全地电镀了铜。接着，同时地沿着多晶片厚度方向向上和向下地沉积铜。因此，高深宽比应用的电镀被转换成低或中深宽比应用的同时电镀。其优点在于，从高深宽比应用到低或中深宽比应用的电镀的转换不仅仅获得了更好的电镀质量，还减少了电镀时间。实质上，高深宽比应用的实施例都可以应用到低或中深宽比应用。
本发明有利地为层叠通孔170形成通孔金属化180，产生具有基本上均匀的晶格和粒度的同质金属层。此外，通过在单个工序中电镀整个通孔，能够获得任意的通孔截面形状，这个任意的形状不可能通过单个晶片通孔到单个晶片通孔接合获得。工艺时间基本上被缩短，并且大大降低了铜扩散导致的短路的风险。本发明随之产生的多晶片层叠非常的薄，部分归因于图1E和2E的晶片减薄。
在电镀之后，可以把多晶片层叠形成为单个半导体元件。如这里所应用的，术语“半导体元件”表示半导体器件或者半导体部件。如果多晶片层叠包括多个半导体元件，可以通过从层叠中分离来形成各个元件。这样的分离可以通过割锯、切块、刻蚀或者其他已知的分离技术进行。在一些实施例中，多晶片层叠形成单个半导体器件或部件。对于这些实施例，实质上在电镀之后完成“形成”单个半导体元件，但是可以包括用来形成最终器件/部件的任何终结技术。
对于所属领域的技术人员而言，本发明的其他优点和修改将会是显而易见的。诸如上述但不限于上述的修改也被考虑在所附权利要求书的范围内。

Claims (17)

1.一种用于垂直地集成多个半导体晶片的方法，每个半导体晶片包括在其上制备的一个或多个集成电路、一个或多个通孔以及电气连接集成电路和通孔的金属层，所述方法包括：
将至少第一硅晶片和第二硅晶片对准，以使第一晶片的一个或多个通孔中的每个通孔中心与第二晶片的对应通孔中的每个通孔中心对准；
接合至少第一硅晶片和第二硅晶片，以形成具有一个或多个层叠通孔的三维晶片层叠，所述一个或多个层叠通孔通过对准至少第一和第二晶片的通孔中心形成；
在一个或多个层叠通孔中的每个通孔的至少一部分上形成金属种子层；
利用金属种子层电镀层叠通孔，以形成贯通三维晶片层叠的连续且同质的导电通路；以及
由三维晶片层叠形成单个三维半导体元件。
2.根据权利要求1所述的方法，还包括：
在未来的通孔位置处，在半导体晶片中刻蚀沟槽；
在每个硅晶片的至少上表面和下表面上形成氧化物层；
形成阻挡层以连接集成电路和未来的通孔并防止金属扩散到硅晶片内；
执行晶片减薄以去除沟槽的底部，产生通孔结构；
在半导体晶片表面上和通孔内侧形成另一氧化物层；
去除通孔侧壁上形成的氧化物层；
对在半导体晶片的至少顶面上形成的氧化物层进行抛光，以确保非常平坦的晶片表面。
3.根据权利要求1所述的方法，其中第一晶片的通孔具有与第二晶片的通孔不同的直径。
4.根据权利要求1所述的方法，其中接合工序是在小于大约200℃的温度执行的低温接合。
5.根据权利要求1所述的方法，其中沿着层叠通孔的厚度方向沉积金属种子层。
6.根据权利要求1所述的方法，还包括接合多个附加的晶片，以形成三维层叠。
7.根据权利要求6所述的方法，其中多个不同的晶片具有不同直径的通孔，以使在接合之后形成的层叠通孔具有任意的截面形状。
8.根据权利要求7所述的方法，其中任意的截面形状是沙漏或哑铃形。
9.根据权利要求1所述的方法，其中同质的金属材料具有均匀的晶格结构和粒度。
10.根据权利要求1所述的方法，其中第一晶片是三维晶片层叠的底部晶片，并且具有比第二晶片的通孔的截面直径小的通孔。
11.根据权利要求10所述的方法，其中仅仅在底部晶片及其通孔上形成铜种子层，并且从三维晶片层叠的底部晶片到顶部晶片进行电镀。
12.根据权利要求1所述的方法，其中通过溅射形成金属种子层。
13.根据权利要求1所述的方法，其中通过将各个半导体元件从晶片层叠分离执行单个半导体元件的形成。
14.根据权利要求13所述的方法，其中所述分离通过割锯执行。
15.根据权利要求1的方法，其中金属种子层是铜。
16.根据权利要求2的方法，其中阻挡层是钛钨合金。
17.一种由权利要求1、8或者10的方法形成的三维半导体元件。
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