CN102157402B - System-in-package method - Google Patents

System-in-package method Download PDF

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Publication number
CN102157402B
CN102157402B CN2011100709175A CN201110070917A CN102157402B CN 102157402 B CN102157402 B CN 102157402B CN 2011100709175 A CN2011100709175 A CN 2011100709175A CN 201110070917 A CN201110070917 A CN 201110070917A CN 102157402 B CN102157402 B CN 102157402B
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China
Prior art keywords
layer
substrate
envelope bed
wiring
package
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Active
Application number
CN2011100709175A
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Chinese (zh)
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CN102157402A (en
Inventor
陶玉娟
石磊
王洪辉
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Tongfu Microelectronics Co Ltd
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Nantong Fujitsu Microelectronics Co Ltd
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Priority to CN2011100709175A priority Critical patent/CN102157402B/en
Publication of CN102157402A publication Critical patent/CN102157402A/en
Priority to PCT/CN2012/072769 priority patent/WO2012126377A1/en
Priority to US13/984,929 priority patent/US9543269B2/en
Application granted granted Critical
Publication of CN102157402B publication Critical patent/CN102157402B/en
Priority to US15/362,625 priority patent/US10741499B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/24146—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the HDI interconnect connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A system-in-package method comprises the steps of: supplying a substrate; forming at least two packaging sets on the substrate, wherein the step of forming the packaging sets comprises forming a placement layer, a material sealing layer and a wiring layer on the substrate in turn; forming a top material sealing layer on the wiring layer of the upper packaging set, and balling under the substrate. The packaging structure formed by the system-in-package method of the invention has relatively high integration.

Description

System-in-a-package method
Technical field
The present invention relates to semiconductor technology, relate in particular to a kind of system-in-a-package method.
Background technology
Along with the development of integrated circuit technique, electronic product is more and more to miniaturization, intellectuality, high-performance and high reliability future development.And integrated antenna package not only directly affects the performance of integrated circuit, electronic module and even complete machine, but also is restricting miniaturization, low cost and the reliability of whole electronic system.Progressively dwindle in the integrated circuit (IC) wafer size, in the situation that integrated level improves constantly, electronics industry has proposed more and more higher requirement to the integrated antenna package technology.
In being the Chinese patent of CN1747156C, notification number discloses a kind of base plate for packaging.Described base plate for packaging comprises: substrate, and described substrate comprises a surface; Be positioned at the pad of receiving on the described substrate surface; Be formed at the welding resisting layer on the described substrate surface, described welding resisting layer comprises at least one opening, and described opening exposes the described pad of receiving; Described base plate for packaging also comprises a pattern metal strengthening course, and described pattern metal strengthening course is formed on the described pad of receiving along the sidewall of described welding resisting layer opening.
Yet along with improving constantly of the compact trend of semiconductor product and product systems functional requirement, the integration that how further to improve system in package becomes those skilled in the art's problem demanding prompt solution.
Summary of the invention
The technical problem that the present invention solves is: provide a kind of system-in-a-package method, to form the higher encapsulating structure of integration.For solving the problems of the technologies described above, a kind of system-in-a-package method comprises: substrate is provided; Form at least two group package group at described substrate, the step that forms described package group comprise form on the substrate successively mount layer, the envelope bed of material, wiring layer; Wiring layer in the superiors' package group forms the top envelope bed of material, plants ball below substrate.
The described step that forms at least two group package group at substrate comprises: attach first at substrate and mount layer; Form the first envelope bed of material with posting the first one side that mounts layer on the substrate; Form the first wiring layer at the first envelope bed of material; Stacking second mounts layer on the first wiring layer; Form the second envelope bed of material that covering second mounts layer at the first envelope bed of material; Form the second wiring layer at the second envelope bed of material.
The described step that mounts layer in substrate attaching first comprises: form cementing layer at described substrate, described cementing layer is used for mounting laminating with first and invests described substrate.
To post the first one side that mounts layer on the substrate when forming the first envelope bed of material, making first, to mount the link of layer exposed.
The step that forms the first wiring layer at the first envelope bed of material comprises: form the first micro through hole in the first envelope bed of material, filled conductive material in the first micro through hole forms the first vertically wiring afterwards; Form the first laterally wiring that connects described first vertical wiring at the first envelope bed of material, wherein, described first vertically wiring be used for realizing being electrically connected between the first package group and other package group and the substrate, described first laterally wiring be used for electrical connection between each device of realization the first package group.
The described layer that mounts comprises chipset.
Described chipset comprises single or multiple chips.
The described layer that mounts also comprises the passive device group, and described passive device group comprises one or more in resistance, electric capacity or the inductance.
The material that described envelope is moulded layer or the described top envelope bed of material is epoxy resin.
Method by metaideophone, compression or printing forms described envelope and moulds layer or the top envelope bed of material.
Compared with prior art, the invention provides a kind of system-in-a-package method, have the following advantages:
The described first envelope bed of material is filled in first and mounts between each device of layer, and the thickness that the thickness of the described first envelope bed of material and first mounts layer is suitable, can reduce respectively to mount the stack thickness of layer, and then improves the integration of encapsulating structure.
Because the envelope bed of material has good insulating properties, can reduce each vertically interference between the wiring.
Description of drawings
Fig. 1 is the schematic flow sheet of system-in-a-package method one execution mode of the present invention;
Fig. 2 to 10 is schematic diagrames of the formed encapsulating structure of system-in-a-package method one embodiment of the present invention;
Figure 11 is the schematic flow sheet of step S102 one embodiment shown in Figure 1.
Embodiment
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can be in the situation that do similar popularization without prejudice to intension of the present invention, so the present invention is not subjected to the restriction of following public implementation.
Secondly, the present invention utilizes schematic diagram to be described in detail, and when the embodiment of the invention was described in detail in detail, for ease of explanation, described schematic diagram was example, and it should not limit the scope of protection of the invention at this.
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
With reference to figure 1, show the schematic flow sheet of system-in-a-package method one execution mode of the present invention, described system-in-a-package method may further comprise the steps:
S101 provides substrate;
S102 forms at least two group package group at substrate;
S103 forms the top envelope bed of material in the superiors' package group;
S104 plants ball below described substrate.
Below in conjunction with accompanying drawing each step is described further.
Execution in step S101 at first, as shown in Figure 2, substrate 101 is provided, substrate 101 is bases of follow-up stacking each package group, simultaneously, it also is the basis of follow-up each layer package group of carrying, described substrate 101 comprises two functional surfaces, wherein, the first surface of described substrate 101 is used for carrying out the stacking of package group, and the second surface of described substrate 101 is used for planting ball (implant and connect ball), in the present embodiment, the upper surface of described substrate 101 is used for carrying out the stacking of package group, and the lower surface of described substrate 101 is used for planting ball, described substrate 101 upper, lower surface is provided with the pad that is electrically connected for realizing.
Wherein, described substrate 101 is generally BT (Bismaleimide Triazine) substrate or PCB (Printed Circuit Board) substrate etc., so that carry out cabling between the first surface of substrate 101 and second surface.
Execution in step S102 with reference to Figure 11, shows the schematic flow sheet of step S102 one embodiment shown in Figure 1, in the present embodiment to form two groups of package group as example at substrate, but the present invention is not restricted to this, and particularly, described step S102 comprises step by step following:
Step S1021 attaches first at substrate and mounts layer;
Step S1022 forms the first envelope bed of material with posting the first one side that mounts layer on the substrate;
Step S1023 forms the first wiring layer at the first envelope bed of material;
Step S1024, stacking second mounts layer on the first wiring layer;
Step S1025 forms the second envelope bed of material that covering second mounts layer at the first envelope bed of material;
Step S1026 forms the second wiring layer at the second envelope bed of material.
Execution in step S1021 as shown in Figure 4, at first forms cementing layer 102 at described substrate 101, and described cementing layer 102 is used for mounting layer 103 with first and is attached at substrate 101, can be by methods such as some glue or printings when forming cementing layer 102 on the substrate 101.Described method is well known to those skilled in the art in field of semiconductor manufacture, does not repeat them here.
Described first mounts layer 103 comprises multiple semiconductor device, in the present embodiment, described first mounts layer 103 comprises the first chipset 105 and the first passive device group 104, and described cementing layer 102 is coated on the substrate 101 position corresponding with the first chipset 105 and the first passive device group 104.
Wherein, described the first chipset 105 can comprise single or multiple chips, and for the embodiment of multiple chips, described multiple chips can be chip not of the same race, each chip is the part of a system in package product, finishes separately the one or more independent function that realizes in the system level function.
Described the first passive device group 104 is and the first chipset 105 common external circuit devices of realizing the system level function of encapsulating products, particularly, comprise in electric capacity, resistance and the inductance one or more, in actual applications, can match according to the design needs.The first passive device group 104 and the first chipset 105 of difference in functionality are combined encapsulation, can realize required system level function.
Need to prove, attach first at described cementing layer 102 and mount layer 103 o'clock, be attached on the cementing layer 102 according to the first supine mode of function that mounts layer 103.In the present embodiment, first mounts layer 103 comprises the first chipset 105 and the first passive device group 104, wherein, functional surfaces in the first chipset 105 is the surface with chip functions pad, the functional surfaces of the first passive device group 104 is the surface that is provided with pad, therefore when attaching the first chipset 105, attach according to chip functions pad mode up; When attaching the first passive device group 104, attach according to pad mode up.
In a preferred embodiment of the present invention, the combination of the first chipset 105 and the first passive device group 104 designs according to systemic-function.Therefore, around the first chipset 105, identical or different the first other chipset 105 may be arranged, perhaps the first passive device groups 104 such as identical or different electric capacity, resistance or inductance; Similarly, around the first passive device group 104, the first passive device group 104 of identical or different other may be arranged, perhaps one or more identical or different the first chipsets 105.
Execution in step S1022, as shown in Figure 5, form the first envelope bed of material 106 with posting the first one side that mounts layer 103 on the substrate, the first link that mounts layer 103 is exposed, in the present embodiment, described link is first to mount the pad of layer 103 chip and the pad of passive device.In the subsequent technique process, the described first envelope bed of material 106 both can have been protected functional surfaces other surfaces in addition of the first chipset 105 and the first passive device group 104, can be used as again the supporting body of subsequent technique.
In one embodiment of the invention, the material of the described first envelope bed of material 106 is epoxy resin.The good seal performance of epoxy resin, plastotype is easy, is the preferred materials that forms the first envelope bed of material 106.Particularly, the method that forms the first envelope bed of material 106 can adopt the method such as metaideophone, compression or printing.The concrete steps of these methods are well known to those skilled in the art, do not repeat them here.
Execution in step S1023, as shown in Figure 6, form the first wiring layer 107 at the first envelope bed of material 106, particularly, described the first wiring layer 107 comprises the first vertically laterally wiring of wiring and first, described first vertically wiring be used for realizing between the first package group and the substrate 101 and the first package group and other package group between be electrically connected, described first laterally wiring be used for electrical connection between each device of realization the first package group.The step of described formation the first wiring layer 107 comprises:
Form first little logically in the first envelope bed of material, filled conductive material in the first micro through hole forms the first vertically wiring afterwards;
Form the first laterally wiring that connects described first vertical wiring at the first envelope bed of material.
Particularly, form described the first micro through hole 107 by the mode of holing, described the first micro through hole 107 runs through the described first envelope bed of material 106, and exposes the pad in the substrate 101, forms with substrate 101 and carries out interconnected passage.Filled conductive material in described the first micro through hole 107 until fill up described the first micro through hole 107, thereby forms the first vertically wiring, continues deposits conductive material at the first envelope bed of material and forms and connect first vertically the first laterally wiring of wiring.In the present embodiment, described first laterally wiring be used for connecting the first chipset 105 and the first passive device group 104, described electric conducting material can be metal, such as copper etc.
In the practical application, can in the envelope bed of material, form selectively vertically wiring according to design requirement, to realize respectively mounting between the layer or to mount electrical connection between layer and the substrate, because the envelope bed of material has good insulating properties, can avoid respectively mounting the interference between each device in the layer.
So far, finished the manufacturing process that forms the first package group at substrate.
Execution in step S1024, described stacking stacking second mounting layer 108 on 106 on the first wiring layer as shown in Figure 7, refer to the second chip layer 108 is placed pre-position on the first envelope bed of material 106.
Need to prove, in the described stacking procedure, mount layer 108 according to the supine mode of function with second and be stacked on the first envelope bed of material 106.Described second mounts layer 108 and first mounts layers 103 similarly, comprises the second chipset and the second passive device group.
Then execution in step S1025 as shown in Figure 8, forms at the first envelope bed of material 106 and to cover second and mount the second envelope bed of material 109 of layer 108, and making second, to mount the pad of the pad of chip of layer 108 and passive device exposed.The material that forms the second envelope bed of material 109 can be identical with the material that forms the first envelope bed of material 106, namely adopts epoxy resin to form the second envelope bed of material 108.
Execution in step S1026, as shown in Figure 9, form the second wiring layer 110 at the second envelope bed of material 109, particularly, described the second wiring layer 110 comprises the second vertically laterally wiring of wiring and second, described second vertically wiring be used for realizing being electrically connected between the second package group and other package group, the substrate 101, described second laterally wiring be used for electrical connection between each device of realization the second package group.The step of described formation the second wiring layer 110 comprises:
Form the second micro through hole in the second envelope bed of material, filled conductive material in the second micro through hole forms the second vertically wiring afterwards;
Form the second laterally wiring that connects described second vertical wiring at the second envelope bed of material.
The method of the method for described formation the second wiring layer 110 and formation the first wiring layer 107 is similar, does not repeat them here.
So far finished the manufacturing process that forms successively the first package group and the second package group at substrate 101, in above-described embodiment take two groups of package group as example, but the present invention is not restricted to this, can also form package group more than two groups at substrate 101, the manufacturing process of other package group and the manufacturing process of above-mentioned package group are similar, do not repeat them here.
Execution in step S103; as shown in figure 10; cover envelope bed of material material at the second wiring layer 110; form the top envelope bed of material 111; the described top envelope bed of material 111 is injury-free for the protection of the second wiring layer 110, and the described top envelope bed of material 111 is identical with the formation method with the material of the described first envelope bed of material 106 and the second envelope bed of material 109.
Execution in step S104, as shown in figure 11, ball is planted in substrate 101 belows, forms to connect ball 112.Particularly, with substrate 101 in be connected the cabling corresponding position and plant ball, the metal of planting ball can adopt the various metals such as metallic tin to form described connection ball 112, the described ball technique of planting is same as the prior art, does not repeat them here.
So far, realized adjacent by wiring layer or interconnected between package group of being separated by between each package group, realized again the integration of system via the circuit arrangement of substrate inside, finally by planting ball with fuction output.
To sum up, the invention provides a kind of system-in-a-package method, can realize that multilayer mounts the encapsulation of layer, the encapsulating structure that forms by system-in-a-package method of the present invention has higher integration.
Although the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can make various changes or modifications, so protection scope of the present invention should be as the criterion with the claim limited range.

Claims (10)

1. a system-in-a-package method is characterized in that, comprising: substrate is provided; Form at least two group package group at described substrate, the step that forms described package group comprise form on the substrate successively mount layer, the envelope bed of material, formation runs through the micro through hole of the described envelope bed of material, the filled conductive material is until fill up micro through hole in the described micro through hole, thereby form vertically wiring, continue deposits conductive material at the described envelope bed of material and form horizontal wiring; Wiring layer in the superiors' package group forms the top envelope bed of material, plants ball below substrate.
2. the system as claimed in claim 1 level packaging methods is characterized in that, the described step that forms at least two group package group at substrate comprises: attach first at substrate and mount layer; Form the first envelope bed of material with posting the first one side that mounts layer on the substrate; Form the first wiring layer at the first envelope bed of material; Stacking second mounts layer on the first wiring layer; Form the second envelope bed of material that covering second mounts layer at the first envelope bed of material; Form the second wiring layer at the second envelope bed of material.
3. system-in-a-package method as claimed in claim 2 is characterized in that, the described step that mounts layer in substrate attaching first comprises: form cementing layer at described substrate, described cementing layer is used for mounting laminating with first and invests described substrate.
4. system-in-a-package method as claimed in claim 2 is characterized in that, will post the first one side that mounts layer on the substrate when forming the first envelope bed of material, and making first, to mount the link of layer exposed.
5. system-in-a-package method as claimed in claim 2, it is characterized in that, the step that forms the first wiring layer at the first envelope bed of material comprises: form the first micro through hole in the first envelope bed of material, filled conductive material in the first micro through hole forms the first vertically wiring afterwards; Form the first laterally wiring that connects described first vertical wiring at the first envelope bed of material, wherein, described first vertically wiring be used for realizing being electrically connected between the first package group and other package group and the substrate, described first laterally wiring be used for electrical connection between each device of realization the first package group.
6. such as the described system-in-a-package method of any claim of claim 1 ~ 5, it is characterized in that, the described layer that mounts comprises chipset.
7. system-in-a-package method as claimed in claim 6 is characterized in that, described chipset comprises single or multiple chips.
8. system-in-a-package method as claimed in claim 6 is characterized in that, the described layer that mounts also comprises the passive device group, and described passive device group comprises one or more in resistance, electric capacity or the inductance.
9. the system as claimed in claim 1 level packaging methods is characterized in that, the material of the described envelope bed of material or the described top envelope bed of material is epoxy resin.
10. system-in-a-package method as claimed in claim 9 is characterized in that, the method by metaideophone, compression or printing forms the described envelope bed of material or the top envelope bed of material.
CN2011100709175A 2011-03-22 2011-03-23 System-in-package method Active CN102157402B (en)

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PCT/CN2012/072769 WO2012126377A1 (en) 2011-03-22 2012-03-22 System-level packaging methods and structures
US13/984,929 US9543269B2 (en) 2011-03-22 2012-03-22 System-level packaging methods and structures
US15/362,625 US10741499B2 (en) 2011-03-22 2016-11-28 System-level packaging structures

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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8592992B2 (en) * 2011-12-14 2013-11-26 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-D Fo-WLCSP
US9064936B2 (en) 2008-12-12 2015-06-23 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US10541228B2 (en) 2017-06-15 2020-01-21 Taiwan Semiconductor Manufacturing Company, Ltd. Packages formed using RDL-last process
CN110634830B (en) * 2019-09-20 2021-11-09 上海先方半导体有限公司 Multi-chip integrated packaging method and structure

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101188232A (en) * 2007-12-19 2008-05-28 日月光半导体制造股份有限公司 Laminated encapsulation structure and its making method
CN101335262A (en) * 2007-06-26 2008-12-31 海力士半导体有限公司 Stack package and method for manufacturing the same
CN101587875A (en) * 2008-05-21 2009-11-25 财团法人工业技术研究院 Vertically electrically connected three-dimensional stacked chip packaging structure and manufacturing method thereof
US7750455B2 (en) * 2008-08-08 2010-07-06 Stats Chippac Ltd. Triple tier package on package system
CN101789420A (en) * 2010-02-03 2010-07-28 南通富士通微电子股份有限公司 System-in-a-package (SIP) structure of semiconductor device and manufacturing method thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100674907B1 (en) * 2003-11-26 2007-01-26 삼성전자주식회사 Stack type semiconductor package having high reliability

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101335262A (en) * 2007-06-26 2008-12-31 海力士半导体有限公司 Stack package and method for manufacturing the same
CN101188232A (en) * 2007-12-19 2008-05-28 日月光半导体制造股份有限公司 Laminated encapsulation structure and its making method
CN101587875A (en) * 2008-05-21 2009-11-25 财团法人工业技术研究院 Vertically electrically connected three-dimensional stacked chip packaging structure and manufacturing method thereof
US7750455B2 (en) * 2008-08-08 2010-07-06 Stats Chippac Ltd. Triple tier package on package system
CN101789420A (en) * 2010-02-03 2010-07-28 南通富士通微电子股份有限公司 System-in-a-package (SIP) structure of semiconductor device and manufacturing method thereof

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Address after: Jiangsu province Nantong City Chongchuan road 226006 No. 288

Patentee after: Tongfu Microelectronics Co., Ltd.

Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288

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