CN102142462B - Power MOS transistor of asymmetric structure and array thereof - Google Patents

Power MOS transistor of asymmetric structure and array thereof Download PDF

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Publication number
CN102142462B
CN102142462B CN201110046602A CN201110046602A CN102142462B CN 102142462 B CN102142462 B CN 102142462B CN 201110046602 A CN201110046602 A CN 201110046602A CN 201110046602 A CN201110046602 A CN 201110046602A CN 102142462 B CN102142462 B CN 102142462B
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grid structure
contact hole
circle
anistree
mos transistor
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CN102142462A (en
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张勇
鲁文高
黄泽
陈博
汤耀云
陈中建
张雅聪
吉利久
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Peking University
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Abstract

The invention provides a power metal oxide semiconductor (MOS) transistor, and belongs to the field of semiconductor devices. The power MOS transistor comprises a source, a drain and a grid structure, wherein the grid structure is specifically designed as: a circle is drawn by using the geometric center of the layout as a circle center, and two sixteen-edge octagonal graphs are made respectively; the edges of the two sixteen-edge octagonal graphs are mutually parallel, a gap between the edges form an octagonal bent belt, and the bent belt is the graph of the grid structure. On the premise of ensuring that the distance between a contact hole of the drain and the grid structure is not changed, the distance between the source and the grid structure is shortened, and smaller layout realization area and lower source connecting metal voltage drop are obtained.

Description

A kind of power MOS transistor of unsymmetric structure and array thereof
Technical field
The present invention relates to a kind of technology of preparing of power field effect transistor, belong to field of semiconductor devices.
Background technology
At present, the ability of (electrostatic discharge) that the mosfet transistor domain that is applied to electric power management circuit requires to have anti-ESD.Therefore in order to bear the big operating current ESD voltage high with opposing, traditional power MOSFET all has relatively large source (S) and leaks (D) size.Yet this will certainly cause bigger chip area.And need bigger metal to do the interconnection between drain electrode or the source electrode, the voltage drop that this can cause excessive metallic resistance to cause again.
Traditional power MOS transistor is to be formed by being displayed on the substrate of many polysilicon gates intervals.Drain region and source region are positioned on the position of polysilicon gate both sides on the substrate separately.Through this kind method, need can be through a plurality of side-by-side reaching in unit with many polysilicon gates through the power MOS transistor device of big electric current.But this device because all there is redundant grid structure sheaf in each unit vertical direction, and needs long bonding jumper to come to connect respectively the source electrode and the drain electrode of MOS crystal, causes excessive metallic resistance pressure drop, so have relatively poor performance.
Fig. 1 is the schematic diagram explanation of existing symmetrical implementation with MOS transistor of esd protection function.This power tube comprises drain electrode (3) zone that is positioned on the substrate, and the grid structure (2) that is positioned on the substrate surrounds the drain electrode (3) that is positioned at the center, and the source electrode (1) that is positioned on the substrate is distributed in grid structure outside composition.But because leaking (3) contact hole, source (1) limits by wherein bigger (the drain terminal metal contact hole is to the distance of grid), so can cause bigger chip area to the distance of grid.
Summary of the invention
The objective of the invention is, same through-current capability with have under the requirement of esd protection effect, have less domain and realize that area is connected the metal pressure drop with less.
The concrete structure of MOS transistor provided by the invention is as shown in Figure 2; Comprise drain electrode (2) zone that is positioned on the substrate, the grid structure (1) that is positioned on the substrate surrounds the drain electrode (2) that is positioned at the center, and the source electrode (1) that is positioned on the substrate is distributed in grid structure outside; The contact hole of esd protection requirement drain electrode (3) is a to the minimum range of grid structure; The contact hole of source electrode (1) is b to the minimum range of grid structure, and the width of grid structure is w, and four contact holes that drain (minimumly can be a contact hole; This moment d=0, we are example with four drain contact holes) minimum dimension and minimum spacing be respectively c and d.Be radius at first with
Figure BDA0000048021890000011
; With the domain geometric center is that justify in the center of circle; Mean allocation gets 8 points on circle then; A, B, C, D, E, F, G and H then connect A, C, E, G and B, D, F, the anistree figure of one ten hexagon of H formation respectively.Same method is a radius with
Figure BDA0000048021890000021
, is that justify in the center of circle (overlapping with the center of circle of a last circle) with the geometric center of domain, and is corresponding with first circle; Also mean allocation gets 8 points, A ', B ', C ' on second circle; D ', E ', F ', G '; And H ', then connect A ', C ', E ' respectively; G ' and B ', D ', F ', H ' form the anistree figure of second ten hexagon.The limit of the anistree figure of concentric two ten hexagons is parallel to each other, and the limit and the gap between the limit of the anistree figure of these two ten hexagons constitute the octagonal bending band of 10 hexagons, are grid structure (2).Outside eight drift angles of the anistree figure of first ten hexagon, place one source pole contact hole structure on angle, every interval, make that the source electrode contact hole is b to the minimum range of grid structure.Source electrode contact hole structure comprises an individuality and draws contact hole and four source electrode contact holes (minimum can be a source class contact hole), because source region (1) has identical electromotive force with tagma (0), can adopt the rule of (BUTTING) back-to-back.
The stepped construction that said grid structure is made up of gate insulation layer and grid.
Said drain electrode comprises or does not comprise suicide block.
The power MOS transistor of a plurality of unsymmetric structures can be formed transistor array, like 2*2 etc.
Technological merit of the present invention and effect:
The grid structure of the power MOS transistor of unsymmetric structure of the present invention has made full use of the power tube source with esd protection function; The drain contact hole is to the different distance requirement of grid; Make near the grid structure of source end outwards outstanding; Grid structure near drain terminal outwards caves in, thereby forms anistree bending band grid structure.The source-drain electrode contact hole is asymmetric to the distance of grid structure.Compare with existing symmetrical structure under drain electrode (3) contact hole prerequisite constant guaranteeing, dwindled the distance of source electrode (1), obtain less domain realization area and be connected the metal pressure drop with less source end to the grid structure to the distance of grid structure.
Description of drawings
Fig. 1 is the schematic diagram explanation of existing symmetrical implementation;
Fig. 2 is a schematic diagram explanation of concrete realization of the present invention;
Fig. 3 is the concrete power tube array (2*2) of realizing of the present invention.
Embodiment
Below in conjunction with through embodiment the present invention being described further, but the present invention is not limited to following examples.
Technology with Chartered semiconductor 0.35um is example.With reference to figure 3; Power MOS transistor ESD requirement, drain contact hole are to the minimum range a=1.7um of grid structure, and the source electrode contact hole is to the minimum range b=0.7um of grid structure; The width w=0.5um of grid structure, the minimum dimension of drain contact hole and minimum spacing are 0.4um.
Concrete realization of the present invention, by above parameter, with:
Figure BDA0000048021890000031
is radius, and the domain geometric center is that circle is done in the center of circle.Do 0 degree then respectively; 45 degree, 90 degree, 135 degree straight lines and circle intersect A, B, C, D, E, F, G and H (135 degree points are A; Clockwise direction marks then), then connect A, C, E, G and B, D, F, two anistree figures one of square ten hexagons that overlap of H formation respectively.Same method, with:
Figure BDA0000048021890000032
is radius; Geometric center with domain is that justify in the center of circle (overlapping with the center of circle of figure one); Do 0 degree then respectively; 45 degree; 90 degree and 135 degree straight lines and circle intersect A ', B ', C ', D ', E ', F ', G ', H ' (135 degree points are A '; Clockwise direction marks then), then connect A ', C ', E ', G ' and B ', D ', F ', two anistree figures two of square ten hexagons that overlap of H ' formation respectively, figure one overlaps mutually the grid structure (2) that must arrive an octagonal bending band with figure two.On figure one 45 degree diagonal and 135 diagonal, place source electrode contact hole structure, make that the source electrode contact hole is b=0.7um to the minimum range of grid structure.Source electrode contact hole structure comprises an individuality and draws contact hole and four source electrode contact holes, because source region (1) has identical electromotive force with tagma (0), can adopt the rule of (BUTTING) back-to-back.
Above-described embodiment is used to limit the present invention, and any those skilled in the art is not breaking away from the spirit and scope of the present invention, can make various conversion and modification, so protection scope of the present invention is looked the claim scope and defined.

Claims (6)

1. a power MOS transistor comprises that one is positioned at the drain region on the substrate, and the grid structure that is positioned on the substrate surrounds
The drain region, and be positioned at source electrode on the substrate be distributed in the grid structure around, it is characterized in that the shape of grid structure specifically is designed to: with R 1 = 2 d 2 + 2 c + 2 a + 2 w = 2 ( d 2 + c + a + w ) Being radius, is that justify in the center of circle with the domain geometric center, and wherein, the contact hole of drain electrode is a to the minimum range of grid structure; The contact hole of source electrode is b to the minimum range of grid structure; The width of grid structure is w; The size dimension of drain contact hole and spacing are respectively c and d; Mean allocation gets 8 points on circle then, and arranged clockwise is respectively A, B, C, D, E, F, G and H, connects A, C, E, G and B, D, F, the anistree figure of first ten hexagon of H formation respectively; Then, the geometric center with domain is the center of circle again, with R 2 = 2 d 2 + 2 c + 2 a = 2 ( d 2 + c + a ) For radius is justified; Corresponding with the 1st circle; Also mean allocation gets A ', B ', C ', D ', E ', F ', G ' and H ' 8 points on the 2nd circle, connects A ', C ', E ', G ' and B ', D ', F ', the anistree figure of second ten hexagon of H ' formation respectively; The limit of the anistree figure of concentric above-mentioned two ten hexagons is parallel to each other; The gap constitutes an octagonal bending band between the limit of the anistree figure of these two ten hexagons and the limit; This bending band is the figure of grid structure; Outside eight drift angles of the anistree figure of first ten hexagon, place one source pole contact hole structure on angle, every interval, outwards cave near the grid structure of drain terminal.
2. power MOS transistor as claimed in claim 1 is characterized in that, the stepped construction that said grid structure is made up of gate insulation layer and grid.
3. power MOS transistor as claimed in claim 1 is characterized in that, said source electrode contact hole structure has comprised body and drawn contact hole, and promptly the source region has identical electromotive force with the tagma, adopts rule back-to-back.
4. power MOS transistor as claimed in claim 1 is characterized in that, said drain electrode comprises or do not comprise suicide block.
5. power MOS transistor array; Comprise several power MOS transistor unit; Each power MOS transistor unit comprises that one is positioned at the drain electrode on the substrate, and the grid structure that is positioned on the substrate surrounds drain electrode, and be positioned at source electrode on the substrate be distributed in the grid structure around; It is characterized in that the shape of grid structure specifically is designed to: with R 1 = 2 d 2 + 2 c + 2 a + 2 w = 2 ( d 2 + c + a + w ) Being radius, is that justify in the center of circle with the domain geometric center, and wherein, the contact hole of drain electrode is a to the minimum range of grid structure; The contact hole of source electrode is b to the minimum range of grid structure; The width of grid structure is w; The size dimension of drain contact hole and spacing are respectively c and d; Mean allocation gets 8 points on circle then, and arranged clockwise is respectively A, B, C, D, E, F, G and H, connects A, C, E, G and B, D, F, the anistree figure of first ten hexagon of H formation respectively; Then, the geometric center with domain is the center of circle again, with R 2 = 2 d 2 + 2 c + 2 a = 2 ( d 2 + c + a ) For radius is justified; Corresponding with the 1st circle; Also mean allocation gets A ', B ', C ', D ', E ', F ', G ' and H ' 8 points on the 2nd circle, connects A ', C ', E ', G ' and B ', D ', F ', the anistree figure of second ten hexagon of H ' formation respectively; The limit of the anistree figure of concentric above-mentioned two ten hexagons is parallel to each other; The gap constitutes an octagonal bending band between the limit of the anistree figure of these two ten hexagons and the limit; This bending band is the figure of grid structure; Outside eight drift angles of the anistree figure of first ten hexagon, place one source pole contact hole structure on angle, every interval, outwards cave near the grid structure of drain terminal.
6. like the said power MOS transistor array of claim 5, it is characterized in that said source electrode contact hole structure has also comprised body and drawn contact hole, promptly the source region has identical electromotive force with the tagma, adopts rule back-to-back.
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CN104899343B (en) * 2014-03-04 2018-07-20 中国科学院上海微***与信息技术研究所 Intersect grid structure MOSFET and multi-fork refers to the layout design of grid structure MOSFET
JP2015204374A (en) * 2014-04-14 2015-11-16 株式会社ジェイテクト semiconductor device
CN106328713A (en) * 2015-06-15 2017-01-11 联想(北京)有限公司 Switch transistor
US10475790B2 (en) * 2017-09-28 2019-11-12 Taiwan Semiconductor Manufacturing Co., Ltd. Asymmetric gate pitch
CN111599807B (en) * 2020-05-22 2023-09-01 赛卓电子科技(上海)股份有限公司 Differential input pair tube for improving performance under standard MOS process and improving method
CN116344530A (en) * 2021-12-24 2023-06-27 长鑫存储技术有限公司 Transistor unit, array thereof and integrated circuit

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US6002156A (en) * 1997-09-16 1999-12-14 Winbond Electronics Corp. Distributed MOSFET structure with enclosed gate for improved transistor size/layout area ratio and uniform ESD triggering
US6140687A (en) * 1996-11-28 2000-10-31 Matsushita Electric Industrial Co., Ltd. High frequency ring gate MOSFET
CN101657901A (en) * 2006-12-28 2010-02-24 马维尔国际贸易有限公司 Geometry of MOS device with low on-resistance

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US6002156A (en) * 1997-09-16 1999-12-14 Winbond Electronics Corp. Distributed MOSFET structure with enclosed gate for improved transistor size/layout area ratio and uniform ESD triggering
CN101657901A (en) * 2006-12-28 2010-02-24 马维尔国际贸易有限公司 Geometry of MOS device with low on-resistance

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