CN102136840B - Self-biased phase-locked loop - Google Patents

Abstract

A kind of self-biased phase-locked loop.Described self-biased phase-locked loop comprises phase frequency detector, charge pump, loop filter, bias generator, voltage controlled oscillator, frequency divider and reference voltage maker, described reference voltage maker generates the reference voltage of the bias current of corresponding voltage controlled oscillator and is supplied to described charge pump, described charge pump is according to described reference voltage regulation output electric current, and the output current of described charge pump equals the bias current of described voltage controlled oscillator generation and the ratio of 2 times of frequency divider divider ratio; Described loop filter at least comprises: the loop filter resistance of series connection and loop filter capacitance, and described loop filter resistance is switching capacity, and the switching frequency of described switching capacity equals the frequency of described input signal.The loop bandwidth of described self-biased phase-locked loop and the ratio of incoming frequency and damping factor will remain fixed value, and circuit is simple.

Description

Self-biased phase-locked loop

Technical field

The present invention relates to phase-locked loop circuit designing technique, particularly self-biased phase-locked loop technology.

Background technology

Along with the development of contemporary microelectric technique, microprocessor and PC/ workstation system dominant frequency and performance improve, and propose more and more higher requirement to the clock forming circuit design of system.And phase-locked loop (PLL, PhaseLockedLoop) is as a kind of conventional designing technique, be widely used in system level chip (SOC, SystemonChip), to form clock forming circuit.

Fig. 1 is a kind of basic structure of phase-locked loop, and phase frequency detector (PFD, PhaseFrequencyDetector) 10 detects input signal F _refwith feedback signal F _fbfrequency difference and difference, produce pulse control signal UP, DN and send into charge pump (CP, chargepump) 20; In charge pump 20, pulse control signal UP, DN are converted into electric current I _pto the electric capacity C of loop filter (LP, LoopFilter) 30 _pcarry out discharge and recharge, loop filter 30 produces control voltage V _ctrlsend into voltage controlled oscillator (VCO, VoltageControlOscillator) 40; Voltage controlled oscillator 40 is at control voltage V _ctrlfrequency of oscillation is accelerated, at control voltage V during rising _ctrlslow down during reduction frequency of oscillation.The output signal F of voltage controlled oscillator 40 _outfeedback signal F is produced through frequency divider 50 _fb, whole phase-locked loop structures forms a reponse system, output signal F _outfrequency and phase place be locked into fixed frequency and phase place.

Damping factor (dampingfactor) ξ of the loop of the phase-locked loop shown in Fig. 1 is represented by formula (1), loop bandwidth ω _nrepresented by formula (2):

$\mathrm{\ξ}=\frac{R_p}{2}\sqrt{\frac{I_p{K}_v{C}_p}{2\mathrm{\ΠN}}}---\left(1\right)$

${\mathrm{\ω}}_n=\sqrt{\frac{I_p{K}_v}{2\mathrm{\Π}{\mathrm{NC}}_p}}---\left(2\right)$

Wherein, C _pfor the electric capacity of loop filter 30, R _pfor the resistance of loop filter 30, I _pfor to electric capacity C _pcarry out the electric current (i.e. the charge or discharge electric current of charge pump 20 output) of charge or discharge, K _vfor the gain of voltage controlled oscillator 40, N is the divider ratio of frequency divider (Divider) 50.

As previously mentioned, propose more and more higher requirement to the clock forming circuit design of system at present, the phase-locked loop thus as clock forming circuit also needs to have high-performance.High-Performance Phase-Locked needs to have following characteristics: be not subject to the impact that technique, voltage and temperature (PVT) change; Bandwidth; Locking after phase jitter (jitter) and frequency change little; Monolithic integrated filter; Circuit low in energy consumption.But reaching these phase-locked loops required is be difficult to design, and a typical phase-locked loop is based on voltage controlled oscillator simultaneously, its phase jitter is caused by power supply and substrate noise, loop is a low pass filter for noise, and loop bandwidth is narrower, shakes less; On the other hand, due to single chip integrated requirement, the electric capacity of filter can not do very large, and bandwidth is subject to again the restriction of loop stability condition simultaneously, and these restrictive conditions make the phase-locked loop operation frequency band of design narrow, and jitter performance is also bad.

Can improve the method that bandwidth can obtain again low jitter, be the bandwidth of change phase-locked loop, enables the operating frequency of following the tracks of phase-locked loop.In each operating state, the smaller bandwidth of loop, shakes also little, but the bandwidth due to phase-locked loop is change, in fact obtains the frequency range of non-constant width, and reduces the phase place and frequency jitter introduced by noise.Automatic biasing is exactly a kind of so method, and adopt the phase-locked loop of automatic biasing method design, the damping factor ξ of its loop is fixed value (usual damping factor is 1).Damping factor ξ, loop bandwidth ω _nwith the angular frequency of input signal _ref(hereinafter referred to as incoming frequency, ω _ref=2 π F _ref, F _reffrequency for input signal) ratio only determined by the relative value of electric capacity in manufacturing process.

Technical literature " Low-JitterProcess-IndependentDLLandPLLBasedonSelf-Biased Techniques " (JohnG.Maneatis, IEEEJOURNALOFSOLID-STATECIRCUITS, VOL.31, NO.11, NOVEMBER1996) a kind of basic structure of self-biased phase-locked loop is disclosed, as shown in Figure 2, electric capacity C ₁form loop filter 31 with bias generator 60, that is, set up the resistance of loop filter 31 by bias generator 60, at the bias voltage V of bias generator 60 _bPoutput add the electric current that an extra charge pump 21 exports, like this, charge pump 20 couples of electric capacity C ₁carry out discharge and recharge, the resistance that charge pump 21 pairs of bias generator 60 are set up carries out discharge and recharge.

Bias generator 60 is for from control voltage V _cTRLgenerate bias voltage V _bPand V _bN, to provide the input voltage of voltage controlled oscillator 41.As shown in Figure 3, bias generator 60 comprises biased initialization (BiasInit.) circuit 601, amplifier biasing (AmplifierBias) circuit 602, differential amplification (Diff.Amplifier) circuit 603, half buffered copy (Half-BufferReplica) circuit 604 and control voltage buffering (V _cTRLbuffer) circuit 605.Amplifier bias circuit 602 provides biased for differential amplifier circuit 603, and differential amplifier circuit 603 regulates bias voltage V _bN, make half buffer replica circuits 604 and control voltage buffer circuit 605 by control voltage V _cTRLcopy to the bias voltage V of output _bP, i.e. V _bP=V _cTRL.

Shown in Fig. 1, the voltage controlled oscillator 40 of basic phase-locked loop is normally made up of the buffer stage of multiple differential configuration, and the voltage controlled oscillator 41 of self-biased phase-locked loop shown in Fig. 2 is with the differential buffer delay stages of balanced load to form by n (n >=2), the voltage controlled oscillator 41 of differential buffer delay stages 410 formation of such as, 3 band balanced loads shown in Fig. 4.Bias voltage V _bNfor balanced load 411,412 provides bias current 2I _d(I _dfor flowing through the electric current of balanced load 411 or 412), the bias voltage V of balanced load 411,412 _bPequal control voltage V _cTRL, the equivalent resistance of balanced load 411,412 equals 1/2g _m, g _mfor the mutual conductance of a transistor in balanced load, along with control voltage V _cTRLchange, the resistance of balanced load 411,412 changes, and the time delay of buffer stage also changes, and the frequency of the output signal (CK+ or CK-) of voltage controlled oscillator 41 changes.

If the electric current I that charge pump 20,21 exports _pfor the bias current 2I of voltage controlled oscillator 41 _dx doubly, i.e. I _p=x2I _dif, the resistance R of the loop filter 31 that balanced load 606 is set up in bias generator 60 _pfor the equivalent resistance R of the buffer stage 410 of voltage controlled oscillator 41 _oy doubly, i.e. R _p=yR _o=y/2g _m.Therefore, the damping factor ξ of the loop of the self-biased phase-locked loop shown in Fig. 2 is represented by formula (3), loop bandwidth ω _nwith incoming frequency ω _refratio represented by formula (4):

$\mathrm{\ξ}=\frac{y}{4}\sqrt{\frac{x}{N}}\sqrt{\frac{C_1}{C_B}}---\left(3\right)$

$\frac{{\mathrm{\ω}}_n}{{\mathrm{\ω}}_{\mathrm{ref}}}=\frac{\mathrm{xN}}{2\mathrm{\π}}\sqrt{\frac{C_B}{C_1}}---\left(4\right)$

Wherein, C _bit is the parasitic capacitance of voltage controlled oscillator 41.

Like this, from ideal situation, if the ratio ω of ξ and loop bandwidth and incoming frequency _n/ ω _refbe all constant, loop bandwidth can follow the tracks of operating frequency all the time, and phase-locked loop does not just limit for operating frequency.But, notice from formula (3) and (4), the ratio ω of damping factor ξ and loop bandwidth and incoming frequency _n/ ω _refalso relation is there is with the ratio of the equivalent resistance of the buffer stage of the ratio of the divider ratio N of frequency divider in phase-locked loop 50, charge pump output current and voltage controlled oscillator bias current, loop filter resistance and voltage controlled oscillator.Therefore, the damping factor ξ of phase-locked loop and the ratio ω of loop bandwidth and incoming frequency _n/ ω _refcannot only by electric capacity C in manufacturing process _b, C ₁relative value determine.

In addition, prior art self-biased phase-locked loop as shown in Figure 2 needs to arrange 2 charge pumps and carries out discharge and recharge to the resistance of loop filter and electric capacity respectively, correspondingly, and the circuit realiration also more complicated of self-biased phase-locked loop.

Summary of the invention

The problem that the present invention solves provides a kind of self-biased phase-locked loop, to simplify circuit, and obtains the ratio of more stable damping factor and loop bandwidth and incoming frequency, improve the performance of self-biased phase-locked loop.

For solving the problem, the invention provides a kind of self-biased phase-locked loop, comprising:

Phase frequency detector, detects frequency difference and the difference of input signal and feedback signal, produces pulse control signal;

Charge pump, produces charge or discharge electric current according to the pulse control signal that described phase frequency detector exports;

Loop filter, is connected with charge pump, exports control voltage, and when charge pump exports charging current, described loop filter raises control voltage; When charge pump exports discharging current, described loop filter reduces control voltage;

Bias generator, the control voltage produced from loop filter generates the first bias voltage and the second bias voltage;

Voltage controlled oscillator, comprise the oscillating unit of band balanced load, described balanced load is controlled by the first bias voltage, the frequency of oscillation of output signal is accelerated when the first bias voltage raises, the frequency of oscillation of the output signal that slows down when the first bias voltage reduces, described voltage controlled oscillator also produces bias current according to the second bias voltage;

Frequency divider, carries out frequency division by the output signal of voltage controlled oscillator, produces the feedback signal of the described phase frequency detector of input,

Wherein, described self-biased phase-locked loop also comprises reference voltage maker, is connected with voltage controlled oscillator and charge pump, and described reference voltage maker generates the reference voltage of the bias current of corresponding described voltage controlled oscillator; Described charge pump is according to described reference voltage regulation output electric current, and the output current of described charge pump equals the ratio of the bias current of described voltage controlled oscillator and 2 times of frequency divider divider ratio; Described loop filter at least comprises: the loop filter resistance of series connection and loop filter capacitance, and described loop filter resistance is switching capacity, and the switching frequency of described switching capacity equals the frequency of described input signal.

Compared with prior art, above-mentioned self-biased phase-locked loop has the following advantages: by arranging the bias current of switching capacity and charge pump output current and voltage controlled oscillator, the relation of frequency divider divider ratio, cancellation divider ratio, the ratio of charge pump output current and voltage controlled oscillator bias current, the impact of the factors such as the equivalent resistance of the buffer stage of loop filter resistance and voltage controlled oscillator, make ratio and the damping factor of loop bandwidth and incoming frequency, all only relevant with the electric capacity of loop filter to the parasitic capacitance of voltage controlled oscillator, namely once manufacturing process determines the parasitic capacitance of voltage controlled oscillator and the electric capacity of loop filter, the ratio of loop bandwidth and incoming frequency and damping factor will remain fixed value.Therefore, the stability of self-biased phase-locked loop is better.

Further, due to the resistance with switching capacity equivalent substitution, then as the charge pump of loop filter front stage circuits, the charging and discharging currents that loop filter provides a road total is only need to.Correspondingly, the front stage circuits of loop filter only needs a charge pump, thus simplifies the circuit of phase-locked loop.

Accompanying drawing explanation

Fig. 1 is the basic structure schematic diagram of a kind of phase-locked loop of prior art;

Fig. 2 is the basic structure schematic diagram of a kind of self-biased phase-locked loop of prior art;

Fig. 3 is the circuit diagram of the bias generator of the self-biased phase-locked loop shown in Fig. 2;

Fig. 4 is the circuit diagram of the voltage controlled oscillator of the self-biased phase-locked loop shown in Fig. 2;

Fig. 5 is a kind of execution mode circuit diagram of self-biased phase-locked loop of the present invention;

Fig. 6 is a kind of embodiment circuit diagram of self-biased phase-locked loop loop filter of the present invention;

Fig. 7 is the another kind of embodiment circuit diagram of self-biased phase-locked loop loop filter of the present invention.

Embodiment

The present invention is intended to realize by replacing the equivalence of resistance in loop filter, and set up charge pump output current, the bias current of voltage controlled oscillator and the relativeness of divider ratio, with the ratio of the equivalent resistance of the buffer stage of the ratio of cancellation divider ratio, charge pump output current and voltage controlled oscillator bias current, loop filter resistance and voltage controlled oscillator.

Specifically, the output current of charge pump in phase-locked loop is pressed following formula foundation and the bias current of voltage controlled oscillator, the relation of frequency divider divider ratio by the present invention:

$I_p=\frac{I_D}{2N}---\left(5\right)$

And known for those skilled in the art, the gain of voltage controlled oscillator meets:

$K_v=\frac{k}{C_B}---\left(6\right)$

Wherein, k is the process factor of device in voltage controlled oscillator.

Then, formula (5), (6) are substituted into formula (2) and can obtain

${\mathrm{\ω}}_n=\sqrt{\frac{I_d}{4\mathrm{\Π}{N}^2}*\frac{1}{C_p}*\frac{k}{C_B}}---\left(7\right)$

Formula (7) is converted

${\mathrm{\ω}}_n=\sqrt{\frac{{2I}_D}{8\mathrm{\Π}{N}^2}*\frac{1}{C_p}*\frac{k}{C_B}}---\left(8\right)$

And known for those skilled in the art, the output frequency of voltage controlled oscillator meets:

$F_{\mathrm{VCO}}=\frac{\sqrt{2k{I}_D}}{C_B}---\left(9\right)$

Wherein, F _vCOfor the output frequency of voltage controlled oscillator.

Formula (9) is converted

$k=\frac{F_{\mathrm{VCO}}*F_{\mathrm{VCO}}*{C_B}^2}{2I_D}---\left(10\right)$

Formula (10) is substituted into formula (8) obtain

${\mathrm{\ω}}_n=\sqrt{\frac{F_{\mathrm{VCO}}*F_{\mathrm{VCO}}}{8\mathrm{\Π}{N}^2}*\frac{C_B}{C_p}}---\left(11\right)$

And known for those skilled in the art, meet between the frequency input signal of the output frequency of voltage controlled oscillator and the divider ratio of frequency divider, phase-locked loop:

F _VCO＝NF _ref(12)

And the frequency of described input signal meets:

ω _ref＝2∏F _ref(13)

Formula (12), formula (13) are substituted into formula (11),

${\mathrm{\ω}}_n=\frac{{\mathrm{\ω}}_{\mathrm{ref}}}{2\mathrm{\Π}}\sqrt{\frac{C_B}{8\mathrm{\Π}{C}_p}}---\left(14\right)$

Then according to formula (14), the ratio of loop bandwidth and incoming frequency is

$\frac{{\mathrm{\ω}}_n}{{\mathrm{\ω}}_{\mathrm{ref}}}=\sqrt{\frac{C_B}{32{\mathrm{\Π}}^3{C}_p}}---\left(15\right)$

Particularly, the present invention also in loop filter with the resistance in switching capacity equivalent substitution loop filter, then loop filter is resistor satisfied:

$R_p=\frac{1}{F_{\mathrm{ref}}*C_s}---\left(16\right)$

Wherein, C _sfor the capacitance of switching capacity.

Formula (16) is substituted into formula (1),

$\mathrm{\ξ}=\frac{1}{2F_{\mathrm{ref}}*C_s}\sqrt{\frac{I_p{K}_v{C}_p}{2\mathrm{\ΠN}}}---\left(17\right)$

Formula (5), formula (10), formula (12) are substituted into formula (17), obtains damping factor

$\mathrm{\ξ}=\frac{1}{4C_s}\sqrt{\frac{C_B*C_p}{2\mathrm{\Π}}}---\left(18\right)$

Thus as can be seen from formula (15), formula (18), the ratio of loop bandwidth and incoming frequency and damping factor, all only with the parasitic capacitance C of voltage controlled oscillator _bwith the electric capacity C of loop filter _prelevant, namely once manufacturing process determines the parasitic capacitance C of voltage controlled oscillator _bwith the electric capacity C of loop filter _p, the ratio of loop bandwidth and incoming frequency and damping factor will remain fixed value.Therefore, the stability of self-biased phase-locked loop is better.

Further, due to the resistance with switching capacity equivalent substitution, then as the charge pump of loop filter front stage circuits, the charging and discharging currents that loop filter provides a road total is only need to.Correspondingly, the front stage circuits of loop filter only needs a charge pump, thus simplifies the circuit of phase-locked loop.

Below by way of accompanying drawing and specific embodiments of the present invention is described in detail in conjunction with above-mentioned analysis.Fig. 5 is a kind of execution mode circuit diagram of self-biased phase-locked loop of the present invention.With reference to shown in Fig. 5, described self-biased phase-locked loop comprises: phase frequency detector 1, charge pump 2, loop filter 3, bias generator 4, voltage controlled oscillator 5, frequency divider 6 and reference voltage maker 7.

Phase frequency detector 1, detects input signal F _refwith feedback signal F _fbfrequency difference and difference, produce pulse control signal UP, DN.Such as, at feedback signal F _fbphase place lag behind input signal F _reftime, the pulse duration of pulse control signal UP is greater than the pulse duration of pulse control signal DN; At feedback signal F _fbphase place be ahead of input signal F _reftime, the pulse duration of pulse control signal UP is less than the pulse duration of pulse control signal DN.The circuit of phase frequency detector 10 is well known to those skilled in the art, and does not launch explanation at this.

Charge pump 2, produces charge or discharge electric current I according to pulse control signal UP, DN that phase frequency detector 1 exports _p.Wherein, at feedback signal F _fbphase place lag behind input signal F _reftime, the pulse duration of pulse control signal UP is greater than the pulse duration of pulse control signal DN, and charge pump 2 exports charging current I _p; At feedback signal F _fbphase place be ahead of input signal F _reftime, the pulse duration of pulse control signal UP is less than the pulse duration of pulse control signal DN, and charge pump 2 exports discharging current I _p.The reference voltage V that described charge pump 2 provides according to reference voltage maker 7 _refthe charging current of regulation output or the size of discharging current, the size of described charging current or discharging current meets formula (5).

Loop filter 3, is connected with charge pump 2, exports control voltage V _ctr, loop filter 3 comprises differential switched capacitor and the loop filter capacitance C of series connection _p.Wherein, described differential switched capacitor comprises: the first electric capacity C10 being controlled by the first K switch 10, and the second electric capacity C12 being controlled by second switch K12, and two electric capacity one end are connected to the output of charge pump 2, and the other end is connected to loop filter capacitance C _pfirst end.Loop filter capacitance C _pthe second end ground connection.Total capacitance value after described first electric capacity C10 and the second electric capacity C12 parallel connection is C _s.Described first K switch 10 and second switch K12 are all controlled by switch clock ck.Charging current I is exported at charge pump 2 _ptime, described loop filter 3 raises control voltage V _ctr; Discharging current I is exported at charge pump 2 _ptime, described loop filter 3 reduces control voltage V _ctr.

Bias generator 4, from the control voltage V that loop filter 3 produces _ctrgenerate the first bias voltage V _bPwith the second bias voltage V _bN, to provide the input voltage of voltage controlled oscillator 5.The physical circuit of described bias generator 4 realizes same as the prior art, can refer to the circuit realiration of Fig. 3.

Voltage controlled oscillator 5, comprises the oscillating unit of band balanced load, the second bias voltage V _bNfor balanced load provides bias current 2I _d(I _dfor flowing through the electric current of balanced load), the first bias voltage V of balanced load _bPequal control voltage V _ctr, the equivalent resistance of balanced load equals 1/2g _m, g _mfor the mutual conductance of a transistor in balanced load, along with control voltage V _ctrchange, the first bias voltage V _bPalso change, the resistance of balanced load changes, the output signal F of voltage controlled oscillator 5 _vcofrequency change.Particularly, output signal F is accelerated when the first bias voltage raises _vcofrequency of oscillation, first bias voltage reduce time slow down output signal F _vcofrequency of oscillation.

Reference voltage maker 7, generates the reference voltage V of the bias current that corresponding voltage controlled oscillator 5 produces _refand be supplied to charge pump 2, the I in the size of described reference voltage and formula (5) _pcorresponding.

The output signal F of voltage controlled oscillator 4 _vcofeedback signal F is produced through frequency divider 6 _fb, i.e. F _fb=F _out/ N, N are the divider ratio of frequency divider 6, and whole system forms a reponse system, output signal F _vcofrequency and phase place be locked into fixed frequency and phase place.

Fig. 6 is a kind of embodiment circuit diagram of self-biased phase-locked loop loop filter of the present invention.With reference to shown in Fig. 6, described loop filter comprises: the first transmission gate TG1, the second transmission gate TG2, the 3rd transmission gate TG3 and the 4th transmission gate TG4, the first electric capacity C10, the second electric capacity C12 and the first NMOS tube MN1, the second NMOS tube MN2.

Described first transmission gate TG1, described second transmission gate TG2 are respectively as the switch controlling described first electric capacity C10, described second electric capacity C12.Two control ends of described first transmission gate TG1 receive the first switching signal F respectively ₁with the first switch complementary signal F _1B, two outputs are connected to first end and second end of described first electric capacity C10.Two control ends of described second transmission gate TG2 receive second switch signal F respectively ₀with second switch complementary signal F _0B, two outputs are connected to first end and second end of described second electric capacity C12.

Two control ends of the 3rd transmission gate TG3 receive second switch signal F respectively ₀with second switch complementary signal F _0B, two control ends of the 4th transmission gate TG4 receive the first switching signal F respectively ₁with the first switch complementary signal F _1Bfirst output of the 3rd transmission gate TG3 and the 4th transmission gate TG4 is connected, and being connected to electric charge delivery side of pump, second output of the 3rd transmission gate TG3 and the 4th transmission gate TG4 is connected to the first end of the first electric capacity C10 and the first end of the second electric capacity C12.Described first switching signal F ₁with second switch signal F ₀complementary signal each other, and frequency and input signal F _reffrequency identical.3rd transmission gate TG3 and the 4th transmission gate TG4 forms differential configuration herein, to improve the noiseproof feature of described loop filter.

In the specific embodiment of above-mentioned transmission gate, transmission gate comprises PMOS and the NMOS tube of the connection of source and drain correspondence, and the breadth length ratio of described PMOS is 2 times of the breadth length ratio of NMOS tube.

The grid of the first NMOS tube MN1 and the second NMOS tube MN2 is all connected to second end of the first electric capacity C10, the second electric capacity C12, and the equal ground connection of source electrode, drain electrode and substrate, to connect into capacitive form.

Circuit shown in analysis chart 6, controlled by above-mentioned each switching signal, make the first electric capacity C10 and the second electric capacity C12 in parallel and be connected to the grid of described first NMOS tube MN1 and the second NMOS tube MN2 with a fixed frequency, according to formula (16), then the capacitive reactance that formed afterwards of now the first electric capacity C10 and the second electric capacity C12 parallel connection can the function of equivalent substitution resistance.

In the another kind of execution mode of self-biased phase-locked loop of the present invention, described loop filter also add the 3rd electric capacity relative to structure shown in Fig. 5, and one end of described 3rd electric capacity is connected to the second end that the electric charge delivery side of pump other end is connected to loop filter capacitance.Increase by the 3rd electric capacity and achieve further filtering, the ability that described loop filter suppresses high-frequency noise can be increased further.

Fig. 7 is a kind of embodiment circuit diagram of the loop filter of corresponding described another kind of execution mode.With reference to shown in Fig. 6 and Fig. 7, relative to the loop filter structure of Fig. 6, Fig. 7 increase only the 3rd NMOS tube MN3.The grid of described 3rd NMOS tube MN3 is connected to electric charge delivery side of pump, and the equal ground connection of source electrode, drain electrode and substrate, to connect into capacitive form.

In sum, the present invention passes through with switching capacity equivalent substitution resistance, and set up charge pump output current, with the bias current of voltage controlled oscillator, the relation of frequency divider divider ratio, thus make the loop bandwidth of self-biased phase-locked loop and the ratio of incoming frequency and damping factor, all only relevant with the electric capacity of loop filter to the parasitic capacitance of voltage controlled oscillator, and simplify circuit.

Disclosed above many aspects of the present invention and execution mode, it will be understood by those skilled in the art that other side of the present invention and execution mode.Many aspects disclosed in the present invention and execution mode are just for illustrating, be not limitation of the invention, real protection range of the present invention and spirit should be as the criterion with claims.

Claims (8)

1. a self-biased phase-locked loop, comprising:

Phase frequency detector, detects frequency difference and the difference of input signal and feedback signal, produces pulse control signal;

Charge pump, produces charge or discharge electric current according to the pulse control signal that described phase frequency detector exports;

Loop filter, is connected with charge pump, exports control voltage, and when charge pump exports charging current, described loop filter raises control voltage; When charge pump exports discharging current, described loop filter reduces control voltage;

Bias generator, the control voltage produced from loop filter generates the first bias voltage and the second bias voltage;

Voltage controlled oscillator, comprise the oscillating unit of band balanced load, described balanced load is controlled by the first bias voltage, the frequency of oscillation of output signal is accelerated when the first bias voltage raises, the frequency of oscillation of the output signal that slows down when the first bias voltage reduces, described voltage controlled oscillator also produces bias current according to the second bias voltage;

Frequency divider, carries out frequency division by the output signal of voltage controlled oscillator, produces the feedback signal of the described phase frequency detector of input,

It is characterized in that, described self-biased phase-locked loop also comprises reference voltage maker, is connected with voltage controlled oscillator and charge pump, and described reference voltage maker generates the reference voltage of the bias current of corresponding described voltage controlled oscillator; Described charge pump is according to described reference voltage regulation output electric current, and the output current of described charge pump equals the ratio of the bias current of described voltage controlled oscillator and 2 times of frequency divider divider ratio; Described loop filter at least comprises: the loop filter resistance of series connection and loop filter capacitance, and described loop filter resistance is switching capacity, and the switching frequency of described switching capacity equals the frequency of described input signal;

Described switching capacity comprises: the first transmission gate, the second transmission gate, the 3rd transmission gate and the 4th transmission gate, the first electric capacity, the second electric capacity, wherein,

Described first transmission gate, described second transmission gate are respectively as the switch controlling described first electric capacity, described second electric capacity, two control ends of described first transmission gate receive the first switching signal and the first switch complementary signal respectively, two outputs are connected to first end and second end of described first electric capacity, two control ends of described second transmission gate receive second switch signal and second switch complementary signal respectively, and two outputs are connected to first end and second end of described second electric capacity; Second end of described first electric capacity, the second end of the second electric capacity are all connected to the first end of described loop filter capacitance;

Two control ends of the 3rd transmission gate receive second switch signal and second switch complementary signal respectively, two control ends of the 4th transmission gate receive the first switching signal and the first switch complementary signal respectively, first output of the 3rd transmission gate and the 4th transmission gate is connected, and being connected to electric charge delivery side of pump, the second output of the 3rd transmission gate and the 4th transmission gate is connected to the first end of the first electric capacity and the first end of the second electric capacity;

Described first switching signal and second switch signal complementary signal each other, and frequency is identical with the frequency of input signal.

2. self-biased phase-locked loop as claimed in claim 1, it is characterized in that, described loop filter capacitance comprises the first NMOS tube and the second NMOS tube, and the grid of the first NMOS tube and the second NMOS tube is all connected to the second end of the first electric capacity, the second electric capacity, the equal ground connection of source electrode, drain electrode and substrate.

3. self-biased phase-locked loop as claimed in claim 1 or 2, it is characterized in that, described loop filter also comprises the 3rd electric capacity, and one end of described 3rd electric capacity is connected to the second end that the electric charge delivery side of pump other end is connected to loop filter capacitance.

4. self-biased phase-locked loop as claimed in claim 3, it is characterized in that, described 3rd electric capacity comprises the 3rd NMOS tube, and the grid of described 3rd NMOS tube is connected to electric charge delivery side of pump, the equal ground connection of source electrode, drain electrode and substrate.

5. self-biased phase-locked loop as claimed in claim 1, it is characterized in that, described bias generator comprises the biased initializing circuit, amplifier bias circuit, differential amplifier circuit, half buffer replica circuits and the control voltage buffer circuit that connect successively.

6. self-biased phase-locked loop as claimed in claim 1, it is characterized in that, described first bias voltage equals described control voltage.

7. self-biased phase-locked loop as claimed in claim 1, is characterized in that, the oscillating unit of band balanced load is the differential buffer delay circuit of band balanced load.

8. self-biased phase-locked loop as claimed in claim 7, is characterized in that, described voltage controlled oscillator comprises the differential buffer delay circuit of 3 band balanced loads.