CN102111127A - Signal count delay method and circuit in chip electrifying process - Google Patents
Signal count delay method and circuit in chip electrifying process Download PDFInfo
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- CN102111127A CN102111127A CN 200910243494 CN200910243494A CN102111127A CN 102111127 A CN102111127 A CN 102111127A CN 200910243494 CN200910243494 CN 200910243494 CN 200910243494 A CN200910243494 A CN 200910243494A CN 102111127 A CN102111127 A CN 102111127A
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Abstract
The invention relates to the field of the reliability of chips, in particular to a signal count delay method in a chip electrifying process. The method increases the reliability of circuit count delay time by improving a conventional chip electrifying delay count circuit. The method is specifically implemented by the following steps of: delaying a plurality of signals by using a counter in the chip electrifying process; extracting marks of a plurality of count values from the count values of a delay counter; stopping counting by using the counter only when the extracted mark values are counted by using the counter; and generating a delayed signal after the counter stops. By adopting the method, the guarantee of the count values of the delay counter when the chip is electrified abnormally can be increased, and the reliability when the chip is electrified abnormally can be remarkably improved.
Description
Technical field
The invention belongs to the chip reliability field, be specifically related to the reliability of chip when improper mode power-on and power-off.
Background technology
Along with informationalized development, electronic product occupies more and more important role in daily life.The problem that the reliability of these electronic products has become people to be concerned about very much, reliability concentrated expression characteristics such as durability of products, fault-free, validity and its usage economy, be an important quality index of product.Vitals in the electronic product that chip is carried as the individual, unconsciously, more and more every aspects that are applied in people's life.The extensive use of chip makes its reliability be paid close attention to greatly by people.
In the application of chip, there are some abominable applied environments or nonstandard operation, some improper power-on and power-off situations appear.If the chip reliability design is good inadequately, the influence of improper damaging property of power-on and power-off meeting.
The reliable design that postpones of internal signal was when chip was tackled improper power-on and power-off operation in the past: some key signal in the power up is carried out digital delay with simple counter, internal power source voltage was stable when the signal after postponing was effective, entire chip brings into operation then, guarantees the stability of moving behind the chip power in this way.There is certain problem in simple counter delay in the such scheme when improper power-on and power-off, following description: when the chip due to abnormal electrifying, powering on, the voltage of internal standard unit does not also reach normal operational voltage value when finishing, but this hour counter is started working, it is unusual that improper operating voltage can make counter works occur, cause counter not write all count values all over and very fast arrival counting terminal point, thereby builtin voltage does not also arrive the normal working voltage value when causing chip to be started working, and low excessively voltage makes the execution of CPU cause confusion and chip is caused a devastating effect.
Along with the development of semiconductor technology, how to guarantee that chip chip reliability when improper power-on and power-off becomes to become increasingly conspicuous to dark nanometer direction.The present invention has improved the counting reliability of chip power hour counter greatly by the decision procedure of improving counter and rolling counters forward, and the safety of chip internal data when improper power-on and power-off is protected.
Summary of the invention
The improving one's methods of the used digit counter of inner power up key signal delay when the object of the present invention is to provide a kind of chip due to abnormal electrifying improved chip safety of data in the card when improper power-on and power-off.Simultaneously, the present invention can also reduce the power consumption of circuit by the clock signal of closing counter register after rolling counters forward is finished.
In order to realize the purpose of foregoing invention, technical scheme provided by the present invention is described in detail as follows:
A kind of circuit of chip power process signal count delay, its circuit comprise counter circuit, count tag circuit, mark treatment circuit, the clock gating circuit that improves counting mode.The operation principle of entire circuit be during by the chip due to abnormal electrifying delay counter through the counting median of all settings, thereby can guarantee count delay time long enough, avoided when due to abnormal electrifying is worked rolling counters forward result inaccurate and gate time that cause is significantly less than the situation of expection.
The above-mentioned said chip that comprises various applications.
The above-mentioned said key signal delay counter that powers on, its concrete circuit form can be any type of counter, the common counter that adds the improved procedure of mentioning among 1 device or the present invention.The counter of improved procedure is by simplifying the combinational logic complexity in the counter circuit, guaranteed that counter can normally be counted under the low pressure condition under the chip exterior clock, included two kinds of forms: linear feedback shift register (LFSR) and asynchronous counter.
Above-mentioned said count tag circuit is made of comparator circuit and flag register two parts.Wherein comparator circuit is the condition that produces flag register set, produces the counting condition of this flag register if the counter meter has been a counting track numerical value that sets in advance.The effect of flag register circuit is to indicate that the counter meter crosses the counting median of all settings.
Above-mentioned said mark treatment circuit is a logical circuit, and its input is the output of all flag registers, and output is the signal after postponing.
The effect of above-mentioned said clock gating circuit is that the clock of all registers is to save power consumption in the shut-off circuit after rolling counters forward postpones to finish, and the gate type can be two kinds.A kind of is and the gateable clock gating circuit that purpose is to allow the clock signal of counter register and flag register be parked in low level; Another kind is or the gateable clock gating circuit that purpose is to allow the clock signal of counter register and flag register be parked in high level.
A kind of method of chip power process signal count delay, utilize circuit in this method can significantly improve chip safety of data in the card when improper power-on and power-off, strengthen chip reliability greatly, guaranteed the application safety of chip under various mal-conditions.
Description of drawings
Fig. 1 overall circuit structure chart
Fig. 2 linear feedback shift register circuit principle sketch
Fig. 3 asynchronous counter principle sketch
Fig. 4 count tag circuit diagram
Embodiment
Below in conjunction with Figure of description the specific embodiment of the present invention is further described.
Fig. 1 is an overall construction drawing of the present invention.The concrete workflow of entire circuit is, counter begins counting after input signal is invalid, in the counter works process, if the count tag circuit was provided with corresponding marker bit automatically when counter values was remembered of set count tag median, signal after the mark treatment circuit produces final delay automatically after all marker bits all are changed to effectively, signal after the delay is given subsequent control circuit in the card, and the signal after this postpones is simultaneously also delivered to clock gating circuit and is used for turn-offing the clock of counter register and the clock of flag register.
The problem of common count delay when being example explanation chip power with the count delay of chip power reset signal below.When the chip due to abnormal electrifying, its external terminal signal begins effectively.Because the electrification reset level in the chip is general all well below the operate as normal level of internal standard unit, the level of power-on reset signal generally also can only keep tens microseconds, when due to abnormal electrifying speed is slow, but exist the invalid back of electrification reset delayed management counter to start working and block the situation that builtin voltage does not reach the logical block normal working voltage, the result can cause the rolling counters forward confusion and make counter count end very early.Voltage when above-mentioned situation can make card system reset invalid in the card does not reach normal working voltage and causes CPU to carry out confusion.
In the said process, the logical circuit between the common counter register is long, and it is very high to occur unusual situation probability under the low pressure.When specifically implementing, the present invention can select the simple counter of some logical circuits for use, two kinds of counters as shown in Figures 2 and 3, be respectively linear feedback shift register and asynchronous counter, combinational logic path between the register is very little, and the reliability than common rolling counters forward under identical low voltage operating condition is higher.
Count tag is the pith of content of the present invention, and Fig. 3 has described the principle of a count tag generation circuit in a plurality of flag registers.Comparator produces the set condition of flag register, and when counter had been remembered the numerical value identical with the value that sets in advance, the corresponding flag register of meeting set can be remained valid after the flag register set always.The mark treatment circuit has all been delivered in the output of all flag registers.
The principle of mark treatment circuit is, must wait until just to discharge after all marker bits all are set in the flag register and give subsequent conditioning circuit, could guarantee the requirement that the delay counter time is minimum like this.
The purpose of clock gating circuit is to save the circuit dynamic power consumption for clock signal that the counting that powers on is closed the clock signal of counter register and flag register after finishing reaches.
The enforcement of above-mentioned detailed circuit scheme among the present invention can effectively strengthen the reliability of chip when improper power-on and power-off operation, and the dynamic power consumption of delay circuit when powering on can reduce chip operation the time.
Claims (5)
1. the method for a chip power process signal count delay, it is characterized in that this method uses a group echo register to strengthen the reliability of power up signal delay rolling counters forward, have only all flag registers all to be set, counter just stops counting, produces the signal after postponing.
2. the circuit of a chip power process signal count delay is characterized in that this circuit is made up of counter, count tag circuit, mark treatment circuit and clock gating circuit, wherein:
When described counter is realized chip power to the delay counter function of source signal;
Described count tag circuit is made up of comparator circuit and flag register circuit, and comparator produces the set condition of flag register, when counter has been remembered the numerical value identical with the value that sets in advance, and the corresponding flag register of set.
The function that signal after described mark treatment circuit is realized postponing produces, the mark treatment circuit is delivered in the output of all count tag circuit;
Described Clock gating is closed the clock signal of register in the entire circuit to save power consumption after counting is finished.
3. the circuit of a kind of chip power process signal count delay as claimed in claim 2 is characterized in that the count tag value that is provided with can be the arbitrary value in the rolling counters forward numerical value.
4. the circuit of a kind of chip power process signal count delay as claimed in claim 2, the number that it is characterized in that flag register is an arbitrary value.
5. the circuit of a kind of chip power process signal count delay as claimed in claim 2 is characterized in that after all count tags all are set, and the signal controlling that postpones the back generation is closed the clock of counter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910243494 CN102111127B (en) | 2009-12-23 | 2009-12-23 | Signal count delay method and circuit in chip electrifying process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN 200910243494 CN102111127B (en) | 2009-12-23 | 2009-12-23 | Signal count delay method and circuit in chip electrifying process |
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| CN102111127A true CN102111127A (en) | 2011-06-29 |
| CN102111127B CN102111127B (en) | 2013-05-15 |
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| CN 200910243494 Active CN102111127B (en) | 2009-12-23 | 2009-12-23 | Signal count delay method and circuit in chip electrifying process |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105790739A (en) * | 2015-01-12 | 2016-07-20 | 英飞凌科技股份有限公司 | Protected Switching Element |
| CN109917887A (en) * | 2019-03-06 | 2019-06-21 | 深圳芯马科技有限公司 | A kind of digital reset circuit applied to MCU chip |
| CN116961628A (en) * | 2023-09-21 | 2023-10-27 | 浙江力积存储科技有限公司 | Method and device for realizing fixed delay time |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5708817A (en) * | 1995-05-31 | 1998-01-13 | Apple Computer, Inc. | Programmable delay of an interrupt |
| CN1308789C (en) * | 2002-01-29 | 2007-04-04 | 中兴通讯股份有限公司 | Reset method |
| CN101350612B (en) * | 2007-07-16 | 2010-08-04 | 北京中电华大电子设计有限责任公司 | Circuit for preventing gating clock bur |
| CN101149636B (en) * | 2007-10-23 | 2010-07-07 | 华为技术有限公司 | Repositioning system and method |
-
2009
- 2009-12-23 CN CN 200910243494 patent/CN102111127B/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105790739A (en) * | 2015-01-12 | 2016-07-20 | 英飞凌科技股份有限公司 | Protected Switching Element |
| CN109917887A (en) * | 2019-03-06 | 2019-06-21 | 深圳芯马科技有限公司 | A kind of digital reset circuit applied to MCU chip |
| CN116961628A (en) * | 2023-09-21 | 2023-10-27 | 浙江力积存储科技有限公司 | Method and device for realizing fixed delay time |
| CN116961628B (en) * | 2023-09-21 | 2023-12-19 | 浙江力积存储科技有限公司 | Method and device for realizing fixed delay time |
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| Publication number | Publication date |
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| CN102111127B (en) | 2013-05-15 |
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Address after: 102209 Beijing, Beiqijia, the future of science and technology in the south area of China electronic network security and information technology industry base C building, Patentee after: Beijing CEC Huada Electronic Design Co., Ltd. Address before: 100102 Beijing City, Chaoyang District Lize two Road No. 2, Wangjing science and Technology Park A block five layer Patentee before: Beijing CEC Huada Electronic Design Co., Ltd. |