CN102098061B - Parallel Turbo coder - Google Patents
Parallel Turbo coder Download PDFInfo
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- CN102098061B CN102098061B CN200910201488.3A CN200910201488A CN102098061B CN 102098061 B CN102098061 B CN 102098061B CN 200910201488 A CN200910201488 A CN 200910201488A CN 102098061 B CN102098061 B CN 102098061B
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Abstract
The invention discloses a parallel Turbo coder, which comprises a parallel inner interleaver, a first member coder and a second member coder, wherein the parallel inner interleaver comprises an interleaving address generator and two interleaving buffers alternately serving as a read buffer and a write buffer, each interleaving buffer comprises a plurality of storage units for storing corresponding bits, and the plurality of storage units output parallel system bit stream and parallel interleaving bit stream under the control of control signals generated by the interleaving address generator according to the corresponding bits; the first member coder performs parallel coding on the parallel system bit stream to generate first parity check bit stream; and the second member coder performs coding on the parallel interleaving stream to generate second parity check bit stream. The Turbo coder of the embodiment of the invention has higher throughput rate and shorter waiting time.
Description
Technical field
The present invention relates to Turbo coding, be specifically related to a kind of parallel Turbo coder.
Background technology
Due to time become fading channel and interference and noise and so on, in wireless transmission process, the reliability of wireless signal has reduced.In wireless communication system, channel coding schemes adopts error correction coding mechanism to ensure the reliability of transmission conventionally.Turbo coding has been chosen as the main channel coding schemes of LTE system by 3GPP.Turbo code is using convolution code as its member's code, and introduced interleaver, to reduce correlation.Because Turbo code can meet the Stochastic Conditions of Shannon channel coding theorem, use iterative encoding scheme, the performance of Turbo code can approach shannon limit in theory.In LTE, the encoding scheme of Turbo encoder is the Parallel Concatenated Convolutional Code (PCCC) that uses two 8 state constituent encoders and a Turbo code interleaver.The code rate of Turbo encoder is 1/3.Fig. 1 shows according to the structure of the Turbo encoder of prior art.As described in Figure 1, this encoder comprises Turbo code interleaver 20 and the first constituent encoder 10 and the second constituent encoder 30, and each constituent encoder adopts serial code structure.The transfer function of the 8 state member codes that use in PCCC in addition, is as follows:
Wherein g
0(D)=1+D
2+ D
3, g
1(D)=1+D+D
3, D represents the register in constituent encoder.
The bit input table that is input to Turbo encoder is shown c
0, c
1, c
2, c
3..., c
k-1, the bit output of the first and second 8 state constituent encoders is expressed as z
0, z
1, z
2, z
3..., z
k-1and z '
0, z '
1, z '
2, z '
3..., z '
k-1.The bit output of Turbo code interleaver is expressed as c '
0, c '
1, ..., c '
k-1and these bits will be imported into the 28 state constituent encoder.
Fig. 2 shows according to the structural representation of the Turbo encoder of prior art.As shown in Figure 2, interleaver 20 comprises current interweave buffer 0 and the buffer 1 that interweaves as read buffer as write buffer, represents respectively with Reference numeral 21 and 22.In addition, interleaver 20 also comprises interleaving address generator 23, for generation of interleaving address.Like this, interleaver 20 utilizes interlacing rule from incoming bit stream, to obtain systematic bits stream and interleaved bitstream.Systematic bits stream is called Parity Check Bits stream 1 by the first constituent encoder 10 codings, and interleaved bitstream is encoded into Parity Check Bits stream 2 by the second constituent encoder 30.Parity Check Bits stream 1, Parity Check Bits stream 2 and systematic bits stream are used as the output of encoder.
Due to the use of many antennas MIMO and 64QAM modulation technique, LTE system is supported the burst down link peak data rate up to 300Mb/s in the downstream spectrum of 20MHz is distributed, and the stand-by period of user plane is less than 5ms.In future, LTE-Advanced system will be supported up to data rate for downlink more than 1Gbps in the spectrum allocation may of 100MHz.In addition, many telecom operators require a baseband board can realize the processing of eNodeB (NodeB of evolution) Zhong Duo community.Need to develop powerful Turbo encoder, it can process the data of Gbps.
Traditional implementation structure of Turbo encoder is to adopt single-bit encoding scheme.In a signal clock cycle, only there is an input bit for Turbo encoder, bit of processing and three output bits including a systematic bits and two Parity Check Bits.
The subject matter of this Turbo encoder is lower code efficiency.Even if use the FPGA of clock rate up to 2-300MHz, in each clock cycle, always only have 3 output bits, Turbo encoder is per second can only process 2-300M Bit data.Clearly, traditional single-bit Turbo encoder can not meet the throughput requirement of LTE system.Therefore, need to improve the implementation structure of Turbo encoder.
Summary of the invention
The object of the invention is to propose a kind of parallel Turbo coder, to improve the throughput of communication system.
One aspect of the present invention has proposed a kind of parallel Turbo coder, comprise: parallel interleaver, comprise interleaving address generator and alternately serve as two buffers that interweave of read buffer and write buffer, each buffer that interweaves includes the multiple memory cell for storing corresponding bit, under the control of the control signal that described multiple memory cell produces for corresponding bits at described interleaving address generator, output parallel system bit stream and parallel interleaved bitstream; The first constituent encoder, carries out parallel encoding to parallel system bit stream, produces the first Parity Check Bits stream; The second constituent encoder, encodes to parallel weaving flow, produces the second Parity Check Bits stream.
According to embodiments of the invention, described parallel interleaver is QPP interleaver.
According to embodiments of the invention, described interleaving address generator is based on adder and subtracter and form.
According to embodiments of the invention, described the first constituent encoder and the second constituent encoder are formed parallel encoding structure.
According to embodiments of the invention, each memory cell comprises two-port RAM.
According to embodiments of the invention, each memory cell has public read/write control signals and independently read/write address and data-signal.
According to embodiments of the invention, described interleaving address generator comprises Part I and Part II, and wherein Part I is responsible for the calculating of difference sequence, and the Output rusults of Part II based on Part I calculates interleaved sequence.
According to the Turbo encoder of the embodiment of the present invention there is higher throughput and the stand-by period shorter.
In addition, the scheme of the embodiment of the present invention is applicable to the communication system of high-throughput.In the scheme of the embodiment of the present invention, traditional Turbo encoder is replaced with parallel Turbo coder, can in a clock cycle, be processed multiple bits.
Brief description of the drawings
By below in conjunction with brief description of the drawings the preferred embodiments of the present invention, will make of the present invention above-mentioned and other objects, features and advantages are clearer, wherein:
Fig. 1 shows according to the structure of the Turbo encoder of prior art;
Fig. 2 shows according to the structural representation of the Turbo encoder of prior art;
Fig. 3 shows according to the general illustration of the parallel Turbo coder of the embodiment of the present invention;
Fig. 4 shows according to the interleaver memory structure in the parallel Turbo coder of the embodiment of the present invention;
Fig. 5 shows according to the structure of the interleaving address generator of the embodiment of the present invention;
Fig. 6 shows according to the concrete structure of the interleaving address generator of the embodiment of the present invention;
Fig. 7 shows according to the serial structure of the constituent encoder of prior art;
Fig. 8 shows according to the parallel organization of the constituent encoder of the embodiment of the present invention.
Embodiment
Various embodiments of the present invention will be described below.Explanation subsequently provides the detail of the complete understanding to these embodiment.But those skilled in the art should understand, also can implement the present invention without details described in some.In addition, may not can illustrate or describe in detail some known structure or functions, in order to avoid unnecessarily make the related description of various embodiments of the present invention unclear.
Even the term using is combined with the detailed description of some specific embodiment of the present invention, also to explain this term with its widest rational method in following explanation.Some term may be emphasized below. still, the term that any preparation makes an explanation in certain limited mode will disclose and clear and definite definition in embodiment part.
According to embodiments of the invention, a kind of parallel Turbo coder structure is proposed.The parallel Turbo coder of the embodiment of the present invention can be processed multiple bits in a clock cycle, thereby has greatly improved code efficiency.In a clock cycle, the Turbo encoder of the embodiment of the present invention can receive multiple input bits, multiple bits are interweaved and the processing of encoding, and produce multiple output groups (each group comprises a systematic bits and two Parity Check Bits).For the object clearly demonstrating, structure and the operating process of the Turbo encoder of the embodiment of the present invention are described as an example of parallel processing 4 bits example in an embodiment of the present invention.
If system clock is 250MHz, can reach 1Gbps according to the theoretical throughput of the Turbo encoder of the embodiment of the present invention, this can meet the throughput requirement of multiple eNodeB.Comprise a parallel interleaver and two parallel constituent encoders according to the Turbo encoder of the embodiment of the present invention, and parallel interleaver comprises two interweave buffer and interleaving address generators.
Fig. 3 shows according to the structural representation of the Turbo encoder of the embodiment of the present invention.As shown in Figure 3, this encoder comprises the parallel interleaver 100 that receives parallel bit stream and it is carried out to parallel processing, comprises the constituent encoder of the first constituent encoder 210 and the second constituent encoder 220.
Parallel interleaver 100 comprises interweave buffer 0 and the buffer 1 that interweaves, they are expressed as 110 and 120, alternately serve as read buffer and write buffer, and each buffer comprises multiple memory cell, the number of memory cell equals the number of the bit of parallel processing.Parallel interleaver 100 also comprises parallel interleaving address generator, and Fig. 6 shows the concrete structure of this address generator.
1. the parallel organization of interleaver
Turbo encoder in LTE system adopts QPP (Quadratic PermutationPolynomial) interleaver as its interleaver.The table of bits that is input to Turbo code interleaver is shown c
0, c
1..., c
k-1, wherein K is the number of input bit.Be shown c ' from the table of bits of Turbo code interleaver output
0, c '
1..., c '
k-1.
Relation between input bit and output bit can be expressed as:
c′
i＝c
∏(i)，i＝0，1，…，(K-1)
Wherein, the relation between output index i and input index ∏ (i) meets following formula:
∏(i)＝(f
1·i+f
2·i
2)mod?K
Wherein, parameter f
1and f
2depend on block size K, and have a detailed description in 3GPP TS 36.212, the document this by reference to and all introduce.
Traditional Turbo interleaver is serial interleaver, and it comprises a buffer and an interleaving address generator, and in a clock cycle, exports a bit, as shown in Figure 2.The Turbo encoder of 3GPPLTE system selects QPP interleaver as its interleaver, and it has without contention characteristic.The structural change of interleaver can be become can in a clock cycle, process the parallel organization of multiple bits.
The structure of the 1.1 parallel buffers that interweave
In order to process continuous code block, and without any interruption, adopt " table tennis " buffer according to the parallel interleaver of the embodiment of the present invention.Therefore,, even the untreated end of current code block, interleaver also can receive next code block.Each buffer 110 and 120 comprises 4 memory cell, and each memory cell is actually two-port RAM.Each memory cell has public read/write control signals and independently read/write address and data-signal.Fig. 4 shows according to the structural representation of the interleaver using in the parallel Turbo coder of the embodiment of the present invention.The data of input, after demodulation multiplexer demultiplexing, are stored in corresponding buffer memory cell, need to read when being formed as a code block completing time, from corresponding memory cell, read, and output after multiplexer is multiplexing.
" table tennis " buffer can be expressed as read buffer and write buffer.Read buffer has formed a complete code block, and write buffer does not also have.Read buffer is by the bit stream output interweaving, and write buffer receives the bit stream of input simultaneously.The operation relevant to read/write buffers is called as read/write operation.
Read operation: read buffer produces two output bit flows---systematic bits stream and interleaved bitstream.From each memory cell, read a bit, the parallel system bit stream of composition 4 bits.Another bit is read in the address of calculating according to interleaving address generator from each memory cell, the interleaved bitstream of composition 4 bit widths.In the time that current code block is all read from read buffer, read buffer is just converted to write buffer.
Write operation: control logic is separated 4 input bits and each bit is write in corresponding memory cell.In the time that a code block is written in write buffer completely, write buffer is converted to read buffer.
The structure of 1.2 parallel interleaving address generators
According to the relation between incoming bit stream and output bit flow, what interleaving address generator calculated each memory cell reads address and control signal.Similar with the structure of the buffer that interweaves, interleaving address generator also comprises 4 unit, and address generate is responsible for reading accordingly in each unit.
Fig. 5 shows according to the structural representation of the interleaving address generator of the embodiment of the present invention.If adjacent element has formed another sequence that is called as difference sequence in interleaving address sequence.Due to the particularity of QPP interleaver, difference sequence is arithmetic (equal difference) sequence.Be based on the recognition, it is very effective calculating whole interleaved sequence with iteration structure.According to the parameter f of current code block
1, f
2, K, first the initialization module that interweaves produces initial value.Left part in Fig. 6 is responsible for the calculating of difference sequence, and the Output rusults of right side part based on left part calculates interleaved sequence.
The iteration structure of interleaving address generator comprises adder and subtracter, instead of complicated multiply operation.In addition, the iterative structure in the embodiment of the present invention for parallel realize more convenient.
2, the structure of parallel constituent encoder
Turbo encoder comprises constituent encoder and a Turbo code interleaver Parallel Concatenated Convolutional Code (PCCC) of two 8 states.The transfer function of 8 state constituent encoders is as follows:
Wherein, g
0(D)=1+D
2+ D
3, g
1(D)=1+D+D
3.D represents the register in constituent encoder.
The traditional structure of constituent encoder is serial.In a clock cycle, receive a bit, and only produce an output bit.Fig. 7 shows the traditional structure of constituent encoder.
Fig. 8 shows according to the structural representation of the constituent encoder of the embodiment of the present invention.Parallel organization as shown in Figure 8 can receive multiple input bits in a clock cycle, and multiple output bits are compiled and produced to multiple bits.Can greatly improve code efficiency according to the scheme of the embodiment of the present invention.
According to the Turbo encoder of the embodiment of the present invention there is higher throughput and the stand-by period shorter.The scheme of the embodiment of the present invention is applicable to the communication system of high-throughput.In the scheme of the embodiment of the present invention, traditional Turbo encoder is replaced with parallel Turbo coder, can in a clock cycle, be processed multiple bits.
According to embodiments of the invention, a kind of Turbo encoder that can process multiple bits in a clock cycle is proposed.In a clock cycle, can receive multiple input bits according to the Turbo encoder of the embodiment of the present invention, process multiple bits and produce multiple output groups.Than traditional single-bit Turbo encoder, the function of the parallel Turbo coder of the embodiment of the present invention is very powerful, can meet the throughput requirement of LTE system to Turbo encoder.In addition, the parallel organization of the Turbo encoder of the embodiment of the present invention is one structure cheaply, can reduce the consumption of the resource to baseband board and the cost of reduction baseband board.
Unless context explicitly calls for, otherwise the implication that " comprising ", " comprising " etc., similar word should be interpreted as comprising in whole specification and claims, instead of exclusive or exhaustive implication; That is to say, be the implication of " comprise, but be not limited to ".The term " connection ", " coupling " or its modification that here used, mean between two or more element and connect directly or indirectly or coupling; Butt coupling between element can be physically, in logic or its combination.
In addition, word " here ", " above-mentioned ", " below " using in the application and the word that contains similar meaning should relate to the application's full content, instead of the application's specific part.In the time that context allows, in above-mentioned embodiment, use the word of odd number or plural number also can comprise respectively plural number or odd number.About the word of two or more option list " or " covered all following explanation of this word: the discretionary choices in list, the total Options in list, and the combination in any of option in list.
The above-mentioned detailed description of the embodiment of the present invention be not exhaustive or for limit the present invention to above-mentioned clear and definite in form.With schematic object, specific embodiment of the present invention and example are described although above-mentioned, those skilled in the art will recognize that and can carry out within the scope of the invention various equivalent modifications.
The enlightenment that the application here provided not is must be applied in said system, can also be applied in other system.Can combine to provide more embodiment by the element of above-mentioned various embodiment and effect.
Can modify to the present invention according to above-mentioned detailed description.Although above-mentioned declarative description specific embodiment of the present invention and described anticipated optimal set pattern, no matter there is hereinbefore how detailed explanation, can implement the present invention by many modes.The details of above-mentioned bucking-out system is carried out in details and can be carried out considerable variation at it, but it is still included in the present invention disclosed herein.
It should be noted that as described above that the specific term using in the time of explanation some feature of the present invention or scheme should not be used for being illustrated in redefines this term here with restriction of the present invention some certain features, feature or the scheme relevant to this term.In a word, should be not disclosed specific embodiment in limiting the invention to specification by the terminological interpretation using in the claims of enclosing, unless above-mentioned detailed description part defines these terms clearly.Therefore, actual range of the present invention not only comprises the disclosed embodiments, also comprises according to claims and implements or carry out all equivalents of the present invention.
Claims (7)
1. a parallel Turbo coder, comprising:
Parallel interleaver, comprise interleaving address generator and alternately serve as two buffers that interweave of read buffer and write buffer, each buffer that interweaves includes the multiple memory cell for storing corresponding bit, under the control of the control signal that described multiple memory cell produces for corresponding bits at described interleaving address generator, output parallel system bit stream and parallel interleaved bitstream;
The first constituent encoder, carries out parallel encoding to parallel system bit stream, produces the first Parity Check Bits stream;
The second constituent encoder, encodes to parallel weaving flow, produces the second Parity Check Bits stream.
2. encoder according to claim 1, wherein said parallel interleaver is twice replaced polynomial interleaver.
3. encoder according to claim 1, wherein said interleaving address generator is based on adder and subtracter and form.
4. encoder according to claim 1, wherein said the first constituent encoder and the second constituent encoder are improved to parallel encoding structure.
5. encoder according to claim 1, wherein each memory cell comprises two-port RAM.
6. encoder according to claim 1, each memory cell has public read/write control signals and independently read/write address and data-signal.
7. encoder according to claim 1, wherein said interleaving address generator comprises Part I and Part II, wherein Part I is responsible for the calculating of difference sequence, and the Output rusults of Part II based on Part I calculates interleaved sequence.
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| WO2019218130A1 (en) * | 2018-05-15 | 2019-11-21 | 深圳市大疆创新科技有限公司 | Turbo encoding method, turbo encoder and unmanned aerial vehicle |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6134694A (en) * | 1996-02-29 | 2000-10-17 | Ntt Mobile Communications Network, Inc. | Error control method and error control device for digital communication |
| CN1277494A (en) * | 1999-06-11 | 2000-12-20 | 阿尔卡塔尔公司 | Method of coding for information element using product code in application of satellite |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6134694A (en) * | 1996-02-29 | 2000-10-17 | Ntt Mobile Communications Network, Inc. | Error control method and error control device for digital communication |
| CN1277494A (en) * | 1999-06-11 | 2000-12-20 | 阿尔卡塔尔公司 | Method of coding for information element using product code in application of satellite |
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Address after: 201206 Pudong New Area, Nanjing Road, No. 388, Shanghai Patentee after: Shanghai NOKIA Baer Limited by Share Ltd Address before: 201206 Pudong New Area, Nanjing Road, No. 388, Shanghai Patentee before: Shanghai Alcatel-Lucent Co., Ltd. |