WO2019149180A1

WO2019149180A1 - Interleaving method and interleaving device

Info

Publication number: WO2019149180A1
Application number: PCT/CN2019/073575
Authority: WO
Inventors: 刘荣科; 冯宝平; 王桂杰
Original assignee: 华为技术有限公司
Priority date: 2018-01-30
Filing date: 2019-01-29
Publication date: 2019-08-08
Also published as: CN110098891A; CN110098891B

Abstract

Provided by the present application are an interleaving method capable of improving random interleaving performance of an interleaving device without increasing interleaving complexity. The method comprises: generating a first interleaving matrix according to the N first bit sequences, the first matrix being 1×1, indicating rounding up to an integer; performing a first cyclic shift on the first matrix according to a first cyclic shift sequence to obtain a second matrix, wherein the first cyclic shift sequence comprises J bits, and J ≥ 2 and is an integer; performing a second cyclic shift on the second matrix according to a second cyclic shift sequence to obtain a third matrix, wherein the second cyclic shift sequence comprises S bits, and S ≥ 2 and is an integer; obtaining N second bit sequences according to the third matrix; and outputting the second bit sequences.

Description

交织方法和交织装置Interleaving method and interleaving device

本申请要求于2018年1月30日提交中国国家知识产权局、申请号为201810087141.X、申请名称为“交织方法和交织装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。This application claims priority to Chinese Patent Application No. 201810087141.X, filed on January 30, 2018, with the application name of "interlacing method and interleaving device", the entire contents of which are incorporated herein by reference. In the application.

技术领域Technical field

本申请涉及信道编码领域，尤其涉及一种交织方法和交织装置。The present application relates to the field of channel coding, and in particular, to an interleaving method and an interleaving apparatus.

背景技术Background technique

数字通信***通常采用信道编码提高数据传输的可靠性，其中，一些信道编码采用了交织技术，以进一步提升数据传输过程中的抗干扰性能。在许多同时出现随机错误和突发错误的复合信道上，如果发生一个错误，往往会波及一串数据，导致突发错误超过信道纠错能力，纠错能力下降。而如果首先把突发错误离散成随机错误，再进行随机错误纠错，则***的抗干扰性能将进一步得到提高。Digital communication systems usually use channel coding to improve the reliability of data transmission. Some channel coding uses interleaving technology to further improve the anti-interference performance during data transmission. On many composite channels where random errors and burst errors occur simultaneously, if an error occurs, a string of data is often transmitted, resulting in burst errors exceeding the channel error correction capability and error correction capability. If the burst error is first discretized into random errors and random error correction is performed, the anti-interference performance of the system will be further improved.

现阶段，根据交织方法的不同，交织方法主要分为随机交织和行列交织。随机交织在离线计算循环移位序列时，需要存储置换序列供交织和解交织使用，在码长较长的情况下，随机交织所需的存储资源非常大，甚至不可接受。而行列交织对于所及错误的纠错能力较弱，纠错性能较差。At this stage, according to the different interleaving methods, the interleaving method is mainly divided into random interleaving and row-column interleaving. Random Interleaving When offline cyclic shift sequences are computed, it is necessary to store permutation sequences for interleaving and deinterleaving. In the case of long code lengths, the storage resources required for random interleaving are very large or even unacceptable. However, the interleaving of rows and columns is weak for the error correction and the error correction performance is poor.

发明内容Summary of the invention

本申请提供一种交织方法和交织装置，可以在不增加交织复杂度的情况下提升纠错性能。The present application provides an interleaving method and an interleaving apparatus, which can improve error correction performance without increasing interlacing complexity.

第一方面，本申请提供一种交织方法，该方法包括：获得N个第一比特序列，所述N为整数；In a first aspect, the present application provides an interleaving method, including: obtaining N first bit sequences, where N is an integer;

根据所述N个第一比特序列，生成第一交织矩阵，所述第一矩阵为l×l，Generating, according to the N first bit sequences, a first interlace matrix, where the first matrix is 1×1,

表示向上取整；根据第一循环移位序列对所述第一矩阵进行第一循环移位，获得第二矩阵，其中，所述第一循环移位序列包括J个比特，J≥2且为整数；根据第二循环移位序列对所述第二矩阵进行第二循环移位，获得第三矩阵，其中，所述第二循环移位序列包括S个比特，S≥2且为整数；根据所述第三矩阵，获得N个第二比特序列；输出所述第二比特序列。

Representing rounding up; performing a first cyclic shift on the first matrix according to the first cyclic shift sequence to obtain a second matrix, wherein the first cyclic shift sequence includes J bits, J≥2 and An integer; performing a second cyclic shift on the second matrix according to the second cyclic shift sequence to obtain a third matrix, wherein the second cyclic shift sequence includes S bits, S≥2 and is an integer; The third matrix obtains N second bit sequences; and outputs the second bit sequence.

本申请实施例的交织方法，与随机交织相比，交织复杂度低，但是交织性能却与随机交织性能相当甚至更优。因此，在不增加交织复杂度的情况下可以提升纠错性能。Compared with the random interleaving, the interleaving method in the embodiment of the present application has low interlacing complexity, but the interleaving performance is equivalent to or even better than the random interleaving performance. Therefore, the error correction performance can be improved without increasing the complexity of the interleaving.

结合第一方面，在第一方面的某些实现方式中，所述方法还包括：In conjunction with the first aspect, in some implementations of the first aspect, the method further comprises:

根据所述一循环移位序列，生成所述第二循环移位序列。Generating the second cyclic shift sequence according to the cyclic shift sequence.

结合第一方面，在第一方面的某些实现方式中，在第二方面的实现方式中，所述方法具体包括：With reference to the first aspect, in some implementations of the first aspect, in an implementation of the second aspect, the method specifically includes:

所述第二循环移位序列包括的比特值为所述第一循环移位序列对应的比特值的倍数或者分数，或者所述所述第二循环移位序列通过对所述第一循环移位序列进行顺序变换获得。The second cyclic shift sequence includes a bit value that is a multiple or a fraction of a bit value corresponding to the first cyclic shift sequence, or the second cyclic shift sequence is shifted by the first cyclic The sequence is obtained by sequential transformation.

结合第一方面，在第一方面的某些实现方式中，在第三方面的实现方式中，所述方法具体包括：With reference to the first aspect, in some implementations of the first aspect, in an implementation of the third aspect, the method specifically includes:

从所述J个第一循环移位序列中截取S个循环移位序列，作为所述第二循环移位序列；所截取方式包括下面的任意一种组合：按照比特的先后顺序从后向前截取S个的比特、按照比特的先后顺序从前向后截取S个的比特，或者按照比特的先后顺序，从后向前截取S1个的比特以及按照比特的先后顺序，从前向后截取S2个的比特，其中，S1+S2＝S，S1为整数，S2为整数。S cyclic shifting sequences are intercepted from the J first cyclic shift sequences as the second cyclic shift sequence; the intercepting manner includes any combination of the following: from the back to the front in the order of bits Intercepting S bits, intercepting S bits from front to back according to the order of bits, or intercepting S1 bits from the back and the front in order of bits, and cutting S2 from front to back according to the order of bits Bit, where S1+S2=S, S1 is an integer, and S2 is an integer.

结合第一方面，在第一方面的某些实现方式中，在第四方面的实现方式中，所述方法具体包括：With reference to the first aspect, in some implementations of the first aspect, in an implementation manner of the fourth aspect, the method specifically includes:

从所述J个第一循环移位序列中截取S个循环移位序列，所截取方式包括下面的任意一种组合：按照比特的先后顺序从后向前截取S个循环移位序列、按照比特的先后顺序从前向后截取S个循环移位序列；S cyclic shifting sequences are intercepted from the J first cyclic shift sequences, and the intercepting manner includes any combination of the following: intercepting S cyclic shift sequences from the back to the front in order of bits, according to bits The sequence of S is sequentially shifted backwards and backwards;

对所述截取的S个循环移位序列进行顺序变换，将顺序变换后的S个循环移位序列作为第二循环移位序列。The sequentially intercepted S cyclic shift sequences are sequentially transformed, and the sequentially transformed S cyclic shift sequences are used as the second cyclic shift sequence.

结合第一方面，在第一方面的某些实现方式中，在第五方面的实现方式中，所述方法具体包括：With reference to the first aspect, in some implementations of the first aspect, in an implementation manner of the fifth aspect, the method specifically includes:

所述第一循环移位序列与所述第二循环移位序列可以从预先配置的L个最长循环移位序列中获取，所述J小于L，所述S小于L，所述L为整数。The first cyclic shift sequence and the second cyclic shift sequence may be obtained from pre-configured L longest cyclic shift sequences, the J is smaller than L, the S is smaller than L, and the L is an integer .

第二方面，提供了一种交织装置，用于执行第一方面、第一方面的任意可能的实现方式中的方法。具体地，该装置包括执行第一方面或第一方面的任意可能的实现方式中的方法的单元。In a second aspect, an interleaving apparatus is provided for performing the method of the first aspect, any possible implementation of the first aspect. In particular, the apparatus comprises means for performing the method of the first aspect or any of the possible implementations of the first aspect.

第三方面，本申请提供一种交织设备，所述交织设备包括：一个或多个处理器，一个或多个存储器，一个或多个收发器(每个收发器包括发射机和接收机)。收发器用于通过天线收发信号。存储器用于存储计算机程序指令(或者说，代码)。处理器用于执行存储器中存储的指令，当指令被执行时，处理器执行第一方面或第一方面的任意可能的实现方式中的方法。In a third aspect, the present application provides an interleaving device comprising: one or more processors, one or more memories, one or more transceivers (each transceiver including a transmitter and a receiver). The transceiver is used to transmit and receive signals through the antenna. The memory is used to store computer program instructions (or code). The processor is operative to execute instructions stored in the memory, and when the instructions are executed, the processor performs the method of the first aspect or any of the possible implementations of the first aspect.

第四方面，本申请提供一种计算机可读存储介质，该计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行上述第一方面或第一方面的任意可能的实现方式中的方法。In a fourth aspect, the present application provides a computer readable storage medium having stored therein instructions that, when executed on a computer, cause the computer to perform any of the above first aspects or any possible implementation of the first aspect The method in the way.

第五方面，本申请提供一种芯片(或者说，芯片***)，包括存储器和处理器，存储器用于存储计算机程序，处理器用于从存储器中调用并运行该计算机程序，使得安装有该芯片的通信设备执行上述第一方面及其任意一种可能的实现方式中的方法。In a fifth aspect, the present application provides a chip (or a chip system) including a memory and a processor, the memory is used to store a computer program, and the processor is configured to call and run the computer program from the memory so that the chip is installed. The communication device performs the method of the first aspect described above and any one of its possible implementations.

第六方面，本申请提供一种计算机程序产品，所述计算机程序产品包括：计算机程序代码，当所述计算机程序代码在计算机上运行时，使得计算机执行上述第一方面及其任意一种可能的实现方式中的方法。In a sixth aspect, the application provides a computer program product, comprising: computer program code, when the computer program code is run on a computer, causing the computer to perform the first aspect and any one of the possible The method in the implementation.

第七方面，本申请提供一种编码装置，该编码装置具有实现上述第一方面及其第一方面任意一种可能的实现方式中的方法的功能。这些功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的模块。此外，该编码装置还应具有和编码相关的性能，例如，编码、速率匹配等。In a seventh aspect, the present application provides an encoding apparatus having a function of implementing the method of any of the above-described first aspects and any one of the possible implementations of the first aspect. These functions can be implemented in hardware or in software by executing the corresponding software. The hardware or software includes one or more modules corresponding to the functions described above. In addition, the encoding device should also have encoding-related capabilities such as encoding, rate matching, and the like.

在一个可能的设计中，当这些功能的部分或全部通过硬件实现时，编码装置包括：输入接口电路，用于获得N个第一比特序列，所述N为整数；逻辑电路，用于执行上述第一方面及其第一方面的任意一种可能的设计中的交织方法；输出接口电路，用于输出第二比特序列。In one possible design, when some or all of these functions are implemented by hardware, the encoding device includes: an input interface circuit for obtaining N first bit sequences, the N being an integer; and a logic circuit for performing the above The first aspect and the interleaving method in any one of the possible designs of the first aspect; the output interface circuit for outputting the second bit sequence.

可选的，编码装置可以是芯片或者集成电路。Alternatively, the encoding device may be a chip or an integrated circuit.

在一个可能的设计中，当这些功能的部分或全部通过软件实现时，编码装置包括：存储器，用于存储计算机程序；处理器，用于执行所述存储器存储的计算机程序，当所述计算机程序被执行时，编码装置可以实现上述第一方面及其第一方面的任意一种可能的设计中所述的交织方法。In one possible design, when some or all of these functions are implemented by software, the encoding device includes: a memory for storing a computer program; a processor, a computer program for executing the memory storage, when the computer program When executed, the encoding device can implement the interleaving method described in the first aspect above and any one of the possible designs of the first aspect.

在一个可能的设计中，当这些功能的部分或全部通过软件实现时，编码装置包括处理器，用于存储计算机程序的存储器位于编码装置之外，处理器通过电路/电线与存储器连接，用于读取并执行所述存储器中存储的计算机程序。In one possible design, when some or all of these functions are implemented by software, the encoding device includes a processor, the memory for storing the computer program is located outside the encoding device, and the processor is connected to the memory through the circuit/wire for the The computer program stored in the memory is read and executed.

可选的，上述存储器可以是物理上独立的单元，也可以与处理器集成在一起。Optionally, the above memory may be a physically separate unit or may be integrated with the processor.

需要说明的是，本申请实施了中描述的交织方法是由数据和/或信息的交织设备来执行的。在数据和/或信息的接收端，需要对接收到的比特序列进行解交织。本领域技术人员公知，解交织是交织的逆过程。在上述第一方面及其任意一种可能的实现方式中描述的交织方法的基础上，本领域技术人员容易得到解交织的方法，本文中不作详述。It should be noted that the interleaving method described in the implementation of the present application is performed by an interleaving device of data and/or information. At the receiving end of the data and/or information, the received bit sequence needs to be deinterleaved. It is well known to those skilled in the art that deinterleaving is the inverse of interleaving. Based on the interleaving method described in the above first aspect and any of its possible implementation manners, those skilled in the art can easily obtain a method of deinterleaving, which is not described in detail herein.

此外，本申请提供一种解交织的装置，具体地，解交织的装置包括执行解交织的方法的单元。Furthermore, the present application provides an apparatus for deinterleaving, and in particular, the apparatus for deinterleaving includes means for performing a method of deinterleaving.

此外，本申请还提供一种解交织的设备，该设备包括一个或多个处理器，一个或多个存储器，一个或多个收发器(收发器包括发射机和接收机)。发射机或接收机通过天线收发信号。存储器用于存储计算机程序指令(或者，代码)。处理器用于执行存储器中存储的指令，当指令被执行时，处理器执行解交织的方法。In addition, the present application also provides a deinterleaved device that includes one or more processors, one or more memories, and one or more transceivers (the transceiver includes a transmitter and a receiver). The transmitter or receiver transmits and receives signals through the antenna. The memory is used to store computer program instructions (or code). The processor is configured to execute instructions stored in the memory, and when the instructions are executed, the processor performs a method of deinterleaving.

此外，本申请提供一种计算机可读存储介质，该计算机可读存储介质中存储有计算机指令，当其在计算机上运行时，使得计算机执行解交织的方法。Moreover, the present application provides a computer readable storage medium having stored therein computer instructions that, when run on a computer, cause the computer to perform a method of deinterleaving.

本申请还提供一种计算机程序产品，该计算机程序产品包括：计算机程序代码，当该计算机程序代码在计算机上运行时，使得计算机执行解交织的方法。The application also provides a computer program product comprising: computer program code, a method of causing a computer to perform deinterleaving when the computer program code is run on a computer.

本申请还提供一种芯片(或者说，芯片***)，包括存储器和处理器，存储器用于存储计算机程序，处理器用于从存储器中调用并运行该计算机程序，使得安装有该芯片的通信设备执行本申请各方法实施例中的交织方法。The present application also provides a chip (or a chip system) including a memory and a processor for storing a computer program, the processor for calling and running the computer program from the memory, such that the communication device on which the chip is mounted performs The interleaving method in the method embodiments of the present application.

本申请还提供一种译码装置，该译码装置具有实现本申请实施例中所说的解交织的方法的功能。这些功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。除此之外，译码装置还具有实现译码的相关功能，例如，解速率匹配、译码等。The present application also provides a decoding apparatus having a function of implementing the method of deinterleaving as described in the embodiments of the present application. These functions can be implemented in hardware or in software by executing the corresponding software. In addition to this, the decoding device also has associated functions for implementing decoding, such as de-rate matching, decoding, and the like.

在本申请实施例中，提出了一种简单易操作的交织方法，能够在不增加交织复杂度的情况下提升纠错性能。In the embodiment of the present application, a simple and easy-to-operate interleaving method is proposed, which can improve error correction performance without increasing interlacing complexity.

附图说明DRAWINGS

图1为适用于本申请实施例的无线通信***100。FIG. 1 is a wireless communication system 100 suitable for use in an embodiment of the present application.

图2是采用无线技术进行通信的基本流程图。Figure 2 is a basic flow diagram for communicating using wireless technology.

图3是本申请实施例的交织方法的流程图。FIG. 3 is a flowchart of an interleaving method in an embodiment of the present application.

图4是本申请实施例的另一种交织方法的示意图。FIG. 4 is a schematic diagram of another interleaving method in the embodiment of the present application.

图5本申请实施例的交织装置500的示意图。FIG. 5 is a schematic diagram of an interleaving apparatus 500 of an embodiment of the present application.

图6为本申请实施例的交织设备600的示意性结构图。FIG. 6 is a schematic structural diagram of an interleaving device 600 according to an embodiment of the present application.

图7为本申请实施例的终端设备700的示意性结构图。FIG. 7 is a schematic structural diagram of a terminal device 700 according to an embodiment of the present application.

具体实施方式Detailed ways

下面将结合附图，对本申请中的技术方案进行描述。The technical solutions in the present application will be described below with reference to the accompanying drawings.

图1为适用于本申请实施例的无线通信***100。该无线通信***中可以包括至少一个网络设备101，该网络设备与一个或多个终端设备(例如，图1中所示的终端设备102和终端设备102)进行通信。网络设备101可以是基站，也可以是基站与基站控制器集成后的设备，还可以是具有类似通信功能的其它设备。FIG. 1 is a wireless communication system 100 suitable for use in an embodiment of the present application. The wireless communication system can include at least one network device 101 in communication with one or more terminal devices (e.g., terminal device 102 and terminal device 102 shown in FIG. 1). The network device 101 may be a base station, or may be a device integrated with a base station controller, or may be another device having similar communication functions.

本申请实施例提及的无线通信***包括但不限于：窄带物联网***(Narrow Band-Internet of Things，NB-IoT)、全球移动通信***(Global System for Mobile Communications，GSM)、增强型数据速率GSM演进***(Enhanced Data rate for GSM Evolution，EDGE)、宽带码分多址***(Wideband Code Division Multiple Access，WCDMA)、码分多址2000***(Code Division Multiple Access，CDMA2000)、时分同步码分多址***(Time Division-Synchronization Code Division Multiple Access，TD-SCDMA)，长期演进***(Long Term Evolution，LTE)、下一代5G移动通信***的三大应用场景eMBB，URLLC和eMTC或者将来出现的新的通信***。The wireless communication system mentioned in the embodiments of the present application includes, but is not limited to, a Narrow Band-Internet of Things (NB-IoT), a Global System for Mobile Communications (GSM), and an enhanced data rate. Enhanced Data Rate for GSM Evolution (EDGE), Wideband Code Division Multiple Access (WCDMA), Code Division Multiple Access (CDMA), Time Division Synchronization Codes Time Division-Synchronization Code Division Multiple Access (TD-SCDMA), Long Term Evolution (LTE), three major application scenarios of next-generation 5G mobile communication systems, eMBB, URLLC and eMTC, or new ones in the future Communication Systems.

本申请实施例中所涉及到的终端设备可以包括各种具有无线通信功能的手持设备、车载设备、可穿戴设备、计算设备或连接到无线调制解调器的其它处理设备。终端设备可以是移动台(Mobile Station，MS)、用户单元(subscriber unit)、蜂窝电话(cellular phone)、智能电话(smart phone)、无线数据卡、个人数字助理(Personal Digital Assistant，PDA)电脑、平板型电脑、无线调制解调器(modem)、手持设备(handset)、膝上型电脑(laptop computer)、机器类型通信(Machine Type Communication，MTC)终端等。The terminal devices involved in the embodiments of the present application may include various handheld devices having wireless communication functions, in-vehicle devices, wearable devices, computing devices, or other processing devices connected to the wireless modem. The terminal device may be a mobile station (MS), a subscriber unit, a cellular phone, a smart phone, a wireless data card, a personal digital assistant (PDA) computer, Tablet PCs, wireless modems, handsets, laptop computers, Machine Type Communication (MTC) terminals, and the like.

图1中的网络设备101与终端设备之间采用无线技术进行通信。当网络设备发送信号时，其为交织设备，终端设备为接收端。当网络设备接收信号时，其为接收端，终端设备为交织设备。The network device 101 and the terminal device in FIG. 1 communicate using wireless technology. When the network device sends a signal, it is an interleaving device, and the terminal device is a receiving end. When the network device receives the signal, it is the receiving end, and the terminal device is the interleaving device.

图2是采用无线技术进行通信的基本流程图。交织设备的信源依次经过信源编码、信道编码、速率匹配和调制后在信道上发出。接收端接收到信号后依次经过解调、解速率匹配、信道解码和信源解码后获得信宿。Figure 2 is a basic flow diagram for communicating using wireless technology. The source of the interleaving device is sequentially transmitted on the channel after source coding, channel coding, rate matching, and modulation. After receiving the signal, the receiving end obtains the sink after demodulation, de-rate matching, channel decoding, and source decoding.

信道编码是无线通信***的核心技术之一，其性能的改进将直接提升网络覆盖及用户传输速率。为了提高信号的抗干扰性，可以进一步地可以引入交织技术。交织技术的思想是在时间上分离码元，将一个有记忆信道转变为无记忆信道，从而使得纠随机错误的编码也能适用于噪声突发信道。Channel coding is one of the core technologies of wireless communication systems, and its performance improvement will directly improve network coverage and user transmission rate. In order to improve the anti-interference of the signal, an interleaving technique can be further introduced. The idea of interleaving technology is to separate symbols in time and convert a memory channel into a memoryless channel, so that the code for correcting random errors can also be applied to the noise burst channel.

常用的交织方法包括随机交织和行列交织。随机交织在平均性能上较优，但是由于交织的随机性，无法保证每次交织都具有较优的性能。并且在离线交织的情况下，需要存储大量的置换序列供交织和解交织使用。当码长较长时，随机交织所需的存储资源较大，给编码器造成很大的硬件负荷，甚至不可接受。此外，随机交织的复杂度较高。而行列交织的方案比较简单，但是对于数据的随机化处理较弱，交织性能不太理想。Common interleaving methods include random interleaving and row and column interleaving. Random interleaving is superior in average performance, but due to the randomness of interleaving, there is no guarantee that each interleaving will have superior performance. And in the case of offline interleaving, it is necessary to store a large number of permutation sequences for interleaving and deinterleaving. When the code length is long, the storage resources required for random interleaving are large, causing a large hardware load to the encoder, and is even unacceptable. In addition, the complexity of random interleaving is higher. The scheme of interlacing is simple, but the randomization of data is weak, and the interleaving performance is not ideal.

为此，本申请提出一种交织方法，可以在不增加交织复杂度的情况下，提升纠错性能。下面对本申请实施例的交织方法进行详细说明。To this end, the present application proposes an interleaving method, which can improve error correction performance without increasing the complexity of interleaving. The interleaving method of the embodiment of the present application will be described in detail below.

参见图3，图3是本申请实施例的交织方法的流程图。Referring to FIG. 3, FIG. 3 is a flowchart of an interleaving method in an embodiment of the present application.

310、交织设备获得N个第一比特序列。310. The interleaving device obtains N first bit sequences.

其中，第一比特序列包括N个比特，其中，N为整数。The first bit sequence includes N bits, where N is an integer.

320、交织设备根据所述N个第一比特序列，生成第一交织矩阵，所述第一矩阵为l×l，

表示向上取整。 320. The interleaving device generates a first interlace matrix according to the N first bit sequences, where the first matrix is 1×l.

Indicates rounding up.

330、交织设备根据第一循环移位序列对所述第一矩阵进行第一循环移位，获得第二矩阵，其中，所述第一循环移位序列包括J个比特，J≥2且为整数。330. The interleaving device performs a first cyclic shift on the first matrix according to the first cyclic shift sequence to obtain a second matrix, where the first cyclic shift sequence includes J bits, J≥2 and is an integer. .

具体地，交织设备生成所述第二循环移位序列的方法为：根据所述一循环移位序列，生成所述第二循环移位序列。Specifically, the method for the interleaving device to generate the second cyclic shift sequence is: generating the second cyclic shift sequence according to the cyclic shift sequence.

进一步可选地，交织设备生成所述第二循环移位序列的方法为：Further optionally, the method for the interleaving device to generate the second cyclic shift sequence is:

所述第二循环移位序列包括的比特值为所述第一循环移位序列对应的比特值的倍数或者分数，或者所述所述第二循环移位序列通过对所述第一循环移位序列进行顺序变换获得；或者，The second cyclic shift sequence includes a bit value that is a multiple or a fraction of a bit value corresponding to the first cyclic shift sequence, or the second cyclic shift sequence is shifted by the first cyclic The sequence is obtained by sequential transformation; or,

从所述J个第一循环移位序列中截取S个循环移位序列，作为所述第二循环移位序列；所截取方式包括下面的任意一种组合：按照比特的先后顺序从后向前截取S个的比特、按照比特的先后顺序从前向后截取S个的比特，或者按照比特的先后顺序，从后向前截取S1个的比特以及按照比特的先后顺序，从前向后截取S2个的比特，其中，S1+S2＝S，S1为整数，S2为整数；或者，S cyclic shifting sequences are intercepted from the J first cyclic shift sequences as the second cyclic shift sequence; the intercepting manner includes any combination of the following: from the back to the front in the order of bits Intercepting S bits, intercepting S bits from front to back according to the order of bits, or intercepting S1 bits from the back and the front in order of bits, and cutting S2 from front to back according to the order of bits Bit, where S1+S2=S, S1 is an integer, and S2 is an integer; or,

对所述截取的S个循环移位序列进行顺序变换，将顺序变换后的S个循环移位序列作为第二循环移位序列；或者，Performing sequential transformation on the intercepted S cyclic shift sequences, and using the sequentially transformed S cyclic shift sequences as the second cyclic shift sequence; or

340、根据第二循环移位序列对所述第二矩阵进行第二循环移位，获得第三矩阵，其中，所述第二循环移位序列包括S个比特，S≥2且为整数。340. Perform a second cyclic shift on the second matrix according to the second cyclic shift sequence to obtain a third matrix, where the second cyclic shift sequence includes S bits, S≥2 and is an integer.

350、根据所述第三矩阵，获得N个第二比特序列，发送所述第二比特序列。350. Obtain, according to the third matrix, N second bit sequences, and send the second bit sequence.

360、输出所述第二比特序列。360. Output the second bit sequence.

上述交织设备包括交织设备，具体地，通过交织设备执行上述的方法；上述交织设备可以为网络设备，也可以为终端设备。The foregoing interleaving device includes an interleaving device, and specifically, the foregoing method is performed by using an interleaving device; the interleaving device may be a network device or a terminal device.

在本申请实施例中，提出了一种简单易操作的交织方法，能够在不增加交织复杂度的情况下，通过对待交织的比特序列进行行或者列循环移位，再进行列或者行循环移位这先后两次的循环移位，使得交织后的性能与随机交织性能接近，尤其是在高阶调制下可以达到与随机交织设备接近的性能，进而提升***的纠错性能；同时该方案也属于一种确定型交织设备，满***织设备的设计要求。In the embodiment of the present application, a simple and easy-to-operate interleaving method is proposed, which can perform row or column cyclic shift by bit sequence to be interleaved without further increasing interleaving complexity, and then perform column or row cyclic shift. The cyclic shift of the bit twice makes the performance of the interleaving close to that of the random interleaving performance, especially in the high-order modulation, which can achieve the performance close to the random interleaving device, thereby improving the error correction performance of the system; It belongs to a deterministic interleaving device that meets the design requirements of interwoven devices.

下面结合图4，对本申请实施例中交织设备对待循环移位序列的交织过程作详细说明。The interleaving process of the interleaving device to the cyclic shift sequence in the embodiment of the present application is described in detail below with reference to FIG.

本发明实施例给定了一个行列矩阵是方阵的形式，并给出循环移位序列，例如第一比特序列以及第二比特序列的具体生成方式，但实际循环移位序列的生成和初始化可以有多种形式，并不限定于本实施例中下述方法。The embodiment of the present invention gives a matrix of rows and columns in the form of a square matrix, and gives a cyclic shift sequence, such as a specific generation manner of the first bit sequence and the second bit sequence, but the generation and initialization of the actual cyclic shift sequence may be There are many forms and are not limited to the following methods in the present embodiment.

步骤1：交织设备获得N个待交织的比特序列，N为整数。Step 1: The interleaving device obtains N bit sequences to be interleaved, and N is an integer.

步骤2：交织设备根据所述N个待交织的比特序列，设置交织设备的行数和列数，且行数和列数相等，Step 2: The interleaving device sets the number of rows and the number of columns of the interleaving device according to the N bit sequences to be interleaved, and the number of rows and the number of columns are equal.

记为l；则

表示向上取整。 Recorded as l;

Indicates rounding up.

如图4所示，以N＝16个待交织的比特序列为例，根据所述N设置交织设备大小为4x4，即l＝4。As shown in FIG. 4, taking N=16 bit sequences to be interleaved as an example, the size of the interleaving device is set to 4×4 according to the N, that is, l=4.

步骤3：交织设备根据待交织的比特序列，生成第一矩阵，所述第一矩阵的大小为l×l。Step 3: The interleaving device generates a first matrix according to the bit sequence to be interleaved, and the size of the first matrix is l×l.

如图4中的(1)所示，这里交织设备获取待交织的比特序列设置为：X＝{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}；As shown in (1) of FIG. 4, the bit sequence to be interleaved by the interleaving device is set to: X={1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,14,15,16};

按照一行l个比特的方式或者一列l个比特的方式，将待交织的比特儿序列逐行或者逐列地读入交织设备，剩余位置填写NULL比特；在从交织设备读出时将NULL比特跳过不进行读取，进而生成l×l的第一矩阵。如图4，按照每行读取4个比特的方式，逐行读入交织设备中，生成第一矩阵，如图4中矩阵(1)。The bit sequence to be interleaved is read into the interleaving device row by row or column by column according to a row of 1 bit or a column of 1 bit, and the remaining position is filled with NULL bits; when read from the interleaving device, the NULL bit is skipped. The reading is not performed, and a first matrix of 1×1 is generated. As shown in FIG. 4, the interleaving device is read line by line in a manner of reading 4 bits per line to generate a first matrix, such as matrix (1) in FIG.

步骤4：交织设备对第一矩阵进行循环移位。Step 4: The interleaving device cyclically shifts the first matrix.

具体地，根据循环移位序列对交织设备中的比特序列进行循环移位操作：Specifically, the bit sequence in the interleaving device is cyclically shifted according to the cyclic shift sequence:

首先，先介绍下上述循环移位序列的生成：First, let's first introduce the generation of the above cyclic shift sequence:

循环移位序列包括第一循环移位序列和第二循环移位序列分别记为S和S′。The cyclic shift sequence includes a first cyclic shift sequence and a second cyclic shift sequence, respectively denoted as S and S'.

以待交织比特数N个比特为例，Take N bits of the number of bits to be interleaved as an example.

(1)初始化S中的特定元素，例如S ₁＝a,S ₂＝b； (1) Initialize a specific element in S, such as S ₁ = a, S ₂ = b;

(2)对于S _i：计算公式可选为：S _i＝(S _i-1+S _i-2)&l；3≤i≤l； (2) For S _i : the calculation formula can be selected as: S _i = (S _i-1 + S _i-2 ) &l; 3 ≤ _i ≤ l;

(3)序列S′为S的反序，即S′ _i＝S _l-i+1；1≤i≤l。 (3) The sequence S' is the reverse order of S, that is, S' _i = S _l-i+1 ; 1 ≤ _i ≤ _l .

序列S′的获得也可以通过新的计算公式，但当交织矩阵为方阵时，序列S′为S的反序或者其他变种在实现上更为方便简洁。The acquisition of the sequence S' can also pass a new calculation formula, but when the interlace matrix is a square matrix, the sequence S' is the reverse order of S or other variants are more convenient and concise in implementation.

以N为16，X＝{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}为例，按照步骤(2)和(3)的公式，生成循环移位序列S，S’：Taking N as 16, X={1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16} as an example, according to steps (2) and ( 3) The formula that generates the cyclic shift sequence S, S':

(1)S1＝1,S2＝2；S3＝(S2+S1)&4＝3；S4＝(S3+S2)&4＝1；即S＝{1,2,3,1}；(1) S1=1, S2=2; S3=(S2+S1)&4=3;S4=(S3+S2)&4=1; that is, S={1, 2, 3, 1};

(2)S’是S的逆序，则S’＝{1,3,2,1}；(2) S' is the reverse order of S, then S' = {1, 3, 2, 1};

其次，按行和按列的方式对待交织的比特进行循环移位：Second, the interleaved bits are cyclically shifted in rows and columns:

(1)根据序列S对矩阵(1)按行进行循环移位得到第二矩阵，如图4矩阵(2)；(1) cyclically shifting the matrix (1) according to the sequence S to obtain a second matrix, as shown in the matrix (2) of FIG. 4;

(2)根据序列S’对矩阵(2)按列进行循环移位得到第三矩阵，如图4矩阵(3)；(2) cyclically shifting the matrix (2) according to the sequence S' to obtain a third matrix, as shown in the matrix (3) of FIG. 4;

步骤5：交织设备将所述第三矩阵序列按行或者按列的方式读出，跳过NULL比特位置，输出读出的比特序列。Step 5: The interleaving device reads the third matrix sequence in a row or column manner, skips the NULL bit position, and outputs the read bit sequence.

以上述N为16为例，若按行的方式，逐行对第三矩阵进行读出，输出比特序列X＝{16,8,12,15,4,11,14,3,7,13,2,6,10,1,5,9}。Taking the above N as 16 as an example, if the third matrix is read line by line, the bit sequence X={16,8,12,15,4,11,14,3,7,13 is outputted. 2,6,10,1,5,9}.

上述交织设备包括交织设备，所述交织设备可以为网络设备，也可以为终端设备。The interleaving device includes an interlacing device, and the interleaving device may be a network device or a terminal device.

对本申请实施例中交织设备对待循环移位序列的交织过程具体还可以如下：The interleaving process of the interleaving device to treat the cyclic shift sequence in the embodiment of the present application may also be specifically as follows:

本实施例与前述实施例的不同之处在于：采用的行列矩阵不是方阵的形式，而是行数与列数呈倍数关系，那么在获得一个循环移位序列时，根据倍数关系或者分数关系，可以通过重复或者截短来获得另一个循环移位序列。The difference between this embodiment and the foregoing embodiment is that the matrix of the row and the column is not in the form of a square matrix, but the number of rows and the number of columns are in a multiple relationship, then when obtaining a cyclic shift sequence, according to a multiple relationship or a fractional relationship Another cyclic shift sequence can be obtained by repeating or truncating.

步骤1：交织设备获得N个待交织比特数；Step 1: The interleaving device obtains the number of N bits to be interleaved;

步骤2：交织设备根据所述N，设置交织设备的大小为：行数为r,列数c为行数的l倍，Step 2: The interleave device sets the size of the interleaving device according to the N: the number of rows is r, and the number of columns c is l times the number of rows.

c＝l*r，则

表示向上取整； c=l*r, then

Indicates rounding up;

步骤3：交织设备根据交织设备的大小为r×c，将待交织比特按行或者按列的方式逐行或者逐列读入，剩余位置填写NULL比特，生成第一矩阵。Step 3: The interleaving device reads the bits to be interleaved row by row or column by column according to the size of the interleaving device, and fills the NULL bits in the remaining positions to generate the first matrix.

步骤4：交织设备对第一矩阵进行循环移位：Step 4: The interleaving device cyclically shifts the first matrix:

例如：行和列进行不等长度的循环移位，移位序列分别记为S和S′；For example, the rows and columns are cyclically shifted by unequal lengths, and the shift sequences are respectively recorded as S and S';

循环移位序列序列S、S′计算方法如下，其中：The cyclic shift sequence sequence S, S' is calculated as follows, wherein:

(1)初始化S中的特定元素；例如S ₁＝a,S ₂＝b； (1) Initializing a specific element in S; for example, S ₁ = a, S ₂ = b;

(2)计算S _i；例如计算公式可选为：S _i＝(S _i-1+S _i-2)&l；3≤i≤l； (2) Calculate S _i ; for example, the calculation formula may be: S _i = (S _i-1 + S _i-2 ) &l; 3 ≤ _i ≤ l;

(3)序列S′为S的顺序变换后的重复累加。(3) The sequence S' is a repeated addition after the sequential transformation of S.

可选的：Optional:

循环移位序列S、S′计算方法如下，其中：The cyclic shift sequence S, S' is calculated as follows, wherein:

(1)初始化S′中的特定元素；(1) initializing a specific element in S';

(2)计算S' _i； (2) Calculate S'_i;

(3)序列S为S'的截取，截取方式可以是从后向前截取S长度的序列，或者从前向后，或者从特定位置截取对应长度的循环移位序列，进而获得S′；或者，(3) The sequence S is intercepted by S', and the intercepting manner may be to intercept the S length sequence from the back to the front, or to cut the cyclic shift sequence of the corresponding length from the front to the back or from a specific position, thereby obtaining S'; or

从S中截取，然后再该截取后的序列做反序或其他顺序变换操作，获得S′。Intercepting from S, and then performing the reverse sequence or other sequential transformation operations on the intercepted sequence to obtain S'.

步骤5：交织设备对第一矩阵进行循环移位。Step 5: The interleaving device cyclically shifts the first matrix.

按行和按列的方式对待交织的比特进行循环移位：The interleaved bits are cyclically shifted in rows and columns:

步骤6：交织设备将所述第三矩阵序列按行或者按列的方式读出，跳过NULL比特位置，输出读出的比特序列。Step 6: The interleaving device reads the third matrix sequence in a row or column manner, skips the NULL bit position, and outputs the read bit sequence.

本实施例与前述实施例的不同之处在于考虑当前控制信道最大的母码长度定义为1024个比特，当编码后比特大于1024时，则采用重复编码来获得编码后比特。因此，考虑该种情况，可以考虑设计最长的可用交织矩阵或者最长的循环移位序列，当所需循环移位序列小于用于循环移位的最大交织矩阵或者最长循环移位序列时，从所述最大交织矩阵或者最长循环移位序列中，截取第一循环移位序列以及第二循环移位序列。另外其它相关步骤与上述实施例相同，故不再赘述。The difference between this embodiment and the foregoing embodiment is that the maximum mother code length of the current control channel is defined as 1024 bits, and when the coded bits are greater than 1024, the coded bits are obtained by using repeated coding. Therefore, considering this case, consider designing the longest available interleaving matrix or the longest cyclic shifting sequence when the required cyclic shifting sequence is smaller than the maximum interleaving matrix or the longest cyclic shifting sequence for cyclic shifting. And extracting, from the maximum interleaving matrix or the longest cyclic shift sequence, the first cyclic shift sequence and the second cyclic shift sequence. The other related steps are the same as those of the above embodiment, and therefore will not be described again.

进一步地，具体方法举例如下：Further, specific methods are as follows:

首先，获得最大交织矩阵的方法如下：First, the method to obtain the largest interleaving matrix is as follows:

1，设待交织比特数为Nmax，交织设备的大小设置为行数为r,列数为c，r*c>＝Nmax；1, the number of bits to be interleaved is Nmax, the size of the interleaving device is set to r, the number of columns is c, r*c>=Nmax;

2，交织设备的大小被设置为r×c，交织矩阵定义为A,将待交织比特按行读入交织设备，剩余位置填写NULL比特；2, the size of the interleaving device is set to r × c, the interleaving matrix is defined as A, the bits to be interleaved are read into the interleaving device in rows, and the remaining positions are filled with NULL bits;

其次，获得所需交织矩阵的方法如下：Second, the method to obtain the required interleaving matrix is as follows:

1，设待交织比特数为N，交织设备的大小设置为行数为r1,列数为c1，r1*c1>＝N；1, the number of interleaving bits is N, and the size of the interleaving device is set to r1, the number of columns is c1, r1*c1>=N;

2，交织设备的大小为r1×c1，交织矩阵定义为B,将待交织比特按行读入交织设备，剩余位置填写NULL比特；2, the size of the interleaving device is r1 × c1, the interleave matrix is defined as B, the bits to be interleaved are read into the interleaving device in rows, and the remaining positions are filled with NULL bits;

交织矩阵B的获取基于上述矩阵A得到，可选的，矩阵B可以是对矩阵A从上到下从左至右的截取，可选的，矩阵B可以是对矩阵A从下到上从右至左的截取，矩阵B可以是对矩阵A从上到下从右至左的截取，矩阵B可以是对矩阵A从下到上从左至右的截取，矩阵B可以是对矩阵A特定位置起始开始的对应行列数的截取。The obtaining of the interleaving matrix B is obtained based on the above matrix A. Alternatively, the matrix B may be a truncation of the matrix A from top to bottom from left to right. Alternatively, the matrix B may be the matrix A from bottom to top and from the right. To the left intercept, the matrix B may be a right-to-left intercept of the matrix A from top to bottom, the matrix B may be a cut-off from the bottom to the top of the matrix A, and the matrix B may be a specific position to the matrix A. The interception of the corresponding number of rows and columns at the beginning.

需要说明的上述是以交织矩阵的形式对循环移位序列的获得进行进一步的描述，所谓的矩阵和序列不同在于表现的方式不同，但是都是由比特组成，并且可以互相互换。The above description is further described in terms of the acquisition of a cyclic shift sequence in the form of an interleaving matrix which differs in the manner of representation, but is composed of bits and can be interchanged with each other.

具体对所述矩阵进行循环移位操作的过程请参见上述的实施例的进一步描述，这里不再赘述。For the process of performing the cyclic shift operation on the matrix, refer to the further description of the foregoing embodiments, and details are not described herein again.

本申请实施例提出了一种简单易操作的交织方法，能够在不增加交织复杂度的情况下，通过对待交织的比特序列进行行或者列循环移位，再进行列或者行循环移位这先后两次的循环移位，使得交织后的性能与随机交织性能接近，尤其是在高阶调制下可以达到与随机交织设备接近的性能，进而提升***的纠错性能；同时该方案也属于一种确定型交织设备，满***织设备的设计要求。The embodiment of the present application proposes a simple and easy-to-operate interleaving method, which can perform row or column cyclic shift by bit sequence to be interleaved without performing interleave complexity, and then perform column or row cyclic shift. The two cyclic shifts make the performance of the interleaving close to that of the random interleaving performance, especially in the high-order modulation, which can achieve the performance close to the random interleaving device, thereby improving the error correction performance of the system; The deterministic interleaving device satisfies the design requirements of the interlaced device.

以上结合图1至图4，对本申请实施例的交织方法的过程作了详细说明，以下对本申请实施例的交织装置作介绍。The process of the interleaving method in the embodiment of the present application is described in detail with reference to FIG. 1 to FIG. 4 . The following describes the interleaving device in the embodiment of the present application.

图5为本申请实施例的交织装置500的示意图。如图5所示，装置500包括接收单元500、处理单元520和发送单元530。其中，FIG. 5 is a schematic diagram of an interleaving apparatus 500 according to an embodiment of the present application. As shown in FIG. 5, the apparatus 500 includes a receiving unit 500, a processing unit 520, and a transmitting unit 530. among them,

接收单元510，用于获得N个第一比特序列，所述N为整数；The receiving unit 510 is configured to obtain N first bit sequences, where N is an integer;

处理单元520，用于根据所述N个第一比特序列，生成第一交织矩阵，所述第一矩阵为l×l，

表示向上取整；根据第一循环移位序列对所述第一矩阵进行第一循环移位，获得第二矩阵，其中，所述第一循环移位序列包括J个比特，J≥2且为整数；根据第二循环移位序列对所述第二矩阵进行第二循环移位，获得第三矩阵，其中，所述第二循环移位序列包括S个比特，S≥2且为整数；根据所述第三矩阵，获得N个第二比特序列； The processing unit 520 is configured to generate, according to the N first bit sequences, a first interlace matrix, where the first matrix is 1×1,

Representing rounding up; performing a first cyclic shift on the first matrix according to the first cyclic shift sequence to obtain a second matrix, wherein the first cyclic shift sequence includes J bits, J≥2 and An integer; performing a second cyclic shift on the second matrix according to the second cyclic shift sequence to obtain a third matrix, wherein the second cyclic shift sequence includes S bits, S≥2 and is an integer; The third matrix obtains N second bit sequences;

发送单元530，用于发送所述第二比特序列。The sending unit 530 is configured to send the second bit sequence.

本申请实施例的装置500中的各单元和上述其它操作或功能分别为了实现本申请各实施例中的交织方法。为了简洁，此处不再赘述。The units in the apparatus 500 of the embodiment of the present application and the other operations or functions described above are respectively implemented in order to implement the interleaving method in the embodiments of the present application. For the sake of brevity, it will not be repeated here.

本申请实施例的交织装置，能够在不增加交织复杂度的情况下提升纠错性能。The interleaving apparatus of the embodiment of the present application can improve error correction performance without increasing the complexity of interleaving.

图6为本申请实施例的交织设备600的示意性结构图。如图6所示，设备600包括：一个或多个处理器601，一个或多个存储器602，一个或多个收发器603。处理器601用于控制收发器603收发信号，存储器602用于存储计算机程序，处理器601用于从存储器602中调用并运行该计算机程序，使得交织设备600执行交织方法各实施例的相应流程和/或操作。为了简洁，此处不再赘述。FIG. 6 is a schematic structural diagram of an interleaving device 600 according to an embodiment of the present application. As shown in FIG. 6, device 600 includes one or more processors 601, one or more memories 602, and one or more transceivers 603. The processor 601 is configured to control the transceiver 603 to send and receive signals, the memory 602 is used to store a computer program, and the processor 601 is configured to call and run the computer program from the memory 602, such that the interleaving device 600 performs the corresponding processes of the embodiments of the interleaving method and / or operation. For the sake of brevity, it will not be repeated here.

需要说明的是，图5中所示的交织装置500可以通过图6中所示的交织设备600实现。例如，接收单元510、发送单元530可以由图6中的收发器603实现。处理单元520可以由处理器601实现等。It should be noted that the interleaving device 500 shown in FIG. 5 can be implemented by the interleaving device 600 shown in FIG. 6. For example, the receiving unit 510 and the transmitting unit 530 can be implemented by the transceiver 603 in FIG. Processing unit 520 can be implemented by processor 601, and the like.

交织设备可以为图1中所示的网络设备或终端设备。在上行传输时，交织设备具体为终端设备，终端设备具有实现上述各实施例中描述的交织方法的功能。这些功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的单元。在下行传输时，交织设备具体为网络设备(例如，基站)，网络设备具有实现上述各实施例中描述的交织方法的功能。同样地，这些功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的单元。The interleaving device may be the network device or the terminal device shown in FIG. 1. In the uplink transmission, the interleaving device is specifically a terminal device, and the terminal device has a function of implementing the interleaving method described in the above embodiments. These functions can be implemented in hardware or in software by executing the corresponding software. The hardware or software includes one or more units corresponding to the functions described above. In the downlink transmission, the interleaving device is specifically a network device (for example, a base station), and the network device has a function of implementing the interleaving method described in the above embodiments. Similarly, these functions can be implemented in hardware or in software. The hardware or software includes one or more units corresponding to the functions described above.

当交织设备600具体为终端设备时，终端设备的结构可以如图7所示。图7为本申请实施例的终端设备700的示意性结构图。When the interleaving device 600 is specifically a terminal device, the structure of the terminal device can be as shown in FIG. 7. FIG. 7 is a schematic structural diagram of a terminal device 700 according to an embodiment of the present application.

如图7所示，终端设备700包括：收发器708和处理装置704。终端设备700还可以包括存储器719，存储器819用于存储计算机指令。As shown in FIG. 7, the terminal device 700 includes a transceiver 708 and a processing device 704. The terminal device 700 can also include a memory 719 for storing computer instructions.

收发器708，用于获得N个第一比特序列，所述N为整数。The transceiver 708 is configured to obtain N first bit sequences, where N is an integer.

处理器704，用于根据所述N个第一比特序列，生成第一交织矩阵，所述第一矩阵为l×l，The processor 704 is configured to generate, according to the N first bit sequences, a first interlace matrix, where the first matrix is 1×1,

表示向上取整；根据第一循环移位序列对所述第一矩阵进行第一循环移位，获得第二矩阵，其中，所述第一循环移位序列包括J个比特，J≥2且为整数；根据第二循环移位序列对所述第二矩阵进行第二循环移位，获得第三矩阵，其中，所述第二循环移位序列包括S个比特，S≥2且为整数；根据所述第三矩阵，获得N个第二比特序列；

收发器708，用于根据处理装置704的指示，发送第二比特序列。The transceiver 708 is configured to send a second bit sequence according to the indication of the processing device 704.

进一步地，上述处理装置704可以用于执行前面方法实施例中描述的由交织设备内部实现的动作，而收发器708可以用于执行前面方法实施例中描述的交织设备的接收或发送动作。具体请见前面方法实施例中的描述，此处不再赘述。Further, the processing device 704 described above may be configured to perform the actions implemented by the interleaving device described in the foregoing method embodiments, and the transceiver 708 may be configured to perform the receiving or transmitting actions of the interleaving device described in the foregoing method embodiments. For details, please refer to the description in the previous method embodiments, and details are not described herein again.

上述处理装置704和存储器719可以集成为一个处理器，处理器用于执行存储器719中存储的程序代码来实现上述功能。具体实现时，该存储器719也可以集成在处理器中。The processing device 704 and the memory 719 described above may be integrated into a processor for executing program code stored in the memory 719 to implement the above functions. In a specific implementation, the memory 719 can also be integrated in the processor.

上述终端设备700还可以包括电源812，用于给终端设备700中的各种器件或电路提供电源。上述终端设备700可以包括天线710，用于将收发器808输出的数据或信息通过无线信号发送出去。The terminal device 700 described above may further include a power source 812 for providing power to various devices or circuits in the terminal device 700. The terminal device 700 may include an antenna 710 for transmitting data or information output by the transceiver 808 through a wireless signal.

除此之外，为了使终端设备800的功能更加完善，终端设备800还可以包括输入单元714，显示单元716，音频电路718，摄像头720和传感器722等中的一个或多个。音频电路还可以包括扬声器7182，麦克风7184等。In addition, in order to improve the functions of the terminal device 800, the terminal device 800 may further include one or more of an input unit 714, a display unit 716, an audio circuit 718, a camera 720, a sensor 722, and the like. The audio circuit may also include a speaker 7182, a microphone 7184, and the like.

需要说明的是，本申请实施例中提供的交织方法可以适用于各种信道编码，例如，LDPC码、Turbo码码、极化(Polar)码等。本申请实施例对此不作限定。It should be noted that the interleaving method provided in the embodiments of the present application may be applicable to various channel coding, for example, an LDPC code, a Turbo code, a Polar code, and the like. This embodiment of the present application does not limit this.

此外，本申请提供的交织方法可以作为一个单独的交织模块，用于实现交织处理。也可以作为速率匹配时读取比特的方式，这样就可以将交织和速率匹配集成在一起实现，不需要单独设计交织模块，同样也可以达到与随机交织相同的纠错性能。In addition, the interleaving method provided by the present application can be used as a separate interleaving module for implementing interleaving processing. It can also be used as a way to read bits during rate matching, so that interleaving and rate matching can be integrated. It is not necessary to design an interleaving module separately, and the same error correction performance as random interleaving can be achieved.

另外，本申请实施例的交织方法，对于符号(symbol)序列的交织也是适用的，本领域技术人员根据上面描述的对比特序列进行交织的方法，也可以将其应用于符号序列的交织，本文中不再详述。In addition, the interleaving method in the embodiment of the present application is also applicable to the interleaving of the symbol sequence. The method for interleaving the bit sequence according to the above description may also be applied to the interleaving of the symbol sequence. No longer detailed.

此外，本申请提供一种计算机可读存储介质，该计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行上述各实施例中的交织方法。Moreover, the present application provides a computer readable storage medium having instructions stored therein that, when executed on a computer, cause the computer to perform the interleaving method of the various embodiments described above.

本申请还提供一种计算机程序产品，该计算机程序产品包括：计算机程序代码，当该计算机程序代码在计算机上运行时，使得计算机执行上述实施例中描述的交织方法。The application also provides a computer program product comprising: computer program code for causing a computer to perform the interleaving method described in the above embodiments when the computer program code is run on a computer.

本申请还提供一种芯片，包括存储器和处理器，存储器用于存储计算机程序，处理器用于从存储器中调用并运行该计算机程序，使得安装有该芯片的通信设备执行上述实施例中描述的交织方法。The present application also provides a chip comprising a memory for storing a computer program, the processor for calling and running the computer program from the memory, such that the communication device on which the chip is mounted performs the interleaving described in the above embodiments method.

其中，这里所说的通信设备可以为网络设备或终端设备。The communication device mentioned herein may be a network device or a terminal device.

本申请还提供一种编码装置，该编码装置具有实现上述实施例中描述的交织方法的功能。这些功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的模块。除此之外，编码装置还具有实现编码的相关功能。编码装置对待编码序列进行编码后，采用本申请实施例的交织方法，对编码后的序列进行交织。或者，该编码装置也可以将本申请实施例的交织方法应用在速率匹配，这样可以省掉交织模块，但是同样会起到提高纠错性能的作用。The present application also provides an encoding apparatus having a function of implementing the interleaving method described in the above embodiments. These functions can be implemented in hardware or in software by executing the corresponding software. The hardware or software includes one or more modules corresponding to the functions described above. In addition to this, the encoding device also has a related function for implementing encoding. After the encoding apparatus encodes the encoded sequence, the encoded sequence is interleaved by using the interleaving method of the embodiment of the present application. Alternatively, the encoding apparatus may also apply the interleaving method of the embodiment of the present application to rate matching, so that the interleaving module may be omitted, but the effect of improving error correction performance is also improved.

在一个可能的设计中，当这些功能的部分或全部通过硬件实现时，编码装置包括：In one possible design, when some or all of these functions are implemented by hardware, the encoding device includes:

输入接口电路，用于获取第一比特序列；An input interface circuit, configured to acquire a first bit sequence;

逻辑电路，用于执行上述实施例中描述的交织方法。具体用于：根据所述N个第一比特序列，生成第一交织矩阵，所述第一矩阵为l×l，A logic circuit for performing the interleaving method described in the above embodiments. Specifically, the method is: generating a first interlace matrix according to the N first bit sequences, where the first matrix is 1×1,

输出接口电路，用于输出所述第二比特序列；An output interface circuit, configured to output the second bit sequence;

在一个可能的设计中，当这些功能的部分或全部通过软件实现时，编码装置包括：存储器，用于存储计算机程序；处理器，用于执行存储器存储的计算机程序，当所述计算机程序被执行时，编码装置可以实现上述实施例中任意一种可能的设计中所述的交织方法。In one possible design, when some or all of these functions are implemented by software, the encoding device includes: a memory for storing a computer program; a processor, a computer program for executing memory storage, when the computer program is executed The encoding apparatus may implement the interleaving method described in any of the possible designs of the above embodiments.

在一个可能的设计中，当这些功能的部分或全部通过软件实现时，编码装置包括处理器。用于存储计算机程序的存储器位于编码装置之外，处理器通过电路/电线与存储器连接，用于读取并执行存储器中存储的计算机程序。In one possible design, when some or all of these functions are implemented by software, the encoding device includes a processor. A memory for storing a computer program is located outside of the encoding device, and the processor is coupled to the memory through a circuit/wire for reading and executing a computer program stored in the memory.

相对应地，本申请提供一种解交织的装置，用于实现解交织的方法中的相应功能。这些功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。Correspondingly, the present application provides a deinterleaving device for implementing corresponding functions in the method of deinterleaving. These functions can be implemented in hardware or in software by executing the corresponding software.

本申请提供一种解交织的设备，该设备包括一个或多个处理器，一个或多个存储器，一个或多个收发器(每个收发器包括发射机和接收机)。发射机或接收机通过天线收发信号。存储器用于存储计算机程序指令(或者，代码)。处理器用于执行存储器中存储的指令，当指令被执行时，处理器执行解交织的方法。The application provides a deinterleaved device that includes one or more processors, one or more memories, and one or more transceivers (each transceiver including a transmitter and a receiver). The transmitter or receiver transmits and receives signals through the antenna. The memory is used to store computer program instructions (or code). The processor is configured to execute instructions stored in the memory, and when the instructions are executed, the processor performs a method of deinterleaving.

可选的，以上实施例中所述的存储器与存储器可以是物理上相互独立的单元，或者，存储器也可以和处理器集成在一起。Optionally, the memory and the memory described in the foregoing embodiments may be physically independent units, or the memory may be integrated with the processor.

以上实施例中，处理器可以为中央处理器(Central Processing Unit，CPU)、微处理器、特定应用集成电路(Application-Specific Integrated Circuit，ASIC)，或一个或多个用于控制本申请方案程序执行的集成电路等。例如，处理器可以包括数字信号处理器设备、微处理器设备、模数转换器、数模转换器等。处理器可以根据这些设备各自的功能而在这些设备之间分配移动设备的控制和信号处理的功能。此外，处理器可以包括操作一个或多个软件程序的功能，软件程序可以存储在存储器中。In the above embodiment, the processor may be a central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more programs for controlling the program of the present application. Execution of integrated circuits, etc. For example, the processor can include a digital signal processor device, a microprocessor device, an analog to digital converter, a digital to analog converter, and the like. The processor can distribute the control and signal processing functions of the mobile device among the devices according to their respective functions. Additionally, the processor can include functionality to operate one or more software programs, which can be stored in memory.

处理器的所述功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的模块。The functions of the processor may be implemented by hardware or by software executing corresponding software. The hardware or software includes one or more modules corresponding to the functions described above.

存储器可以是只读存储器(Read-Only Memory，ROM)或可存储静态信息和指令的其他类型的静态存储设备，随机存取存储器(Random Access Memory，RAM)或者可存储信息和指令的其他类型的动态存储设备。也可以是电可擦可编程只读存储器(Electrically Erasable Programmable Read-Only Memory，EEPROM)、只读光盘(Compact Disc Read-Only Memory，CD-ROM)或其他光盘存储、光碟存储(包括压缩光碟、激光碟、光碟、数字通用光碟、蓝光光碟等)、磁盘存储介质或者其他磁存储设备、或者能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质，但不限于此。The memory may be a Read-Only Memory (ROM) or other type of static storage device that can store static information and instructions, a Random Access Memory (RAM) or other type that can store information and instructions. Dynamic storage device. It can also be an Electrically Erasable Programmable Read-Only Memory (EEPROM), a Compact Disc Read-Only Memory (CD-ROM) or other optical disc storage, or a disc storage (including a compact disc, a laser disc, a compact disc, a digital versatile disc, a Blu-ray disc, etc.), a disk storage medium or other magnetic storage device, or any other device that can be used to carry or store desired program code in the form of an instruction or data structure and accessible by a computer. Medium, but not limited to this.

结合前面的描述，本领域的技术人员可以意识到，本文实施例的方法，可以通过硬件(例如，逻辑电路)，或者软件，或者硬件与软件的结合来实现。这些方法究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。In view of the foregoing description, those skilled in the art will appreciate that the methods of the embodiments herein may be implemented by hardware (eg, logic circuitry), or software, or a combination of hardware and software. Whether these methods are implemented in hardware or software depends on the specific application and design constraints of the solution. A person skilled in the art can use different methods to implement the described functions for each particular application, but such implementation should not be considered to be beyond the scope of the present application.

当上述功能通过软件的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。在这种情况下，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。When the above functions are implemented in the form of software and sold or used as stand-alone products, they can be stored in a computer readable storage medium. In this case, the part of the technical solution of the present application, which contributes in essence or to the prior art, or part of the technical solution, may be embodied in the form of a software product stored in a storage medium. A number of instructions are included to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like, which can store program codes. .

以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。The foregoing is only a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto, and any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present application. It should be covered by the scope of protection of this application. Therefore, the scope of protection of the present application should be determined by the scope of the claims.

Claims

一种交织方法，其特征在于，包括：An interleaving method, comprising:

获得N个第一比特序列，所述N为整数；Obtaining N first bit sequences, the N being an integer;

根据所述N个第一比特序列，生成第一交织矩阵，所述第一矩阵为l×l，Generating, according to the N first bit sequences, a first interlace matrix, where the first matrix is 1×1,

表示向上取整；
Indicates rounding up;

根据第一循环移位序列对所述第一矩阵进行第一循环移位，获得第二矩阵，其中，所述第一循环移位序列包括J个比特，J≥2且为整数；Performing a first cyclic shift on the first matrix according to the first cyclic shift sequence to obtain a second matrix, where the first cyclic shift sequence includes J bits, J≥2 and is an integer;

根据第二循环移位序列对所述第二矩阵进行第二循环移位，获得第三矩阵，其中，所述第二循环移位序列包括S个比特，S≥2且为整数；Performing a second cyclic shift on the second matrix according to the second cyclic shift sequence to obtain a third matrix, where the second cyclic shift sequence includes S bits, S≥2 and is an integer;

根据所述第三矩阵，获得N个第二比特序列；Obtaining N second bit sequences according to the third matrix;

输出所述第二比特序列。The second bit sequence is output.
根据权利要求1所述的方法，其特征在于，所述方法还包括：The method of claim 1 further comprising:

根据所述一循环移位序列，生成所述第二循环移位序列。Generating the second cyclic shift sequence according to the cyclic shift sequence.
根据权利要求2所述的方法，其特征在于，所述方法具体包括：The method of claim 2, wherein the method specifically comprises:

所述第二循环移位序列包括的比特值为所述第一循环移位序列对应的比特值的倍数或者分数，或者所述所述第二循环移位序列通过对所述第一循环移位序列进行顺序变换获得。The second cyclic shift sequence includes a bit value that is a multiple or a fraction of a bit value corresponding to the first cyclic shift sequence, or the second cyclic shift sequence is shifted by the first cyclic The sequence is obtained by sequential transformation.
根据权利要求2所述的方法，其特征在于，所述方法具体包括：The method of claim 2, wherein the method specifically comprises:

从所述J个第一循环移位序列中截取S个循环移位序列，作为所述第二循环移位序列；所截取方式包括下面的任意一种组合：按照比特的先后顺序，从后向前截取S个的比特、按照比特的先后顺序，从前向后截取S个的比特，或者，按照比特的先后顺序，从后向前截取S1个的比特以及按照比特的先后顺序，从前向后截取S2个的比特，其中，S1+S2＝S，S1为整数，S2为整数，或者按照比特的先后顺序，从后向前截取S1个的比特以及按照比特的先后顺序，从前向后截取S2个的比特，其中，S1+S2＝S，S1为整数，S2为整数。S cyclic shifting sequences are intercepted from the J first cyclic shifting sequences as the second cyclic shifting sequence; the intercepting manner includes any combination of the following: in the order of bits, from the backward S bits are intercepted in advance, and S bits are intercepted from front to back according to the order of the bits, or S1 bits are intercepted from the back and the front in the order of the bits, and are read from the front to the back according to the order of the bits. S2 bits, where S1+S2=S, S1 is an integer, S2 is an integer, or S1 bits are intercepted from the back and the front in the order of the bits, and S2 are cut from the front to the back according to the order of the bits. Bits, where S1+S2=S, S1 is an integer, and S2 is an integer.
根据权利要求2所述的方法，其特征在于，所述方法具体包括：The method of claim 2, wherein the method specifically comprises:

从所述J个第一循环移位序列中截取S个循环移位序列，所截取方式包括下面的任意一种组合：按照比特的先后顺序从后向前截取S个循环移位序列、按照比特的先后顺序从前向后截取S个循环移位序列；S cyclic shifting sequences are intercepted from the J first cyclic shift sequences, and the intercepting manner includes any combination of the following: intercepting S cyclic shift sequences from the back to the front in order of bits, according to bits The sequence of S is sequentially shifted backwards and backwards;

对所述截取的S个循环移位序列进行顺序变换，将顺序变换后的S个循环移位序列作为第二循环移位序列。The sequentially intercepted S cyclic shift sequences are sequentially transformed, and the sequentially transformed S cyclic shift sequences are used as the second cyclic shift sequence.
根据权利要求1所述的方法，其特征在于，所述第一循环移位序列与所述第二循环移位序列可以从预先配置的L个最长循环移位序列中获取，所述J小于L，所述S小于L，所述L为整数。The method according to claim 1, wherein said first cyclic shift sequence and said second cyclic shift sequence are obtainable from pre-configured L longest cyclic shift sequences, said J being smaller than L, the S is smaller than L, and the L is an integer.
一种交织装置，其特征在于，包括：An interlacing device, comprising:

输入接口电路，用于获得N个第一比特序列，所述N为整数；An input interface circuit, configured to obtain N first bit sequences, where N is an integer;

逻辑电路，用于根据所述N个第一比特序列，生成第一交织矩阵，所述第一矩阵为l×l，a logic circuit, configured to generate a first interlace matrix according to the N first bit sequences, where the first matrix is 1×1,

表示向上取整；根据第一循环移位序列对所述第一矩阵进行第一循环移位，获得第二矩阵，其中，所述第一循环移位序列包括J个比特，J≥2且为整数；根据第二循环移位序列对所述第二矩阵进行第二循环移位，获得第三矩阵，其中，所述第二循环移位序列包括S个比特，S≥2且为整数；根据所述第三矩阵，获得N个第二比特序列；
Representing rounding up; performing a first cyclic shift on the first matrix according to the first cyclic shift sequence to obtain a second matrix, wherein the first cyclic shift sequence includes J bits, J≥2 and An integer; performing a second cyclic shift on the second matrix according to the second cyclic shift sequence to obtain a third matrix, wherein the second cyclic shift sequence includes S bits, S≥2 and is an integer; The third matrix obtains N second bit sequences;

输出接口电路，用于输出所述第二比特序列。An output interface circuit for outputting the second bit sequence.
根据权利要求7所述的装置，其特征在于，所述逻辑电路还用于，根据所述一循环移位序列，生成所述第二循环移位序列。The apparatus according to claim 7, wherein said logic circuit is further configured to generate said second cyclic shift sequence according to said cyclic shift sequence.
根据权利要求8所述的装置，其特征在于，所述逻辑电路具体用于，所述第二循环移位序列包括的比特值为所述第一循环移位序列对应的比特值的倍数或者分数，或者所述所述第二循环移位序列通过对所述第一循环移位序列进行顺序变换获得。The apparatus according to claim 8, wherein the logic circuit is configured to: the second cyclic shift sequence comprises a bit value that is a multiple or a fraction of a bit value corresponding to the first cyclic shift sequence. Or the second cyclic shift sequence is obtained by sequentially transforming the first cyclic shift sequence.
根据权利要求8所述的装置，其特征在于，所述逻辑电路具体用于，从所述J个第一循环移位序列中截取S个循环移位序列，作为所述第二循环移位序列；所截取方式包括下面的任意一种组合：按照比特的先后顺序从后向前截取S个的比特、按照比特的先后顺序从前向后截取S个的比特，或者，按照比特的先后顺序，从后向前截取S1个的比特以及按照比特的先后顺序，从前向后截取S2个的比特，其中，S1+S2＝S，S1为整数，S2为整数。The apparatus according to claim 8, wherein the logic circuit is specifically configured to intercept S cyclic shift sequences from the J first cyclic shift sequences as the second cyclic shift sequence The interception method includes any combination of the following: S bits are intercepted from the back to the front in the order of the bits, S bits are intercepted from the front to the back in the order of the bits, or, in the order of the bits, S1 bits are truncated backward and S2 bits are intercepted from front to back according to the order of the bits, where S1+S2=S, S1 is an integer, and S2 is an integer.
根据权利要求8所述的装置，其特征在于，所述逻辑电路具体用于，从所述J个第一循环移位序列中截取S个循环移位序列，所截取方式包括下面的任意一种组合：按照比特的先后顺序从后向前截取S个循环移位序列、按照比特的先后顺序从前向后截取S个循环移位序列；The apparatus according to claim 8, wherein the logic circuit is configured to intercept S cyclic shift sequences from the J first cyclic shift sequences, and the intercepting manner includes any one of the following Combining: S cyclic shift sequences are intercepted from the back and the front in the order of bits, and S cyclic shift sequences are intercepted from front to back in order of bits;

对所述截取的S个循环移位序列进行顺序变换，将顺序变换后的S个循环移位序列作为第二循环移位序列。The sequentially intercepted S cyclic shift sequences are sequentially transformed, and the sequentially transformed S cyclic shift sequences are used as the second cyclic shift sequence.
根据权利要求8所述的装置，其特征在于，所述逻辑电路具体用于，从预先配置的L个最长循环移位序列中获取所述第一循环移位序列；以及从预先配置的L个最长循环移位序列中获取所述第二循环移位序列，所述J小于L，所述S小于L，所述L为整数。The apparatus according to claim 8, wherein the logic circuit is specifically configured to: acquire the first cyclic shift sequence from pre-configured L longest cyclic shift sequences; and from a pre-configured L The second cyclic shift sequence is obtained in a longest cyclic shift sequence, the J is smaller than L, the S is smaller than L, and the L is an integer.
一种交织装置，其特征在于，所述装置包括：An interlacing device, characterized in that the device comprises:

处理器，用于根据N个第一比特序列，生成第一交织矩阵，所述第一矩阵为l×l，a processor, configured to generate a first interlace matrix according to the N first bit sequences, where the first matrix is 1×1,

表示向上取整；根据第一循环移位序列对所述第一矩阵进行第一循环移位，获得第二矩阵，其中，所述第一循环移位序列包括J个比特，J≥2且为整数；根据第二循环移位序列对所述第二矩阵进行第二循环移位，获得第三矩阵，其中，所述第二循环移位序列包括S个比特，S≥2且为整数；根据所述第三矩阵，获得N个第二比特序列。
Representing rounding up; performing a first cyclic shift on the first matrix according to the first cyclic shift sequence to obtain a second matrix, wherein the first cyclic shift sequence includes J bits, J≥2 and An integer; performing a second cyclic shift on the second matrix according to the second cyclic shift sequence to obtain a third matrix, wherein the second cyclic shift sequence includes S bits, S≥2 and is an integer; The third matrix obtains N second bit sequences.
根据权利要求13所述的装置，其特征在于，所述处理器还用于，根据所述一循环移位序列，生成所述第二循环移位序列。The apparatus according to claim 13, wherein the processor is further configured to generate the second cyclic shift sequence according to the cyclic shift sequence.
根据权利要求14所述的装置，其特征在于，所述处理器具体用于，所述第二循环移位序列包括的比特值为所述第一循环移位序列对应的比特值的倍数或者分数，或者所述所述第二循环移位序列通过对所述第一循环移位序列进行顺序变换获得。The apparatus according to claim 14, wherein the processor is specifically configured to: the second cyclic shift sequence includes a bit value that is a multiple or a fraction of a bit value corresponding to the first cyclic shift sequence. Or the second cyclic shift sequence is obtained by sequentially transforming the first cyclic shift sequence.
根据权利要求14所述的装置，其特征在于，所述处理器具体用于，从所述J个第一循环移位序列中截取S个循环移位序列，作为所述第二循环移位序列；所截取方式包括下面的任意一种组合：按照比特的先后顺序从后向前截取S个的比特、按照比特的先后顺序从前向后截取S个的比特，或者按照比特的先后顺序，从后向前截取S1个的比特以及按照比特的先后顺序，从前向后截取S2个的比特，其中，S1+S2＝S，S1为整数，S2为整数。The apparatus according to claim 14, wherein the processor is specifically configured to intercept S cyclic shift sequences from the J first cyclic shift sequences as the second cyclic shift sequence The interception method includes any combination of the following: S bits are intercepted from the back to the front in the order of the bits, S bits are intercepted from the front to the back in the order of the bits, or in the order of the bits, from the back S1 bits are intercepted forward and S2 bits are intercepted from front to back according to the order of the bits, where S1+S2=S, S1 is an integer, and S2 is an integer.
根据权利要求14所述的装置，其特征在于，所述处理器具体用于，从所述J个第一循环移位序列中截取S个循环移位序列，所截取方式包括下面的任意一种组合：按照比特的先后顺序从后向前截取S个循环移位序列、按照比特的先后顺序从前向后截取S个循环移位序列；The apparatus according to claim 14, wherein the processor is specifically configured to intercept S cyclic shift sequences from the J first cyclic shift sequences, and the intercepting manner includes any one of the following Combining: S cyclic shift sequences are intercepted from the back and the front in the order of bits, and S cyclic shift sequences are intercepted from front to back in order of bits;

对所述截取的S个循环移位序列进行顺序变换，将顺序变换后的S个循环移位序列作为第二循环移位序列。The sequentially intercepted S cyclic shift sequences are sequentially transformed, and the sequentially transformed S cyclic shift sequences are used as the second cyclic shift sequence.
根据权利要求14所述的装置，其特征在于，所述处理器具体用于，从预先配置的L个最长循环移位序列中获取所述第一循环移位序列；以及从预先配置的L个最长循环移位序列中获取所述第二循环移位序列，所述J小于L，所述S小于L，所述L为整数。The apparatus according to claim 14, wherein the processor is specifically configured to: acquire the first cyclic shift sequence from pre-configured L longest cyclic shift sequences; and from a pre-configured L The second cyclic shift sequence is obtained in a longest cyclic shift sequence, the J is smaller than L, the S is smaller than L, and the L is an integer.
一种交织装置，其特征在于，所述装置包括：An interlacing device, characterized in that the device comprises:

接收单元，用于接收N个第一比特序列，所述N为整数；a receiving unit, configured to receive N first bit sequences, where N is an integer;

处理单元，用于根据所述N个第一比特序列，生成第一交织矩阵，所述第一矩阵为l×l，a processing unit, configured to generate, according to the N first bit sequences, a first interlace matrix, where the first matrix is 1×1,

表示向上取整；根据第一循环移位序列对所述第一矩阵进行第一循环移位，获得第二矩阵，其中，所述第一循环移位序列包括J个比特，J≥2且为整数；根据第二循环移位序列对所述第二矩阵进行第二循环移位，获得第三矩阵，其中，所述第二循环移位序列包括S个比特，S≥2且为整数；根据所述第三矩阵，获得N个第二比特序列；
Representing rounding up; performing a first cyclic shift on the first matrix according to the first cyclic shift sequence to obtain a second matrix, wherein the first cyclic shift sequence includes J bits, J≥2 and An integer; performing a second cyclic shift on the second matrix according to the second cyclic shift sequence to obtain a third matrix, wherein the second cyclic shift sequence includes S bits, S≥2 and is an integer; The third matrix obtains N second bit sequences;

发送单元，用于输出所述第二比特序列。And a sending unit, configured to output the second bit sequence.
根据权利要求19所述的装置，其特征在于，所述处理单元还用于，根据所述一循环移位序列，生成所述第二循环移位序列。The apparatus according to claim 19, wherein the processing unit is further configured to generate the second cyclic shift sequence according to the cyclic shift sequence.
根据权利要求20所述的装置，其特征在于，所述处理器具体用于，所述第二循环移位序列包括的比特值为所述第一循环移位序列对应的比特值的倍数或者分数，或者所述所述第二循环移位序列通过对所述第一循环移位序列进行顺序变换获得。The apparatus according to claim 20, wherein the processor is specifically configured to: the second cyclic shift sequence includes a bit value that is a multiple or a fraction of a bit value corresponding to the first cyclic shift sequence. Or the second cyclic shift sequence is obtained by sequentially transforming the first cyclic shift sequence.
根据权利要求20所述的装置，其特征在于，所述处理器具体用于，从所述J个第一循环移位序列中截取S个循环移位序列，作为所述第二循环移位序列；所截取方式包括下面的任意一种组合：按照比特的先后顺序从后向前截取S个的比特、按照比特的先后顺序从前向后截取S个的比特，或者按照比特的先后顺序，从后向前截取S1个的比特以及按照比特的先后顺序，从前向后截取S2个的比特，其中，S1+S2＝S，S1为整数，S2为整数。The apparatus according to claim 20, wherein the processor is specifically configured to intercept S cyclic shift sequences from the J first cyclic shift sequences as the second cyclic shift sequence The interception method includes any combination of the following: S bits are intercepted from the back to the front in the order of the bits, S bits are intercepted from the front to the back in the order of the bits, or in the order of the bits, from the back S1 bits are intercepted forward and S2 bits are intercepted from front to back according to the order of the bits, where S1+S2=S, S1 is an integer, and S2 is an integer.
根据权利要求20所述的装置，其特征在于，所述处理器具体用于，从所述J个第一循环移位序列中截取S个循环移位序列，所截取方式包括下面的任意一种组合：按照比特的先后顺序从后向前截取S个循环移位序列、按照比特的先后顺序从前向后截取S个循环移位序列；The apparatus according to claim 20, wherein the processor is specifically configured to intercept S cyclic shift sequences from the J first cyclic shift sequences, and the intercepting manner includes any one of the following Combining: S cyclic shift sequences are intercepted from the back and the front in the order of bits, and S cyclic shift sequences are intercepted from front to back in order of bits;

对所述截取的S个循环移位序列进行顺序变换，将顺序变换后的S个循环移位序列作为第二循环移位序列。The sequentially intercepted S cyclic shift sequences are sequentially transformed, and the sequentially transformed S cyclic shift sequences are used as the second cyclic shift sequence.
根据权利要求20所述的装置，其特征在于，所述处理器具体用于，从预先配置的L个最长循环移位序列中获取所述第一循环移位序列；以及从预先配置的L个最长循环移位序列中获取所述第二循环移位序列，所述J小于L，所述S小于L，所述L为整数。The apparatus according to claim 20, wherein the processor is specifically configured to: acquire the first cyclic shift sequence from pre-configured L longest cyclic shift sequences; and from a pre-configured L The second cyclic shift sequence is obtained in a longest cyclic shift sequence, the J is smaller than L, the S is smaller than L, and the L is an integer.