CN102086020B - For the manufacture of the method for silicon sub-carrier - Google Patents
For the manufacture of the method for silicon sub-carrier Download PDFInfo
- Publication number
- CN102086020B CN102086020B CN201010581224.8A CN201010581224A CN102086020B CN 102086020 B CN102086020 B CN 102086020B CN 201010581224 A CN201010581224 A CN 201010581224A CN 102086020 B CN102086020 B CN 102086020B
- Authority
- CN
- China
- Prior art keywords
- silicon substrate
- insulating barrier
- conductive material
- method step
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 121
- 239000010703 silicon Substances 0.000 title claims abstract description 121
- 238000000034 method Methods 0.000 title claims abstract description 114
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 116
- 239000000758 substrate Substances 0.000 claims abstract description 96
- 239000004020 conductor Substances 0.000 claims abstract description 83
- 230000004888 barrier function Effects 0.000 claims abstract description 51
- 238000009434 installation Methods 0.000 claims abstract description 9
- 238000007639 printing Methods 0.000 claims description 22
- 238000002844 melting Methods 0.000 claims description 8
- 230000008018 melting Effects 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 150000003376 silicon Chemical class 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 claims description 2
- 238000011084 recovery Methods 0.000 claims description 2
- 230000005484 gravity Effects 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000004377 microelectronic Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- 238000010924 continuous production Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000009422 external insulation Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 239000010813 municipal solid waste Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 229920001200 poly(ethylene-vinyl acetate) Polymers 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000003631 wet chemical etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/147—Semiconductor insulating substrates
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
- B81C1/005—Bulk micromachining
- B81C1/00515—Bulk micromachining techniques not provided for in B81C1/00507
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2201/00—Manufacture or treatment of microstructural devices or systems
- B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
- B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
- B81C2201/0128—Processes for removing material
- B81C2201/0143—Focussed beam, i.e. laser, ion or e-beam
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Micromachines (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
The present invention relates to the method for the manufacture of silicon sub-carrier.The present invention relates to a kind of method for the manufacture of silicon sub-carrier (1), for at substrate, especially circuit board is installed microelectromechanicdevices devices and/or there is the electronic installation of integrated circuit, the method comprises following methods step: a) introduce in silicon substrate (3) by laser means by least one recess (2), its center dant (2) extends to the second side (II) from first side (I) of silicon substrate (3), b) at least on the subregion on the surface of silicon substrate (3), the first insulating barrier (4) is constructed, described subregion extends to the second side (II) from first side (I) of silicon substrate (3) by recess (2), and c) conductive material (5) is applied on the first insulating barrier (4) for construct at least one from first side (I) of silicon substrate (3) by recess (2) to the break-through contact site of the second side (II).
Description
Background technology
The present invention relates to a kind of method for the manufacture of silicon sub-carrier and silicon sub-carrier.
Summary of the invention
Microminiaturization is current at IC chip (IC chip, English: " integratedcircuitchips ") and the manufacture of Micro Electronic Mechanical System die (MEMS chip, English: " microelektromechanicalsystemchips ") and interconnection technique in trend.Packed device should be much larger unlike chip itself in the conceived case at this, and this is also referred to as CSP (English: " chipsizepackage (chip size packages) " or " chipscalepackage (wafer-level package) ").Chip (do not have housing ground) is built directly in possibility substrate provided to this, this installs (COB, English: " chiponboard (chip on board) ") also referred to as nude film (English: " baredie ") or nude film.
Nude film when microelectromechanical systems (MSMS) for entertainment electronic devices and household electronic device is installed and is become difficulty due to following reason: product comprises two chips usually, i.e. a Micro Electronic Mechanical System die (MEMS chip) and a special circuit chip (asic chip).If directly build two chips on substrate, then these chips individually must be supplied to client, and it jointly can not be corrected or is tested in advance.In addition, Micro Electronic Mechanical System die is responsive for mechanical stress.This mechanical stress can especially occur due to the different heat expansion coefficient of the material for building such as chip, solder flux, substrate when temperature fluctuation, and the Functional Capability of meeting EVAC.
Publication US 7,447,323B2 describes a kind of device, and wherein especially microphone and the device comprising integrated circuit are arranged on the first side of the silicon sub-carrier of silicon formation conversion element abreast.Silicon sub-carrier has the break-through contact site of the first side to the second side of silicon sub-carrier from silicon sub-carrier, the conversion element on the first side or electronic installation to be electrically connected with the such as circuit board of the substrate on the second side being arranged on silicon sub-carrier by break-through contact site.By silicon sub-carrier, the thermal and mechanical stress of substrate to conversion element or electronic installation can be reduced at this.
Publication US 7,447,323B2 proposes and manufactures break-through contact site by etching, especially wet chemical etching or plasma etching and metallization subsequently.But particularly due to engraving method, the method according to publication US 7,447,323B2 is associated with higher manufacturing cost.
Summary of the invention
Theme of the present invention is a kind of method for the manufacture of silicon sub-carrier, and silicon sub-carrier for installing microelectromechanicdevices devices and/or having the electronic installation of integrated circuit on substrate, especially circuit board, and the method comprises following methods step:
A) introduced in silicon substrate by least one recess by laser means, such as laser ablation method, its center dant extends to the second side from the first side of silicon substrate,
B) at least on the subregion on the surface of silicon substrate, construct the first insulating barrier, described subregion extends to the second side from the first side of silicon substrate by recess, and
C) conductive material is applied to the first insulating barrier is used for construct at least one from the first side of silicon substrate the break-through contact site by recess to the second side.
The advantage that method according to the present invention has is, it can realize manufacturing extremely cheap for silicon sub-carrier cost.Thus, especially can realize the material advantages on thermal coefficient of expansion basis of silicon relative to plastic silicon sub-carrier when considering cost pressure.Advantageously, the method for the manufacture of silicon sub-carrier according to the present invention is without the need to photoetching method and/or engraving method.In addition, not necessarily clean room environment is needed to realize.
This laser means can advantageously be carried out with very high speed.Show, the coarse surface that may occur in laser means or residue (discarded object in laser drill) can be advantageously used in the attachment of conductive material.
Method step a) in can introduce at least one recess particularly by laser drill.Correspondingly, recess also can be called the hole through silicon substrate.
In the scope of a form of implementation of the method, method step a) in addition especially by laser means introduce alignment mark, such as, for later divided silicon substrate and/or for locating described device later.
In the scope of another form of implementation of the method, at method step b) in construct the first insulating barrier by the oxidation on the surface of silicon substrate.This advantageously can act on the coarse surface or residue (discarded object in laser drill) that may occur in laser means.At method step b) in, the first insulating barrier can by constructing at least in part and by the surface of fully silicon oxide substrate.Being oxidized completely of surface can be implemented by less technology expense at this.
In the scope of another form of implementation of the method, at method step b) in by by the surface heat of silicon substrate oxidation construct the first insulating barrier.This such as can carry out in the stove under oxidizing atmosphere, especially contains in the atmosphere of oxygen, carries out in such as air.By thermal oxide, silicon substrate can be insulated all sidedly.
In the scope of another form of implementation of the method, at method step b) and/or c) in especially side by side also at least one first electric printed conductor is configured to silicon substrate by least one break-through contact site described the first side and/or the second side on, wherein at method step b) in the first insulating barrier is at least configured on the subregion on the surface of silicon substrate, wherein at method step c) on these subregions structure at least one first electric printed conductor described.
In the scope of another form of implementation of the method, at method step c) in apply conductive material by printing process, especially method for printing screen.Typography can advantageously cost be very cheap, and implements in a continuous process.In addition, can advantageously realize having width by printing process is be more than or equal to the printed conductor of 100 μm.
Method step c) can method step be subdivided into
C1) conductive material is applied on the first insulating barrier on the first side of silicon substrate, and method step
C2) conductive material is applied on the first insulating barrier on the second side of silicon substrate.
In the scope of another form of implementation of the method, the method is at method step c) after comprise method step:
D) silicon substrate (3) is heated to the temperature of conductive material (5) melting, and the temperature being cooled to conductive material (5) to harden silicon substrate (3) subsequently.
In this way, conductive material can be ensured on the one hand to be connected to better on the first insulating barrier.On the other hand, the conductive material that can make to be applied on the first side of silicon substrate and/or the second side to flow in recess and constructs break-through contact site.
In the scope of another form of implementation of the method, methods && steps of implementation d in a vacuum).In this way, the field trash in conductive material can be avoided.
In the scope of another form of implementation of the method, method step c) and d) be subdivided into following method step c1) and c2) and d1) and d2):
C1) conductive material is applied on the first insulating barrier on the first side of silicon substrate,
D1) silicon substrate first is heated to the temperature of conductive material melting, and the temperature being cooled to conductive material to harden silicon substrate subsequently.
C2) conductive material is applied on first insulating barrier of the second side of silicon substrate, and
D2) silicon substrate second is heated to the temperature of conductive material melting, and the temperature being cooled to conductive material to harden silicon substrate subsequently.
At this, silicon substrate can at method step d1) and method step c2) between such as rotate 180 ° around the axis in substrate plane.At method step d1) in, silicon substrate is preferably arranged so that the first side of silicon substrate is positioned at top about gravity direction.At method step d2) in, silicon substrate is preferably arranged so that the second side of silicon substrate is positioned at top about gravity direction.In this way, conductive material can flow by gravity in recess respectively.
The method can at method step c) and/or d) after also comprise method step
E1) at least one second insulating barrier is applied.
Second insulating barrier can partly be applied on the first insulating barrier, especially not capped region at this, region that such as do not cover with at least one first electric printed conductor described, the first insulating barrier and/or be partly applied at least one break-through contact site described and/or be partly applied at least one electric printed conductor described.
Such as, the second insulating barrier can be applied for and make at least one first electric printed conductor described form border by the second insulating barrier laterally.In this way, at least one first electric printed conductor described can be prevented at method step d) in heating hour offset or lose profile.
To this alternatively or additionally, second insulating barrier can partly be applied at least one break-through contact site described or at least one first electric printed conductor described, and a part at least one break-through contact site described or at least one the first electric printed conductor described is not covered by the second insulating barrier to contact break-through contact site or the first electric printed conductor.In this way, break-through contact site or the first electric printed conductor can partially to external insulation and still can partly can from external contacts.
Being applied to this and can carrying out in one step or in two or more steps of second insulating barrier.Such as, the second insulating barrier can be applied to the first and/or second side of silicon supporting body by (except the region for contacting break-through contact site or the first electric printed conductor) plane earth in one step.But, second insulating barrier also can be applied on the first insulating barrier in a first step, at least one first electric printed conductor described is made to form border in side by the second insulating barrier, and to be partly applied in the second step at least one first electric printed conductor described (and being partly applied on the second insulating layer region of manufacturing in a first step), a part at least one the first electric printed conductor described is not covered with the second insulating barrier to contact described first electric printed conductor.The applying of the second insulating barrier can be carried out advantageous by the with low cost and printing process that can implement in a continuous process.
In the scope of another form of implementation of the method, the method is therefore at method step c) and/or d) after comprise method step in addition
E1) at least one second insulating barrier is applied by printing process.
Printing process can be such as seal glass printing process (Sealglasdruck-verfahren) or polymeric printing method at this.Especially, printing process can be method for printing screen.
The method can at method step e1) after comprise method step
E2) at least one second electric printed conductor is applied at least one second insulating barrier described.
Especially, can at method step e2) in by printing process, at least one second electric printed conductor described is applied at least one second insulating barrier described.Printing process can be method for printing screen at this equally.
Especially, method step e1) and e2 can repeatedly alternately in succession carry out.Like this, the staggered of printed conductor can also be realized.
But the staggered of printed conductor also can ensure by the opposite side that by break-through contact site printed conductor guided to silicon sub-carrier.In order to realize interlocking between two printed conductors, one of printed conductor can guide to the opposite side of silicon substrate from the side of silicon substrate by break-through contact site.If desired, a described printed conductor can then be guided to returning again by the second break-through contact site.Such as, printed conductor and break-through contact site can be constructed so that at least one printed conductor arranged on the first side is divided into multiple printed conductor section, especially interlock with another printed conductor be arranged on the first side of silicon substrate to realize, wherein the first printed conductor section contacts the first break-through contact site on the first side of silicon substrate, and wherein the first break-through contact site contacts the second printed conductor section on the second side of silicon substrate.Second printed conductor section can contact the second break-through contact site in addition at this on the second side of silicon substrate, and wherein the second break-through contact site contacts the 3rd printed conductor section on the first side of silicon substrate.
The method in addition can at method step c) and/or d) and/or e) after comprise method step
F) by silicon substrate separation, such as sawing, be especially divided into two or more less silicon substrate, especially multiple less silicon substrate.
By implementing the method and separation subsequently on large silicon substrate, advantageously can manufacture a large amount of silicon sub-carrier within the short time, and reducing manufacturing cost further.
In the scope of another form of implementation of the method, silicon substrate is constructed by polysilicon and/or the silicon of low-purity (metallurgy grade) and/or the silicon of recovery.In this way, advantageously manufacturing cost can be reduced further.
First side and second side of silicon substrate can be opposite each other.Especially the first side of substrate and the second side can be substantially parallel to each other.
Silicon sub-carrier can comprise first group of contact element on the first side, is especially selected from the contact element of the group be made up of printed conductor and break-through contact site, for contacting microelectromechanicdevices devices; And comprise second group of contact element, be especially selected from the contact element of the group be made up of printed conductor and break-through contact site, for contacting the electronic installation with integrated circuit.On the second side, silicon sub-carrier can comprise another group contact element, especially be selected from the contact element of the group be made up of printed conductor and break-through contact site, for contact circuit plate, wherein one of be at least electrically connected with the contact element of described first group or second group.Microelectromechanicdevices devices can be such as pressure sensor or acceleration transducer or speed probe or microelectron-mechanical actuator.Electronic installation such as can have special circuit (ASIC) as integrated circuit.
Another theme of the present invention is a kind of silicon sub-carrier, and manufacture especially by method according to the present invention, the feature of this silicon sub-carrier is, it at least comprises:
-the recess introduced by laser means, and/or
-the alignment mark introduced by laser means, and/or
-by printing process, especially method for printing screen apply printed conductor,
-as the first insulating barrier, silicon oxide layer that silicon substrate is surrounded especially completely, and/or
-by printing process, especially method for printing screen apply the second insulating barrier.
Silicon sub-carrier can comprise first group of contact element on the first side, is especially selected from the contact element of the group be made up of printed conductor and break-through contact site, for contacting microelectromechanicdevices devices; And comprise second group of contact element, be especially selected from the contact element of the group be made up of printed conductor and break-through contact site, for contacting the electronic installation with integrated circuit.On the second side, silicon sub-carrier can comprise another group contact element, especially be selected from the contact element of the group be made up of printed conductor and break-through contact site, for contact circuit plate, wherein one of be at least electrically connected with the contact element of described first group or second group.Microelectromechanicdevices devices can be such as pressure sensor or acceleration transducer.Electronic installation such as can have special circuit (ASIC) as integrated circuit.
Accompanying drawing explanation
To be represented by accompanying drawing according to other advantages of theme of the present invention and favourable expansion scheme and set forth in the following description.Here, it is noted that the accompanying drawing only descriptive feature of tool, and and not intended to be limits the present invention in any form.Wherein:
Fig. 1 shows the schematic cross-section of an embodiment according to silicon sub-carrier of the present invention.
Detailed description of the invention
Fig. 1 shows silicon sub-carrier 1 and has silicon substrate 3, and this silicon substrate 3 is with the first side I and the second side II with the first side I parallel opposed.Introduce in this silicon substrate 3 by laser means by recess 2, this recess extends to the second side II from the first side I of silicon substrate 3.Then, constructed the silicon oxide layer 4 surrounding silicon substrate 3 completely by the oxidation on the surface of silicon substrate, it is used as the first insulating barrier.
Subsequently, by conductive material 5 in order to construct penetrating part 6 and electric printed conductor 7 and first be applied on the first insulating barrier 4 on the first side I of silicon substrate 3.Simultaneously or subsequently, the region of the second insulating barrier 8 is applied to by printing process on the first insulating barrier 4 on the first side I of silicon substrate 3, makes electric printed conductor 7 form border in side by the second insulating layer region 8.Subsequently, silicon substrate 3 first time is heated to the temperature of conductive material 5 melting, and is cooled to again the temperature that conductive material 5 hardens.At this, silicon substrate 3 is arranged so that the first side I of silicon substrate 3 is positioned at top about gravity direction.In this way, the conductive material 5 be applied on the first side I of silicon substrate 3 can to flow in recess 2 and to construct the Part I of break-through contact site 6.Subsequently, silicon substrate 3 is rotated 180 ° around the axis in substrate plane, silicon substrate 3 is arranged so that, and the second side II of silicon substrate 3 is positioned at top about gravity direction.Subsequently, by conductive material 5 in order to construct break-through contact site 6 and electric printed conductor 7 and be applied on the first insulating barrier 4 on the second side II of silicon substrate 3.Simultaneously or subsequently, the region of the second insulating barrier 8 is applied to by printing process on the first insulating barrier 4 on the second side II of silicon substrate 3, makes electric printed conductor 7 form border in side by the second insulating layer region 8.Subsequently, silicon substrate 3 second time is heated to the temperature of conductive material 5 melting, and is then cooled to the temperature that conductive material 5 hardens.In this way, the conductive material 5 be applied on the second side II of silicon substrate 3 to flow in recess 2 and constructs the Part II of break-through contact site 6.
Subsequently, on both sides I, II of silicon sub-carrier 1, the other region of the second insulating barrier 8 is applied respectively by printing process, wherein the second insulating barrier 8 other area part to be applied on printed conductor 7 and to be partly applied on the second insulating layer region 8 of manufacturing in advance, a part for printed conductor 7 is not covered by the second insulating barrier 8 respectively in order to later contact.
Claims (10)
1., for the manufacture of a method for silicon sub-carrier (1), this silicon sub-carrier is for the electronic installation installing microelectromechanicdevices devices and/or have integrated circuit on substrate, and the method comprises following methods step:
A) introduced in silicon substrate (3) by least one recess (2) by laser means, its center dant (2) extends to the second side (II) from first side (I) of silicon substrate (3),
B) at least on the subregion on the surface of silicon substrate (3), construct the first insulating barrier (4), described subregion extends to the second side (II) from first side (I) of silicon substrate (3) by recess (2), and
C) conductive material (5) is applied on the first insulating barrier (4) for construct at least one from first side (I) of silicon substrate (3) by recess (2) to the break-through contact site of the second side (II),
Wherein at method step c) after comprise method step:
D) silicon substrate (3) is heated to the temperature of conductive material (5) melting, and the temperature being cooled to conductive material (5) to harden silicon substrate (3) subsequently.
2. method according to claim 1, is characterized in that, this external method step is a) middle introduces alignment mark.
3. method according to claim 1 and 2, is characterized in that, at method step b) in construct the first insulating barrier (4) by the oxidation on the surface of silicon substrate (3).
4. according to the method one of claim 1 to 2 Suo Shu, it is characterized in that, at method step b) in by by the surface heat of silicon substrate (3) oxidation construct the first insulating barrier (4).
5. according to the method one of claim 1 to 2 Suo Shu, it is characterized in that, at method step b) and c) in also at least one first electric printed conductor (7) is configured to silicon substrate (3) by least one break-through contact site (6) the first side (I) and/or the second side (II) on, wherein at method step b) in the first insulating barrier (4) is at least configured on the subregion on the surface of silicon substrate (3), wherein on these subregions at method step c) in structure at least one first electric printed conductor (7) described.
6. according to the method one of claim 1 to 2 Suo Shu, it is characterized in that, at method step c) in apply conductive material (5) by printing process.
7. method according to claim 1, is characterized in that, in a vacuum methods && steps of implementation d).
8. according to the method one of claim 1 to 2 Suo Shu, it is characterized in that, method step c) and d) be subdivided into following method step c1) and c2) and d1) and d2):
C1) conductive material (5) is applied on the first insulating barrier (4) on first side (I) of silicon substrate (3),
D1) is heated to the temperature of conductive material (5) melting silicon substrate (3) first time, and the temperature being cooled to conductive material (5) to harden silicon substrate (3) subsequently,
C2) conductive material (5) is applied on first insulating barrier (4) of the second side (II) of silicon substrate (3), and
D2) silicon substrate (3) second time is heated to the temperature of conductive material (5) melting, and the temperature being cooled to conductive material (5) to harden silicon substrate (3) subsequently.
9. according to the method one of claim 1 to 2 Suo Shu, it is characterized in that, at method step c) and/or d) after also comprise method step
E1) at least one second insulating barrier (8) is applied by printing process.
10. according to the method one of claim 1 to 2 Suo Shu, it is characterized in that, described silicon substrate (3) is constructed by polysilicon and/or the silicon of low-purity and/or the silicon of recovery.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102009047592.3 | 2009-12-07 | ||
| DE102009047592.3A DE102009047592B4 (en) | 2009-12-07 | 2009-12-07 | Process for producing a silicon intermediate carrier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102086020A CN102086020A (en) | 2011-06-08 |
| CN102086020B true CN102086020B (en) | 2016-01-27 |
Family
ID=43971985
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010581224.8A Expired - Fee Related CN102086020B (en) | 2009-12-07 | 2010-12-06 | For the manufacture of the method for silicon sub-carrier |
Country Status (3)
| Country | Link |
|---|---|
| CN (1) | CN102086020B (en) |
| DE (1) | DE102009047592B4 (en) |
| TW (1) | TWI564239B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9076751B2 (en) * | 2011-08-30 | 2015-07-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices with self-heating structures, methods of manufacture thereof, and testing methods |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1571620A (en) * | 2003-07-14 | 2005-01-26 | 银河光电股份有限公司 | Structure of substrate, structure of insulating layer of substrate, and manufacturing method thereof |
| CA2383740C (en) * | 1999-09-06 | 2005-04-05 | Microtronic A/S | Silicon-based sensor system |
| CN1625805A (en) * | 2002-02-06 | 2005-06-08 | 揖斐电株式会社 | Board for mounting semiconductor chip and manufacturing method and semiconductor module |
| CN1933696A (en) * | 2005-07-22 | 2007-03-21 | 索尼株式会社 | Multilayer wiring board and fabricating method of the same |
| CN101494260A (en) * | 2008-01-23 | 2009-07-29 | 晶元光电股份有限公司 | LED element |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0272695A (en) * | 1988-09-07 | 1990-03-12 | Toshiba Lighting & Technol Corp | Hybrid integrated circuit |
| US6522762B1 (en) | 1999-09-07 | 2003-02-18 | Microtronic A/S | Silicon-based sensor system |
| KR100487224B1 (en) * | 2002-12-18 | 2005-05-03 | 삼성전자주식회사 | Vertical cavity surface emitting laser and method for fabricating the same |
| US7262622B2 (en) | 2005-03-24 | 2007-08-28 | Memsic, Inc. | Wafer-level package for integrated circuits |
| US20070232046A1 (en) * | 2006-03-31 | 2007-10-04 | Koji Miyata | Damascene interconnection having porous low K layer with improved mechanical properties |
| TWI372478B (en) * | 2008-01-08 | 2012-09-11 | Epistar Corp | Light-emitting device |
| DE102009027321A1 (en) * | 2009-06-30 | 2011-01-05 | Robert Bosch Gmbh | Method for producing electrical interlayer connection in substrate of micro-component or sensor, involves opening mask layer over substrate area provided for electrical interlayer connection, where mask layer is applied on substrate |
-
2009
- 2009-12-07 DE DE102009047592.3A patent/DE102009047592B4/en not_active Expired - Fee Related
-
2010
- 2010-12-06 CN CN201010581224.8A patent/CN102086020B/en not_active Expired - Fee Related
- 2010-12-06 TW TW099142337A patent/TWI564239B/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA2383740C (en) * | 1999-09-06 | 2005-04-05 | Microtronic A/S | Silicon-based sensor system |
| CN1625805A (en) * | 2002-02-06 | 2005-06-08 | 揖斐电株式会社 | Board for mounting semiconductor chip and manufacturing method and semiconductor module |
| CN1571620A (en) * | 2003-07-14 | 2005-01-26 | 银河光电股份有限公司 | Structure of substrate, structure of insulating layer of substrate, and manufacturing method thereof |
| CN1933696A (en) * | 2005-07-22 | 2007-03-21 | 索尼株式会社 | Multilayer wiring board and fabricating method of the same |
| CN101494260A (en) * | 2008-01-23 | 2009-07-29 | 晶元光电股份有限公司 | LED element |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201130729A (en) | 2011-09-16 |
| DE102009047592B4 (en) | 2019-06-19 |
| TWI564239B (en) | 2017-01-01 |
| CN102086020A (en) | 2011-06-08 |
| DE102009047592A1 (en) | 2011-06-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102164848B (en) | Micromechanical component and method for the production thereof | |
| KR100907514B1 (en) | Sensor device, sensor system and method of manufacturing the same | |
| CN101346815B (en) | Microelectronic machine and method for manufacturing same | |
| KR101423749B1 (en) | Formation of through-wafer electrical interconnections and other structures using a thin dielectric membraine | |
| US20160084865A1 (en) | Integrated rotation rate and acceleration sensor and method for manufacturing an integrated rotation rate and acceleration sensor | |
| CN109553065A (en) | The packaging method of MEMS devices and MEMS | |
| JP4539155B2 (en) | Manufacturing method of sensor system | |
| CN102099281B (en) | Process for manufacturing a component, process for manufacturing a component arrangement, component and component arrangement | |
| JP4544140B2 (en) | MEMS element | |
| JP2009016717A (en) | Semiconductor device and method of manufacturing the same | |
| JP2007222956A (en) | Mems device and manufacturing method of mems device | |
| JP2008256495A (en) | Sensor device | |
| KR20070102265A (en) | Micro-electro mechanical system device using silicon on insulator wafer and method of manufacturing the same | |
| JP2000133616A (en) | Integrated device and manufacture thereof | |
| US20110169169A1 (en) | Method for providing and connecting two contact areas of a semiconductor component or a substrate, and a substrate having two such connected contact areas | |
| CN102086020B (en) | For the manufacture of the method for silicon sub-carrier | |
| JP2010287887A (en) | Method for producing power semiconductor module and the power semiconductor module with connection device | |
| US9114975B2 (en) | Micromechanical component and method for producing a micromechanical component having a thin-layer cap | |
| JP2006201158A (en) | Sensor | |
| JP4857718B2 (en) | Micromachine mixed electronic circuit device and method for manufacturing micromachine mixed electronic circuit device | |
| JP2006224219A (en) | Manufacturing method for mems element | |
| JP2004202604A (en) | Package structure and manufacturing method | |
| JP2007307705A (en) | Micro-mechanical element and manufacturing method of micro-mechanical element | |
| CN104843631A (en) | Layer structure for a micromechanical component | |
| US20220348453A1 (en) | Sensor system with a microelectromechanical sensor element and method for producing a sensor system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160127 |