CN102064673B - Suppression circuit for neutrality point excursion of direct voltage of multilevel converter and suppression method - Google Patents
Suppression circuit for neutrality point excursion of direct voltage of multilevel converter and suppression method Download PDFInfo
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- CN102064673B CN102064673B CN 201010539280 CN201010539280A CN102064673B CN 102064673 B CN102064673 B CN 102064673B CN 201010539280 CN201010539280 CN 201010539280 CN 201010539280 A CN201010539280 A CN 201010539280A CN 102064673 B CN102064673 B CN 102064673B
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Abstract
The invention relates to a suppression circuit for neutrality point excursion of direct voltage of a multilevel converter and a suppression method, which belong to the technical field of converter control. The circuit comprises at least four resistance-capacitance parallel units, each being connected in series between both ends of a direct current power supply. One ends of controllable switchers are connected between adjacent resistance-capacitance parallel units while the other ends of the controllable switchers are connected in parallel and derive the voltage output end as load neutrality point of multilevel converter. By adopting the invention, however the power supply voltage fluctuates, excursion of the neutrality point potential can be effectively suppressed only by switching the controllable switcher appropriately so that the potential of the output voltage is always maintained at neutrality point potential, thereby avoiding damage of the loading system caused by potential excursion of neutrality point.
Description
Technical field
The present invention relates to a kind of direct voltage neutral point excursion and suppress circuit, especially a kind of many level current transformers direct voltage neutral point excursion suppresses circuit, provides simultaneously the method that suppresses neutral point excursion by this circuit, belongs to current transformer control technology field.
Background technology
Understand according to the applicant, in the process of dc voltage power supply output, spread of voltage can cause that many level current transformers direct voltage neutral point is offset, if according to the prior art connecting circuit, will make the neutral point current potential that the variation that can not expect occurs, cause electric current extremely unstable, even cause load impaired.
Fig. 1 is the DC power supply direct voltage circuit of neutral point of prior art, connects the tandem compound of two identical capacitance-resistance unit in parallel between input direct voltage Uo and the load system, and wherein capacitance-resistance unit in parallel is connected in parallel by an electric capacity and a resistance.When connecting DC power supply, the current potential of neutral point is half of DC power supply voltage, if supply power voltage is unstable, the neutral point current potential also changes thereupon, can't regulate and control, and will cause load system impaired when serious.
Summary of the invention
The objective of the invention is: for the problem that above-mentioned prior art exists, propose a kind of many level current transformers direct voltage neutral point excursion that can pass through the regulation and control neutral point voltage and suppress circuit.
In order to reach above purpose, many level current transformers direct voltage neutral point excursion of the present invention suppresses circuit and contains at least four capacitance-resistances unit in parallel, described each capacitance-resistance unit in parallel is connected between the DC power supply two ends mutually, connect respectively an end of gate-controlled switch device between the adjacent capacitance-resistance unit in parallel, the other end of each gate-controlled switch device is connected in parallel, and draws the voltage output end as many level current transformers load neutral point.
Further, gate-controlled switch device of the present invention is selected from IGBT, IGCT, GTO, MOSFET, the SET bidirectional switch device of bidirectional thyristor or inverse parallel structure.
The actual potential of the break-make selective basis output voltage of gate-controlled switch of the present invention and predeterminated voltage upper limit threshold and the threshold value comparative result that rolls off the production line are determined.After being appreciated that employing the present invention, no matter how supply voltage fluctuates, as long as by taking the circumstances into consideration to switch the gate-controlled switch device, skew that just can establishment neutral point current potential makes the current potential of output voltage remain at the neutral point current potential, thereby it is impaired because of the neutral point potential shift to exempt load system.This shows, the present invention has rationally solved the direct voltage neutral point excursion and can't obtain accurate neutral point reference potential problem, and can determine the quantity of capacitance-resistance unit in parallel according to the control precision needs, thus not only economy but also practicality.
Description of drawings
Fig. 1 is the direct voltage circuit of neutral point of prior art DC power supply.
Fig. 2 (1) is the many level current transformers direct voltage neutral point excursion inhibition circuit diagram as the even number capacitance-resistance unit in parallel of the embodiment of the invention one.
Fig. 2 (2) to (7) is working mechanism's schematic diagram of the embodiment of the invention one.
Fig. 3 (1) is the many level current transformers direct voltage neutral point excursion inhibition circuit diagram as the odd number capacitance-resistance unit in parallel of the embodiment of the invention two.
Fig. 3 (2) to (4) is working mechanism's schematic diagram of the embodiment of the invention two.
Embodiment
Embodiment one
The direct voltage neutral point excursion of the present embodiment suppresses circuit shown in Fig. 2 (1), contains four above even number capacitance-resistance unit in parallel.Shown in Fig. 2 (2), capacitance-resistance unit in parallel number is that (n is natural number to even number 2n, n is not equal to 1), when the controllable switch S n in the connection arranged in sequence gate-controlled switch, if the output voltage current potential U0 of voltage output end is less than predeterminated voltage value 1 (U
PN/ 2-U
PN/ 2n) time, shown in Fig. 2 (3), disconnect this gate-controlled switch, be communicated with next controllable switch S (n+1).If output voltage current potential U0 is greater than predeterminated voltage value 2 (U
PN/ 2+U
PN/ 2n) time, shown in Fig. 2 (4), disconnect this gate-controlled switch, be communicated with a controllable switch S (n-1) on it.With the one by one diverter switch debugging of this rule, namely can reach the inhibition skew purpose that the output voltage current potential is the neutral point current potential by enough accuracy.
Shown in Fig. 2 (5), capacitance-resistance unit in parallel number is even number 2n (n is natural number, and N is not equal to 1), when being communicated with controllable switch S (i) (i is the natural number of 2～2n-1), if output voltage current potential U0 is less than predeterminated voltage value 1 (U
PN/ 2-U
PN/ 2n) time, shown in Fig. 2 (6), disconnect this gate-controlled switch, be communicated with controllable switch S (i+1) (i is the natural number of 2～2n-1).If output voltage current potential U
0Greater than predeterminated voltage value 2 (U
PN/ 2+U
PN/ 2n) time, shown in Fig. 2 (7), disconnect this gate-controlled switch, be communicated with controllable switch S (i-1) (i is the natural number of 2～2n-1).With the continuous diverter switch of this rule, until till the neutral point current potential that the output voltage current potential is error to be allowed.
Embodiment two
The direct voltage neutral point excursion of the present embodiment suppresses circuit shown in Fig. 3 (1), different from embodiment one is, contain four above odd number capacitance-resistance unit in parallel, each capacitance-resistance unit in parallel is formed in parallel by capacitance resistance ware C1...C (2n+1) and the R1...R (2n+1) of parallel connection respectively, wherein the resistance of each resistance equates, the appearance value of each electric capacity equates.Connect mutually in each capacitance-resistance unit in parallel, between direct voltage U
PNAnd between the load of many level current transformers, connect respectively the end of one of gate-controlled switch device S1...S (2n) between the adjacent capacitance-resistance unit in parallel, the other end of each gate-controlled switch device is connected in parallel, and draws the voltage output end U as many level current transformers load neutral point
0
Shown in Fig. 3 (2), capacitance-resistance unit in parallel number is that (n is natural number to odd number 2n+1, n is not equal to 1), when the controllable switch S (i) (i is the natural number of 2～2n-1) in the connection arranged in sequence gate-controlled switch, if output voltage current potential U
0Less than default neutral point voltage current potential lower threshold, the present embodiment is 1[U
PN/ 2-U
PN/ (2n-1)] time, then shown in Fig. 3 (3), disconnect this gate-controlled switch, a controllable switch S (i+1) (i is the natural number of 2～2n-1) after being communicated with.If the output voltage current potential U0 of voltage output end is greater than default neutral point voltage current potential upper limit threshold, the present embodiment is 2[U
PN/ 2+U
PN/ (2n-1)], then shown in Fig. 3 (4), disconnect this gate-controlled switch, be communicated with last controllable switch S (i-1) (i is the natural number of 2～2n-1).With the one by one diverter switch debugging of this rule, until reach the output voltage current potential of described voltage output end the most approaching with desirable neutral point current potential till, the inhibition that namely can enough accuracy reach the output voltage current potential and be the neutral point current potential is offset purpose.
Be summed up, (referring to Fig. 1) compares with prior art, and above-described embodiment has following remarkable advantage:
1. directly adjust neutral point voltage, time of delay is short, and it is fast that variation suppresses speed;
2. reduce the net side because the neutral point voltage skew causes the probability of overcurrent resonance phenomena;
3. be independent of the program control of microcontroller, alleviated the burden of microcontroller, and strengthened reliability.
In addition to the implementation, the present invention can also have other execution modes.For example, the appearance value of the resistance of each resistance of arranged in sequence and each electric capacity increases progressively by predetermined difference value respectively, can when mains fluctuations are larger, reach as early as possible the purpose that suppresses neutral point excursion like this.All employings are equal to the technical scheme of replacement or equivalent transformation formation, all drop on the protection range of requirement of the present invention.
Claims (7)
1. the neutral point excursion of level current transformer direct voltage more than a kind suppresses circuit, it is characterized in that: contain at least four capacitance-resistances unit in parallel, described each capacitance-resistance unit in parallel is connected between the DC power supply two ends mutually, connect respectively an end of gate-controlled switch device between the adjacent capacitance-resistance unit in parallel, the other end of each gate-controlled switch device is connected in parallel, and draws the voltage output end as many level current transformers load neutral point; When i gate-controlled switch device in the connection arranged in sequence gate-controlled switch device, i is the natural number of 2～2n-1, the output voltage current potential of voltage output end then disconnects i gate-controlled switch device less than default neutral point voltage current potential lower threshold as described, is communicated with its next gate-controlled switch device; The output voltage current potential of voltage output end then disconnects i gate-controlled switch device greater than default neutral point voltage current potential upper limit threshold as described, is communicated with a gate-controlled switch device on it; Switch one by one gate-controlled switch device debugging with this rule, until reach the output voltage current potential of described voltage output end and desirable neutral point current potential the most approaching till.
2. according to claim 1 described many level current transformers direct voltage neutral point excursion suppresses circuit, and it is characterized in that: described neutral point voltage current potential lower threshold is pressed: 1[U
PN/ 2-U
PN/ k] determine; Described neutral point voltage current potential upper limit threshold is pressed: 2[U
PN/ 2+ U
PN/ k] determine; U in the formula
PNBe the dc voltage value, k is the capacitance-resistance of series connection unit number in parallel.
3. many level current transformers direct voltage neutral point excursion according to claim 2 suppresses circuit, it is characterized in that: consists of the resistance of resistance of described each capacitance-resistance parallel connection unit and the appearance value of electric capacity and increase progressively according to the order of sequence respectively.
4. many level current transformers direct voltage neutral point excursion according to claim 2 suppresses circuit, it is characterized in that: the resistance that consists of described each capacitance-resistance unit in parallel equates, and the appearance value of electric capacity equates.
According to claim 3 or 4 described many level current transformers direct voltage neutral point excursions suppress circuit, it is characterized in that: one of IGBT, the IGCT that described gate-controlled switch device is bidirectional thyristor or inverse parallel structure, GTO, MOSFET, SET bidirectional switch device.
6. many level current transformers direct voltage neutral point excursion according to claim 4 suppresses circuit, it is characterized in that: described capacitance-resistance unit in parallel number is even number 2n, and n is natural number and greater than 1.
7. many level current transformers direct voltage neutral point excursion according to claim 4 suppresses circuit, it is characterized in that: described capacitance-resistance unit in parallel number is odd number 2n+1, and n is natural number and greater than 1.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010539280 CN102064673B (en) | 2010-11-11 | 2010-11-11 | Suppression circuit for neutrality point excursion of direct voltage of multilevel converter and suppression method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010539280 CN102064673B (en) | 2010-11-11 | 2010-11-11 | Suppression circuit for neutrality point excursion of direct voltage of multilevel converter and suppression method |
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| CN102064673A CN102064673A (en) | 2011-05-18 |
| CN102064673B true CN102064673B (en) | 2013-02-27 |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201345536Y (en) * | 2009-01-22 | 2009-11-11 | 广东省电力工业局试验研究所 | Transformer neutral point capacitance-resistance mixed type inhibition direct current device |
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Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201345536Y (en) * | 2009-01-22 | 2009-11-11 | 广东省电力工业局试验研究所 | Transformer neutral point capacitance-resistance mixed type inhibition direct current device |
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