CN102064154A - 集成电路结构 - Google Patents

集成电路结构 Download PDF

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Publication number
CN102064154A
CN102064154A CN2010105355030A CN201010535503A CN102064154A CN 102064154 A CN102064154 A CN 102064154A CN 2010105355030 A CN2010105355030 A CN 2010105355030A CN 201010535503 A CN201010535503 A CN 201010535503A CN 102064154 A CN102064154 A CN 102064154A
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Prior art keywords
layer
copper
integrated circuit
passivation
circuit structure
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CN102064154B (zh
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黄见翎
吴逸文
刘重希
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种集成电路结构，包括：一半导体基板；一钝化层，位于该半导体基板上；一高分子层，位于该钝化层上；一内连线线路，形成于该钝化层与该高分子层之间；以及一保护层，形成于该内连线线路与该高分子层之间；其中该保护层为含铜材料层，且包括III族元素、IV族元素、或V族元素中至少一个。形成于钝化层上的铜内连线被含铜材料层保护。上述含铜材料层含有III族元素、IV族元素、V族元素、或上述的组合。本发明可避免后钝化内连线氧化而在后续凸块工艺不需额外蚀刻步骤。

Description

集成电路结构
技术领域
本发明涉及一种集成电路元件的制造工艺，特别是涉及一种具有后钝化内连线的集成电路元件。
背景技术
现有的集成电路是由横向排列的百万个有源元件如晶体管及电容所组成。这些元件在初步制造工艺中彼此绝缘，但在后段制造工艺中将以内连线连接元件以形成功能电路。一般的内连线结构包含横向内连线如金属线路，与垂直内连线如通孔与接点。现有的集成电路其性能与密度的上限取决于内连线。集成电路可含有钝化层，以保护其下的层状结构不受湿气、污染物、或其他劣化或损伤集成电路的状况影响。目前广泛采用的晶片等级的裸片尺寸封装(WLCSP)具有成本低廉与工艺简单等优点。在一般的晶片等级的裸片尺寸封装中，在金属化层上形成内连线结构后，接着形成凸块下冶金(UBM)层，以及固定焊球。在后钝化内连线(PPI)工艺中，连接至集成电路的接点区的接点焊盘与其他导体，是形成于钝化层的顶部上。后钝化内连线可将集成电路的连线重新布线，以接触封装结构。一般来说，氮化硅或聚酰亚胺可避免铜组成的后钝化内连线氧化，但需额外的图案化步骤(比如蚀刻工艺)以利后续凸块工艺。由于聚酰亚胺涂布工艺中无法进行去氧化步骤，因此必需考虑铜电镀工艺到聚酰亚胺涂布工艺之间的留置时间(Q-time)。
发明内容
为克服现有技术的缺陷，本发明一实施例提供一种集成电路结构，包括半导体基板；钝化层，位于半导体基板上；高分子层，位于钝化层上；内连线线路，形成于钝化层与高分子层之间；以及保护层，形成于内连线线路与高分子层之间；其中保护层为含铜材料层，且包括III族元素、IV族元素、或V族元素中至少一个。
本发明另一实施例提供一种集成电路结构，包括半导体基板，包括接触区；钝化层，位于半导体基板上，且钝化层具有开口露出部分接触区；铜线路位于部分钝化层上，且填入开口以电性连接至接触区；以及保护层，形成于铜连线的表面上；其中保护层为含铜材料层，且包括III族元素、IV族元素、或V族元素中至少一个。
本发明可避免后钝化内连线氧化而在后续凸块工艺不需额外蚀刻步骤。
附图说明
图1A至图1C是本发明一实施例中，PPI工艺的剖视图；
图1D至图1H是本发明一实施例中，在PPI线路上进行凸块工艺的剖视图；
图2A至图2C是本发明一实施例中，在PPI线路上进行凸块工艺的剖视图；以及
图3A至图3C是本发明一实施例中，在PPI线路上进行凸块工艺的剖视图。
【主要附图标记说明】
10～基板；
12～接点区；
14～钝化层；
15、27、32～开口；
16～黏着层；
18～晶种层；
20～层状结构；
22～后钝化内连线线路；
24、36～保护层；
26～高分子层；
28～凸块下冶金层；
28a～保留的凸块下冶金层；
30～掩模层；
34～铜层；
34P～铜柱；
35、35a、35b～凸块结构；
38～盖层；
40～焊料层。
具体实施方式
在下述说明中，多种特例会先置前以利本领域普通技术人员对本发明有全面性的了解。然而本领域普通技术人员应理解，实际上的操作并不需完全符合这些特例。在某些例子中，不会详细地描述本领域熟知的结构与工艺，以避免不必要地模糊公开内容。
在下述说明中，“一实施例”指的是特定特征、结构、或至少一实施例中包含的实施例所连结的结构。因此，不同段落中的“一实施例”指的不一定是同一实施例。此外，一或多个实施例中的特定特征、结构、或特点可由任何合适形式组合。可以理解的是，下述图示并非依比例示出，仅用以方便说明而已。
图1A至图1C是本发明一实施例中，PPI工艺的剖视图。
如图1A所示的实施例中，用以形成后钝化内连线的基板10可为半导体集成电路产业常用的半导体基板，在半导体基板之上或之中可形成集成电路。半导体基板的定义可为任何半导体材料组成，包含但不限于基体硅、半导体晶片、绝缘层上硅(SOI)基板、或硅锗基板。半导体材料也可含有III、IV、或V族元素。这里所指的集成电路为具有多个独立电路单元的电子电路，而电路单元可为晶体管、二极管、电阻、电容、电感、及其他有源或无源半导体元件。
基板10可进一步具有层间介电层与金属化结构于集成电路上。位于金属化结构中的层间介电层可为低介电常数的介电材料、未掺杂的硅酸盐玻璃(USG)、氮化硅、氮氧化硅、或其他一般常用材料。低介电常数的介电材料的介电常数(k值)可小于约3.9，或小于约2.8。金属化结构中的金属线路的组成可为铜或铜合金。本领域普通技术人员应理解上述金属化层的详细制造工艺。最上层的金属化层为接点区12，是位于最上层的层间介电层上。接点区12为导电线路的一部分，且露出平坦化工艺处理过的表面。若必要的话，上述平坦化工艺可为化学机械研磨(CMP)工艺。适用于接点区12的材料可包含但不限定于铜、铝、铜合金、或其他现有导电材料。在一实施例中，接点区12为接合焊盘区，可用于连接不同芯片中的集成电路至外部结构的接合工艺。
如图1A所示，形成钝化层14于基板10上，并图案化钝化层14以形成开口15，露出部分的接点区12。在一实施例中，钝化层14的组成为非有机材料如USG、氮化硅、氮氧化硅、氧化硅、或上述的组合。在另一实施例中，钝化层14的组成为高分子层如环氧树脂、聚酰亚胺、苯并环丁烯(BCB)、聚苯并恶唑(PBO)、类似物、或其他较软，通常为有机物的介电材料。
如图1B所示，在钝化层14上形成黏着层16与晶种层18，以衬垫开口15的侧壁与底部。黏着层16又称胶层，是毯覆性地覆盖钝化层14及开口15的侧壁与底部。黏着层16可为常用阻挡材料如钛、氮化钛、钽、氮化钽、或上述的组合。黏着层16的形成方法可为物理气相沉积法(PVD)、溅镀法、或类似方法。黏着层16可帮助改善钝化层14与后续形成其上的铜线路之间的黏着力。晶种层18是毯覆性地形成于黏着层16上。晶种层18的组成可为铜或铜合金，其他金属如银、金、铝，或上述的组合。晶种层18可为铝或铝合金。在一实施例中，晶种层18的形成方法为溅镀。在其他实施例中，晶种层18的形成方法可为其他常用方法如PVD或无电电镀法。为了简洁起见，在后续图示中将以层状结构20表示上述的晶种层18与黏着层16。
此外，后钝化内连线(PPI)线路22形成于层状结构20上以填入开口15。以掩模搭配光刻工艺，将导电材料填入掩模开口，再移除掩模与露出的层状结构20。形成于层状结构20上与填入开口15的导电材料可作为后钝化内连线线路22。后钝化内连线线路22的组成可含有但不限于铜、铝、铜合金、或其他现有的导电材料。后钝化内连线线路22可进一步具有含镍层(未图示)形成于含铜层的顶部上。后钝化内连线的形成方法可为电镀、无电电镀、溅镀、化学气相沉积法(CVD)、或类似方法。后钝化内连线线路22可将接触区12连线至凸块结构。后钝化内连线线路22可作为电源线、再分布线路(RDL)、电感、电容、或任何无源构件。后钝化内连线线路22的厚度可小于约30μm，比如介于约2μm至约25μm之间。
接着移除露出的部分层状结构20(即黏着层16与晶种层18)。移除步骤可为湿蚀刻或干蚀刻。在一实施例中，移除步骤采用氨为主的酸类进行等向湿蚀刻，此为短时间的闪蚀法。
接着如图1C所示，在后钝化内连线线路22上形成保护层24。保护层24为含铜材料层，并含有周期表中的III、IV、及V族元素或上述的任何组合。在一实施例中，含铜材料层可含有但不限于硼、锗、硅、碳、氮、磷、或上述的组合。在某些实施例中，含铜材料层为氮化铜锗(CuGeN)层、铜锗(CuGe)层、硅化铜(CuSi)层、硅氮化铜(CuSiN)层、硅氮化铜锗层(CuSiGeN)、氮化铜(CuN)层、磷化铜(CuP)层、碳化铜(CuC)层、硼化铜(CuB)层、或上述的组合。含铜材料层的形成方法可为选择性CVD，其制造工艺气体含硼、锗、硅、碳、氮、磷、或上述的组合，比如硼烷、甲烷、硅烷、锗烷、氨、或磷化氢。以形成氮化铜锗层为例，在去氧处理步骤(氨处理)后接着进行锗烷的CVD工艺。
在一实施例中，保护层24用以避免后钝化内连线线路22在后续工艺中氧化。如此一来，保护层24也可称为抗氧化层或阻止氧化层。与后钝化内连线线路上的现有氮化硅层相较，保护层24比较能减少后钝化内连线的应力。此外在后续的凸块工艺中，保护层24可保留于铜组成的后钝化内连线线路上，而不需以额外蚀刻步骤移除保护层24。另一方面，在铜组成的后钝化内连线线路、钝化层、以及后续的聚酰亚胺的工艺间可选择性地形成保护层24，且不会大幅增加结构的电阻(Rs)。
图1D至图1G是本发明一实施例中，在后钝化内连线线路上进行凸块工艺的剖视图。
如图1D所示，在钝化层14上形成高分子层26以覆盖保护层24，其形成方法包含涂布、硬化、去渣、及类似工艺。接着进行光刻工艺与蚀刻工艺如干蚀刻及/或湿蚀刻以图案化高分子层26，形成贯穿高分子层26的开口27以露出部分下方的保护层24。高分子层26如名所示，其组成为高分子如环氧树脂、聚酰亚胺、BCB、PBO、类似物、或其他较软，通常为有机物的介电材料。在一实施例中，高分子层26为聚酰亚胺层。高分子层26为软性材料，因此可减少基板上的固有应力。另一方面，高分子层26的厚度可轻易达到数十个微米。
如图1E所示，含有阻挡层与晶种层的凸块下冶金(UBM)层28形成于上述结构上。凸块下冶金层28形成于高分子层26与露出的部分保护层24上，并衬垫开口27的侧壁与底部。扩散阻挡层也称为胶层，是形成以覆盖开口27的侧壁与底部。扩散阻挡层的组成可为氮化钽，也可为其他材料如氮化钛、钽、钛、或类似物。扩散阻挡层的形成方法可为PVD或溅镀法。晶种层可为形成于扩散阻挡层上的铜晶种层。晶种层的组成可为铜合金，除了铜以外还含有银、铬、镍、锡、金、或上述的组合。在一实施例中，凸块下冶金层28含有钛组成的扩散阻挡层，与铜组成的晶种层。接着形成掩模层30于凸块下冶金层28上，再图案化掩模层30以形成开口32露出部分的凸块下冶金层28以利凸块工艺。在一实施例中，开口32位于开口27上。在另一实施例中，开口32的直径大于或等于开口27的直径。掩模层30可为干膜或光致抗蚀剂膜。
如图1F所示，以具有焊料湿润性的导电材料填入部分或全部的开口32。在一实施例中，在凸块下冶金层28上形成铜层34以填入部分的开口32。在说明书中的所有段落中，“铜层”此用语可延伸至实质上纯铜元素层、含有无可避免的杂质的铜层、以及铜合金层，其次要元素可为钽、铟、锡、锌、镁、铬、钛、锗、锶、铂、锰、铝、或锆。铜层34的形成方法可为溅镀、印刷、电镀、无电电镀、或常用的CVD。举例来说，电化学电镀(ECP)法可用以形成铜层34。在一实施例中，铜层34的厚度大于40μm。在另一实施例中，铜层34的厚度介于约40μm至约50μm之间。在其他实施例中，铜层34的厚度介于约40μm至约70μm之间。不过铜层34的厚度并不限于上述范围，可大于或小于上述范围。
接着如图1G所示，移除掩模层30。当掩模层30为干膜时，其移除方法可采用碱性溶液。若掩模层30为光致抗蚀剂时，其移除方法可采用丙酮、N-甲基咯烷酮(NMP)、二甲基亚砜(DMSO)、胺基乙氧基乙醇、或类似物。接着蚀刻露出的部分凸块下冶金层28，直到露出铜层34以外与凸块下冶金层28下方的高分子层26。在一实施例中，移除凸块下冶金层28的步骤为干蚀刻或湿蚀刻。举例来说，可采用氨为主的酸类进行等向蚀刻。由于蚀刻时间短，此蚀刻也称为闪蚀。由于铜层34自高分子层26凸出，因此称之为铜柱34P。铜柱34P与其下方的凸块下冶金层28a组成凸块结构35。接着切割基板10，并以固定于封装基板或其他裸片上的焊盘上焊球或铜柱，将切割后的基板10封装至封装基板或另一裸片上。
为了保护铜柱34P的表面不致氧化，可视情况形成另一保护层36于铜柱34P上，如图1H所示。保护层36可选择性地形成于凸块结构35的侧壁表面及/或上表面上。在一实施例中，保护层36为含锡层。举例来说，先将凸块结构35浸入含锡的无电电镀溶液中。通过起始后就会自动催化的化学还原法，可将锡沉积于凸块结构35上。溶液中的化学剂会还原无电电镀溶液中的锡离子，使其沉积于凸块表面上。由于电镀反应只发生在凸块结构35的表面，高分子层26的表面上将不具有电镀铜。保护层36可包覆凸块结构35以避免其氧化，并改善后续形成的底填材料与凸块结构35之间的黏着力。
图2A至图2C是本发明一实施例中，在PPI线路上进行凸块工艺的剖视图。在下述说明中，与图1A至图1H重叠的部分将不赘述。
如图2A所示，在形成铜层34后，在掩模层30的开口32中沉积盖层38于铜层34上。盖层38可为镍、锡、锡铅、金、银、钯、铟、镍铂金、镍金、其他类似材料、或上述的合金。在一实施例中，盖层38为无铅预焊层如锡金。在另一实施例中，盖层38为焊料如下述金属的合金：锡、铅、银、铜、镍、铋、或上述的组合。在其他实施例中，盖层38为镍层、金层、或镍金层。如图2B所示，在移除掩模层30与部分凸块下冶金层28后，保留的铜层34(即铜柱34P)凸出高分子层26。保留的凸块下冶金层28a、铜柱34P、与盖层38形成凸块结构35a。盖层38作为阻挡层，可避免铜柱34P中的铜扩散。避免铜扩散可增加元件可信度及封装的接合强度。在图2C中，可选择性地形成另一保护层36于凸块结构35a的侧壁表面上及/或上表面上。在一实施例中，保护层36为含锡层。
图3A至图3C是本发明一实施例中，在PPI线路上进行凸块工艺的剖视图。在下述说明中，与图1A至图1H重叠的部分将不赘述。
如图3A所示，在形成铜层34后，在掩模层30的开口32中沉积盖层38与焊料层40于铜层34上。盖层38可为镍、金、银、银、钯、铟、镍铂金、镍金、其他类似材料、或上述的合金。在一实施例中，焊料层40为无铅预焊层如锡金，或焊料如下述金属的合金：锡、铅、银、铜、镍、铋、或上述的组合。如图3B所示，在移除掩模层30及部分凸块下冶金层28后，保留的铜层34(即铜柱34P)凸出高分子层26。保留的凸块下冶金层28a、铜柱34P、盖层38、与焊料层40形成凸块结构35b。接着可进行焊料再流动工艺使焊料层40转变为焊球。在图3C中，可选择性地形成另一保护层36于凸块结构35b的侧壁表面上及/或上表面上。在一实施例中，保护层36为含锡层。
虽然本发明已以多个较佳实施例公开如上，然其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰，因此本发明的保护范围当视所附的权利要求所界定的范围为准。

Claims (10)

1.一种集成电路结构，包括：
一半导体基板；
一钝化层，位于该半导体基板上；
一高分子层，位于该钝化层上；
一内连线线路，形成于该钝化层与该高分子层之间；以及
一保护层，形成于该内连线线路与该高分子层之间；
其中该保护层为含铜材料层，且包括III族元素、IV族元素、或V族元素中至少一个。
2.根据权利要求1所述的集成电路结构，其中该保护层为氮化铜锗层。
3.根据权利要求1所述的集成电路结构，其中该钝化层具有一开口露出部分的该半导体基板，且该内连线线路是形成于部分该钝化层上并填入该钝化层的开口。
4.根据权利要求3所述的集成电路结构，还包括一钛层位于该内连线线路下，且该钛层衬垫该钝化层的开口的底部及侧壁；以及一铜层形成于该内连线线路与该钛层之间。
5.根据权利要求1所述的集成电路结构，其中该高分子层具有一开口露出部分该保护层，以及一凸块结构位于该高分子层上，且该凸块结构经由该高分子的该开口电性连接至该保护层。
6.根据权利要求5所述的集成电路结构，其中该凸块结构包括一铜柱，与一盖层位于该铜柱上，其中该盖层包括含镍层、含锡层、或上述的组合中至少一个。
7.根据权利要求5所述的集成电路结构，其中该凸块结构包括一含锡层位于该铜柱的侧壁上。
8.一种集成电路结构，包括：
一半导体基板，包括一接触区；
一钝化层，位于该半导体基板上，且该钝化层具有一开口露出部分该接触区；
一铜线路位于部分该钝化层上，且填入该开口以电性连接至该接触区；以及
一保护层，形成于该铜连线的表面上；
其中该保护层为含铜材料层，且包括III族元素、IV族元素、或V族元素中至少一个。
9.根据权利要求8所述的集成电路结构，其中该保护层是氮化铜锗层、铜锗层、硅化铜层、硅氮化铜层、硅氮化铜锗层、氮化铜层、磷化铜层、碳化铜层、硼化铜层、或上述的组合中至少一个。
10.根据权利要求8所述的集成电路结构，还包括一铜柱位于该保护层上。
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