CN108666359A - A kind of device architecture and implementation method improving GaN enhancement type channel mobilities using novel barrier layer - Google Patents

A kind of device architecture and implementation method improving GaN enhancement type channel mobilities using novel barrier layer Download PDF

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CN108666359A
CN108666359A CN201710196720.3A CN201710196720A CN108666359A CN 108666359 A CN108666359 A CN 108666359A CN 201710196720 A CN201710196720 A CN 201710196720A CN 108666359 A CN108666359 A CN 108666359A
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gan
algan
aln
barrier layer
type channel
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王茂俊
沈波
陶明
刘少飞
郝龙
郝一龙
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Peking University
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

The invention discloses a kind of device architecture and preparation method thereof improving GaN enhancement type channel mobilities using novel barrier layer, the structure includes substrate, GaN or AlN buffer layers, GaN channel layers, AlGaN layer insert layer, GaN insert layers, AlN insert layers, AlGaN insert layers, mask medium layer, insulation gate dielectric layer and source and drain Ohmic contact and grid metal.AlGaN/AlN/GaN/AlGaN/GaN heterojunction materials are epitaxially grown on the substrate, and form source electrode and drain electrode on this structure.The present invention is inserted into one group of AlN/GaN in AlGaN potential barrier, the GaN layer of insertion is as thermal oxide, the stop-layer of wet etching, side remains complete AlGaN/GaN heterojunction structures under the gate, avoid the damage of corrosion and dielectric layer deposited to raceway groove, reduce conducting resistance, the thickness that barrier layer below grid can be accurately controlled simultaneously, can improve the accuracy, controllability, consistency of technique, be conducive to industrialization and prepare on a large scale.

Description

A kind of device architecture improving GaN enhancement type channel mobilities using novel barrier layer And implementation method
Technical field
The invention belongs to microelectronics technologies, are related to the making of GaN power electronic devices
Background technology
In recent years, gallium nitride material causes extensive pass since energy gap is big, breakdown potential field strength, saturated velocity are big Note.AlGaN/GaN hetero-junctions strong polarity effects form the two-dimensional electron gas of high concentration in high speed, high power and pressure-resistant electronic device Field plays important role.It is wide that the superior performance of GaN material makes it have in frequency microwave and field of power electronics Application prospect.
GaN device is mainly based on GaN hetero-junctions HEMT, in conventional AlGaN/GaN hetero-junctions, due to spontaneous polarization Effect and piezoelectric polarization effect, in heterojunction boundary, there are the two-dimensional electron gas of high concentration, i.e., conventional AlGaN/GaN HEMT Device shows as depletion device.But it the considerations of for security of system and terseness, is needed in the application of many actual circuits Want enhancement device.
The current more commonly used method to realize enhanced GaN MOS is grid removal technology and fluorine ion injection technique, grid Removal technology includes two kinds of dry etching and wet etching again.The wherein side of the grid removing method of dry etching and fluorine ion injection Method has prodigious damage to GaN MOS channel surfaces;And although the grid of wet etching remove technology without plasma damage, AlGaN potential barrier is all removed due to disposable, deposit gate dielectric layer is inevitable to the damage of raceway groove, obtained MOS raceway grooves Mobility be far below the mobility of heterojunction boundary, therefore the conducting resistance for the enhancement device prepared is big, output current Density is relatively low.
In order to improve GaN enhancement type channel electron mobilities, surface topography is needed to be improved, interface scattering is reduced.Solution at present Certainly this problem has following improvement plan:Make the damage to raceway groove as small as possible 1. adjusting technological parameter;2. from energy band engineering Angle using the back of the body barrier structure make channel electrons far from dielectric layer and the interfaces GaN, to reduce interface to channel electrons Scattering improves enhancement type channel electron mobility, and then promotes the saturation current of device, obtains high-performance, the GaN of high stable increases Strong type device.
Invention content
The present invention in order to preferably solve the problems, such as GaN enhancement type channel mobilities it is low this, utilize wet etching self-stopping technology The characteristics of, be inserted into one group of AlN/GaN in AlGaN potential barrier, the GaN layer of insertion as thermal oxide, the stop-layer of wet etching, Side remains complete AlGaN/GaN heterojunction structures under the gate, reduces conducting resistance, while can accurately control under grid The thickness of square barrier layer obtains the high GaN enhancement devices of superior performance, stability.
The technical thought of the present invention is as follows:In the traditional AlGaN/GaN enhancement devices structure for removing technology based on grid, grid Dielectric layer is in direct contact to form MOS raceway grooves with GaN layer.On the one hand, the distance of insulation gate dielectric layer and GaN channel layers is close, leads Channel electrons are caused to be acted on by the strong scattering from interface, mobility reduces;On the other hand, dielectric layer is deposited directly on GaN ditches It is inevitable to the damage of GaN raceway grooves on road.In on the basis of traditional enhanced AlGaN/GaN device structure, It is inserted into one group of AlN/GaN in AlGaN potential barrier, uses high-temperature thermal oxidation method so that oxidation is automatically stopped the GaN in insertion Layer, eliminates the damage to raceway groove in technical process, remains complete AlGaN/GaN hetero-junctions, gate dielectric layer and GaN raceway grooves It realizes separation, effectively inhibits the strong scattering at interface to act on, improve the mobility of enhancement type channel electronics.
According to above-mentioned technical thought the conducting of device is reduced in order to reduce the mobility of GaN enhancement device channel electrons Resistance, a kind of device architecture improving GaN enhancement type channel mobilities using novel barrier layer, the structure includes substrate, GaN Or it is AlN buffer layers, intrinsic GaN channel layers, intrinsic AlGaN insert layers, intrinsic GaN insert layers, intrinsic AlN insert layers, intrinsic AlGaN potential barrier, mask medium layer, insulation insulation gate dielectric layer and grid metal;The AlN/GaN groups be located at two layers AlGaN it Between;AlGaN/GaN/AlN/AlGaN/GaN heterojunction materials are epitaxially grown on the substrate, area of grid is defined in wafer surface, It is etched away for AlGaN/AlN layers below area of grid, and forms source electrode, drain and gate on this structure.
Each layer constituent and material category are as follows in the structure:
The substrate material is one kind in following material:Si, SiC, sapphire.
The thickness of the AlGaN insert layers is between 1 and 5nm.
The thickness of the GaN insert layers is between 1 and 3nm.
The thickness of the AlN insert layers is between 1 and 3nm.
The material of the mask medium layer can be:SiO2、Al2O3、HfO2、MgO。
The material of the insulation gate dielectric layer is any one in following material:Si3N4、Al2O3、AlN、HfO2、SiO2、 HfTiO、Sc2O3、Ga2O3、MgO、SiNO。
The source electrode and drain electrode is:It is one or more in titanium, aluminium, nickel, gold, platinum, iridium, molybdenum, tantalum, niobium, cobalt, zirconium, tungsten etc. Alloy.
The gate metal is one or more combinations of following conductive material:Platinum, iridium, nickel, gold, molybdenum, palladium, selenium, beryllium, TiN, polysilicon, ITO.
The preparation method of this novel enhancement type GaN MOS devices includes step in detail below:
(1) GaN or AlN buffer layers, intrinsic GaN channel layers, sheet are grown successively according to certain growth conditions on substrate Levy AlGaN insert layers, intrinsic GaN insert layers, intrinsic AlN insert layers, intrinsic AlGaN potential barrier;
(2) the AlGaN/AlN/GaN/AlGaN/GaN materials grown carry out lithography and etching (or ion implanting), shape At active region mesa;
(3) organic washing is carried out to the AlGaN/AlN/GaN/AlGaN/GaN materials for preparing active region mesa, with flowing Deionized water cleaning after be put into HCl:H2O=1:1~2min is cleaned in 10 solution, then using PECVD, ICPCVD or LPCVD is formed on its surface one layer of thin SiO2Mask of the dielectric layer as thermal oxide;
(4) photoetching gate electrode region etches SiO with RIE2Etching window is formed, is then placed in annealing furnace, temperature is 650 DEG C, at one atm, oxygen flow is that 2.5L/min aoxidizes 45min, and sample is put into 70 DEG C after the completion of oxidation Corrode 40min in KOH solution, remove the upper layer AlGaN/AlN hetero-junctions aoxidized, finally BOE is used to remove SiO2Mask;
(5) photoetching is carried out to the material for completing grid etching, etches source and drain ohmic contact regions, by electron beam evaporation or Magnetron sputtering prepares metal ohmic contact and is removed, and finally fast speed heat is moved back between 800 DEG C~900 DEG C in nitrogen environment Fiery (general 30s) forms Ohmic contact;
(6) material for forming source and drain Ohmic contact is put into atomic layer deposition apparatus, grows insulated gate in wafer surface Dielectric layer, makes source and drain areas contact hole by lithography, then etches away insulation gate dielectric layer, and source and drain Ohmic contact is made to be exposed;
(7) deposited by electron beam evaporation or the foregoing alloy gate electrodes material of Grown by Magnetron Sputtering, then to device into Row stripping technology processing forms gate electrode, is finally made annealing treatment in a nitrogen environment to entire wafer, completes integral device Preparation.
The invention has the advantages that:
(1) device of the invention is by introducing AlN/GaN insert layers so that corrosion is automatically stopped in GaN layer, retains grid Lower section AlGaN/GaN hetero-junctions avoids the influence to raceway groove in the process of corrosion process and dielectric layer deposited, improves GaN increasings The channel mobility of strong type device;
(2) present invention is from the angle of device structure design, by changing the position of AlN/GaN insert layers, Ke Yijing The really thickness of control grid lower section AlGaN layer so that device performance has high consistency, is conducive to the extensive system of device It is standby;
(3) compared with conventional wet corrodes the method for realizing enhancement device, the present invention only needs implementation method of the invention The structure for changing epitaxial layer does not need to change technological process, therefore implementation method simple possible.
Description of the drawings
The principle and its structure of device of the present invention can be more fully hereinafter illustrated by referring to accompanying drawing, and further describe this hair Bright exemplary embodiment, in the accompanying drawings:
Fig. 1 is the whole sectional structure chart of enhancement device prepared by conventional wet corrosion, and help preferably illustrates this hair Bright mentality of designing;
Fig. 2 is the whole cross-sectional view of enhancement device of the present invention;
Fig. 3~Figure 10 is the cross-section structure signal after each step manufacturing process of new structure enhancement device in the present invention Figure reflects the technique manufacturing process of the present invention.
Specific implementation mode
Hereinafter, the present invention is more fully described with reference to the accompanying drawings, and embodiment is shown in the accompanying drawings and its realized Journey, described embodiment are only a kind of way of realization in the present invention, i.e. the present invention should not be construed as limited to herein The embodiment of elaboration.Based on the embodiment, those skilled in the art are fully conveyed the scope of the present invention to.
Hereinafter, exemplary embodiment of the present invention is more fully described with reference to the accompanying drawings.
With reference to Fig. 2, the sequence of the device architecture from bottom to top includes substrate, GaN or AlN buffer layers, intrinsic GaN ditches successively Channel layer, intrinsic AlGaN insert layers, intrinsic GaN insert layers, intrinsic AlN insert layers, intrinsic AlGaN potential barrier, insulating medium layer and Grid metal.Preparation method includes step in detail below:
(1) as shown in figure 3, on a si substrate (substrate can be SiC or sapphire), growing one layer with MOCVD first Then GaN or AlN buffer layers grow intrinsic GaN channel layers, intrinsic AlGaN insert layers, intrinsic AlN insert layers, intrinsic successively again GaN insert layers, intrinsic AlGaN potential barrier;
(2) the AlGaN/AlN/GaN/AlGaN/GaN material good to epitaxial growth in (1) carries out lithography and etching, is formed Then active region mesa carries out organic washing, HCl is put into after being cleaned with the deionized water of flowing:H2O=1:It is clear in 10 solution 1~2min is washed, is then formed on its surface one layer of thin SiO using PECVD, ICPCVD or LPCVD2Dielectric layer is as hot oxygen The mask of change, sectional view are as shown in Figure 4;
(3) photoetching gate electrode region is carried out on architecture basics shown in Fig. 4, and SiO is etched with RIE2Etching window is formed, such as Shown in Fig. 5;
(4) it being formed after structure shown in Fig. 5, wafer is put into annealing furnace, temperature is 650 DEG C, at one atm, Oxygen flow is that 2.5L/min aoxidizes 45min, and sample, which is put into after the completion of oxidation in 70 DEG C of KOH solution, corrodes 40min, removes It is as shown in Figure 6 to form structure for the upper layer AlGaN/AlN hetero-junctions aoxidized;
(5) on architecture basics shown in Fig. 6, SiO is removed using BOE2Mask, as shown in Figure 7;
(6) photoetching is carried out on architecture basics as shown in Figure 7, is etched source and drain ohmic contact regions, is steamed by electron beam Hair or magnetron sputtering prepare metal ohmic contact and are removed, finally fast between 800 DEG C~900 DEG C in nitrogen environment Speed heat is annealed (general 30s), is formed Ohmic contact, is formed structure as shown in Figure 8;
(7) on architecture basics as shown in Figure 8, the material for forming source and drain Ohmic contact is put into atomic layer deposition apparatus In, insulation gate dielectric layer is grown in wafer surface, source and drain areas contact hole is made by lithography, then etches away insulation gate dielectric layer, make Source and drain Ohmic contact is exposed, as shown in Figure 9;
(8) in structure shown in Fig. 9, deposited by electron beam evaporation or Grown by Magnetron Sputtering alloy gate electrodes material, then Stripping technology processing is carried out to device and forms gate electrode, finally entire wafer is made annealing treatment in a nitrogen environment, is completed The preparation of integral device, as shown in Figure 10.
(9) the new structure HEMT device prepared by above step for conventional structure, move by channel electrons Shifting rate is obviously improved, and conducting resistance reduces.

Claims (14)

1. a kind of device architecture and implementation method being improved GaN enhancement type channel mobilities using novel barrier layer, feature are existed In:The structure includes:Substrate, GaN or AlN buffer layers, intrinsic GaN channel layers, intrinsic AlGaN insert layers, intrinsic GaN are inserted into Layer, intrinsic AlN insert layers, intrinsic AlGaN potential barrier, mask medium layer, insulation insulation gate dielectric layer and grid metal;The AlN/ GaN groups are located between two layers of AlGaN;AlGaN/GaN/AlN/AlGaN/GaN heterojunction materials are epitaxially grown on the substrate, in crystalline substance First surface defines area of grid, is etched away for AlGaN/AlN layers below area of grid, and form source electrode and drain electrode on this structure To form GaN enhancement devices.
2. the device architecture and reality according to claim 1 for improving GaN enhancement type channel mobilities using novel barrier layer Existing method, it is characterised in that:Substrate material therein is Si, SiC, sapphire.
3. the device architecture and reality according to claim 1 for improving GaN enhancement type channel mobilities using novel barrier layer Existing method, it is characterised in that:The thickness of AlGaN insert layers is between 1 and 5nm.
4. the device architecture and reality according to claim 1 for improving GaN enhancement type channel mobilities using novel barrier layer Existing method, it is characterised in that:The thickness of GaN insert layers is between 1 and 3nm.
5. the device architecture and reality according to claim 1 for improving GaN enhancement type channel mobilities using novel barrier layer Existing method, it is characterised in that:The thickness of AlN insert layers is between 1 and 3nm.
6. the device architecture and reality according to claim 1 for improving GaN enhancement type channel mobilities using novel barrier layer Existing method, it is characterised in that:The material of mask medium layer can be:SiO2、Al2O3、HfO2、MgO。。
7. the device architecture and reality according to claim 1 for improving GaN enhancement type channel mobilities using novel barrier layer Existing method, it is characterised in that:The material of insulation gate dielectric layer is any one in following material:Si3N4、Al2O3、AlN、 HfO2、SiO2、HfTiO、Sc2O3、Ga2O3、MgO、SiNO。
8. the device architecture and reality according to claim 1 for improving GaN enhancement type channel mobilities using novel barrier layer Existing method, it is characterised in that:Source electrode and drain electrode material is:In titanium, aluminium, nickel, gold, platinum, iridium, molybdenum, tantalum, niobium, cobalt, zirconium, tungsten etc. One or more alloys.
9. the device architecture and reality according to claim 1 for improving GaN enhancement type channel mobilities using novel barrier layer Existing method, it is characterised in that:Gate metal is one or more combinations of following conductive material:Platinum, iridium, nickel, gold, molybdenum, palladium, Selenium, beryllium, TiN, polysilicon, ITO.
10. the device architecture and reality according to claim 1 for improving GaN enhancement type channel mobilities using novel barrier layer Existing method, it is characterised in that:Mask medium layer below area of grid can be realized by ICP RIE dry etchings.
11. the device architecture and reality according to claim 1 for improving GaN enhancement type channel mobilities using novel barrier layer Existing method, it is characterised in that:AlGaN/AlN layers under area of grid can pass through wet etching and dry etching and wet method The method that corrosion combines is realized.
12. it is according to claim 11 using novel barrier layer improve GaN enhancement type channel mobilities device architecture and The method of implementation method, wet etching can be:First use oxygen plasma, ozone, hydrogen peroxide or other with strong oxidizing property Medium aoxidizes AlGaN/AlN, then falls oxide with hcl corrosion.
13. it is according to claim 11 using novel barrier layer improve GaN enhancement type channel mobilities device architecture and The method of implementation method, wet etching can be:First high-temperature oxydation AlGaN/AlN, reusable heat KOH solution corrosion fall oxide.
14. it is according to claim 11 using novel barrier layer improve GaN enhancement type channel mobilities device architecture and Implementation method, the method that dry etching and wet etching combine can be:A part of AlGaN first is etched with ICP, then rotten with wet method Etching off removes remaining AlGaN/AlN.
CN201710196720.3A 2017-03-29 2017-03-29 A kind of device architecture and implementation method improving GaN enhancement type channel mobilities using novel barrier layer Pending CN108666359A (en)

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CN110660643A (en) * 2019-09-05 2020-01-07 西交利物浦大学 Method for optimizing passivation of gallium nitride high electron mobility transistor
CN111048471A (en) * 2019-12-05 2020-04-21 中国电子科技集团公司第五十五研究所 Preparation method of n-channel and p-channel enhanced GaN device integrated structure
WO2020228352A1 (en) * 2019-05-10 2020-11-19 中国科学院苏州纳米技术与纳米仿生研究所 Semiconductor device and manufacturing method therefor
CN112713188A (en) * 2020-12-25 2021-04-27 西安电子科技大学芜湖研究院 GaN-based enhanced MIS-HEMT device and preparation method thereof
CN113035938A (en) * 2021-03-12 2021-06-25 浙江集迈科微电子有限公司 Multi-grid GaN device and preparation method thereof
CN113053742A (en) * 2021-03-12 2021-06-29 浙江集迈科微电子有限公司 GaN device and preparation method
CN113299766A (en) * 2020-02-21 2021-08-24 北京大学 GaN quasi-vertical structure diode and preparation method thereof

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CN102064108A (en) * 2010-11-12 2011-05-18 中国电子科技集团公司第五十五研究所 Method for manufacturing medium/nitride composite structure enhanced field effect transistor
CN106298887A (en) * 2016-09-30 2017-01-04 中山大学 A kind of preparation method of high threshold voltage high mobility notched gates MOSFET

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CN102064108A (en) * 2010-11-12 2011-05-18 中国电子科技集团公司第五十五研究所 Method for manufacturing medium/nitride composite structure enhanced field effect transistor
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Cited By (10)

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Publication number Priority date Publication date Assignee Title
WO2020228352A1 (en) * 2019-05-10 2020-11-19 中国科学院苏州纳米技术与纳米仿生研究所 Semiconductor device and manufacturing method therefor
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CN111048471A (en) * 2019-12-05 2020-04-21 中国电子科技集团公司第五十五研究所 Preparation method of n-channel and p-channel enhanced GaN device integrated structure
CN113299766A (en) * 2020-02-21 2021-08-24 北京大学 GaN quasi-vertical structure diode and preparation method thereof
CN113299766B (en) * 2020-02-21 2022-08-26 北京大学 GaN quasi-vertical structure diode and preparation method thereof
CN112713188A (en) * 2020-12-25 2021-04-27 西安电子科技大学芜湖研究院 GaN-based enhanced MIS-HEMT device and preparation method thereof
CN112713188B (en) * 2020-12-25 2022-12-02 西安电子科技大学芜湖研究院 GaN-based enhanced MIS-HEMT device and preparation method thereof
CN113035938A (en) * 2021-03-12 2021-06-25 浙江集迈科微电子有限公司 Multi-grid GaN device and preparation method thereof
CN113053742A (en) * 2021-03-12 2021-06-29 浙江集迈科微电子有限公司 GaN device and preparation method

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Application publication date: 20181016