CN102044501A - 集成电路结构 - Google Patents

集成电路结构 Download PDF

Info

Publication number
CN102044501A
CN102044501A CN2010105128624A CN201010512862A CN102044501A CN 102044501 A CN102044501 A CN 102044501A CN 2010105128624 A CN2010105128624 A CN 2010105128624A CN 201010512862 A CN201010512862 A CN 201010512862A CN 102044501 A CN102044501 A CN 102044501A
Authority
CN
China
Prior art keywords
metal
projection
under
semiconductor chip
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2010105128624A
Other languages
English (en)
Other versions
CN102044501B (zh
Inventor
郭宏瑞
刘重希
余振华
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN102044501A publication Critical patent/CN102044501A/zh
Application granted granted Critical
Publication of CN102044501B publication Critical patent/CN102044501B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05555—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/14104—Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09427—Special relation between the location or dimension of a pad or land and the location or dimension of a terminal
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

本发明提供一种集成电路结构，包括一第一工件，其择自一半导体芯片及一封装基材所组成的群组，其中该第一工件包含多个第一凸块下金属，分布于此第一工件的主要表面上；以及多个第一金属凸块，其中每一第一金属凸块直接位于一个此第一凸块下金属上并与其电性连接，其中所述多个第一凸块下金属及多个第一金属凸块之间的配置具有一叠对补偿，且至少一部分的第一凸块下金属与其对应的此第一金属凸块具有错位。本发明具有众多优点，例如可消除半导体芯片上及封装基材上凸块不对齐的情况，且此解决方法不需增加制造成本，既然其仅包含进行一测量步骤，剩余步骤均可由步进曝光机台自动化完成。

Description

集成电路结构
技术领域
本发明涉及集成电路，且特别涉及一种含集成电路芯片及封装基板的封装集成，以及其制造方法。
背景技术
现今集成电路形成于半导体芯片上。为了增加产能及降低制造成本，集成电路制造在半导体晶片中，每一晶片中含有大量相同的半导体芯片。待集成电路制造完毕后，自晶片切割下半导体芯片并将其封装以作使用。
在一般封装工艺中，首先将半导体芯片(公知技术中也称为裸片)贴附(attach)于封装基材上。此步骤包含以物理方式将半导体芯片固定于封装基材上，及将半导体芯片上的连接垫与封装基材上的连接垫相连接，且更使用底部填充材料(通常包含环氧树脂)使接合更为固定。半导体芯片之间可使用倒装芯片连接或导线连接来作接合。所得的封装体称为球栅阵列(ball grid array，BGA)模块。可整合许多不同功能的芯片于同一球栅阵列模块中，以形成***级封装(system-in-package)模块。
图1及图2显示半导体芯片100封装至封装基材110上于各种中间阶段的剖面图。半导体芯片100包含凸块102及其上的助熔剂(flux)104。封装基材110包含焊料凸块112。凸块102的位置及节距与焊料凸块112的位置及节距彼此互相准确对齐。然而，既然封装基材110(及/或半导体芯片100)具有多层不同材料的膜层，焊料凸块112可能会因多层结构所产生的应力造成其位置偏移(position shift)(如箭头114所示)而造成应力产生于这些叠层中。位置偏移会造成焊料凸块112彼此之间的节距改变，而与预设值有所差异。因此，如图2所示，当半导体芯片100及封装基材110互相接合时，凸块102及焊料凸块112未能准确对齐，造成有更多应力施加至半导体芯片100，且当某些凸块102与其所对应的焊料凸块112完全错位(fully disalignment)时，可能会造成短路。
发明内容
为克服现有技术中的缺陷，本发明提供一种集成电路结构，包括：一第一工件，择自由下列组成的群组：一半导体芯片及一封装基材，其中此第一工件包含：多个第一凸块下金属，分布于此第一工件的主要表面上；以及多个第一金属凸块，其中每一第一金属凸块直接位于一个此第一凸块下金属上并与其电性连接，其中所述多个第一凸块下金属及多个第一金属凸块之间的配置具有一叠对补偿，且至少一部分的第一凸块下金属与其对应的此第一金属凸块具有错位。
本发明也提供一种集成电路结构，包括：一半导体芯片，包含多个第一凸块下金属分布于此半导体芯片的主要表面上；一封装基材，包含多个第二凸块下金属分布于此封装基材的主要表面上；以及多个含铜凸块，且每一含铜凸块通过焊接方式与所述多个第一凸块下金属或所述多个第二凸块下金属其中一者电性连接，并通过非焊接方式与另一者电性连接，且其中所述多个含铜凸块与所述多个第一凸块下金属或所述多个第二凸块下金属之间具有一叠对补偿。
本发明还提供一种集成电路结构，包括：一半导体芯片及一封装基材，包含：多个凸块下金属，分布于此半导体芯片的主要表面上；以及多个金属凸块，其中至少一部分的多个凸块下金属与其下方所对应的金属凸块错位，且其中靠近此半导体芯片中央的金属凸块与其下方所对应的金属凸块的错位较远离此半导体芯片中央的金属凸块大。
本发明具有众多优点，例如可消除半导体芯片上及封装基材上凸块不对齐的情况，且此解决方法不需增加制造成本，既然其仅包含进行一测量步骤，剩余步骤均可由步进曝光机台自动化完成。
为让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举出优选实施例，并配合附图，进行详细说明。
附图说明
图1及图2显示传统接合工艺接合半导体芯片及封装基材于各种中间阶段的剖面图；
图3A至图7显示依照本发明实施例凸块制造于各种中间阶段的俯视图及剖面图；
图8显示半导体基材的俯视图，其中所凸块使用叠对补偿形成；
图9显示接合半导体芯片及封装基材；
图10掩饰半导体芯片及封装基材的剖面图，其中半导体芯片及封装基材的凸块皆使用叠对补偿形成；
图11显示半导体芯片的俯视图，其中凸块在X及Y方向皆使用叠对补偿；
图12显示半导体芯片的俯视图，其中在形成凸块时施予叠对补偿使其旋转；
图13显示叠对补偿使用于整个晶片上的半导体芯片，其中凸块位置整体转移；
图14显示叠对补偿使用于整个晶片上的半导体芯片，其中凸块位置整体旋转；
图15显示叠对补偿使用于整个晶片上的半导体芯片，其中凸块位置整体偏移。
其中，附图标记说明如下：
2～晶片              10～半导体芯片
11～半导体基材       12～凸块下金属
12_1～凸块下金属     12_2～凸块下金属
14～凸块             14_1～凸块
14_2～凸块           16～光致抗蚀剂
16’～开口边界       18～光刻掩模
20～叠对补偿         22～步进曝光机台
24～介电层           26～叠对补偿
40～封装基材         42_1～凸块下金属
42_2～凸块下金属     44～凸块
44_1～凸块           44_2～凸块
56～叠对补偿         100～半导体芯片
102～凸块            104～助熔剂
110～封装基材        112～焊料凸块
114～偏移        P1～节距
P1’～节距
具体实施方式
本发明接下来将会提供许多不同的实施例以实施本发明中不同的特征。然而，这些实施例并非用于限定本发明。以下所讨论的特定实施例仅用于举例本发明实施例的制造及使用，但不限定本发明的范畴。
在此，将揭示依照本发明实施例制造集成电路的新颖方法，及将举例一实施例于制造时的各种中间阶段，并将讨论此实施例的各种变化。在本发明所举例的各种附图及实施例中，相似参考标号代表相似元件。
图3A显示半导体芯片10及封装基材40的剖面图。可知的是，所显示的半导体芯片10及封装基材40在同一平面中仅是用于举例及比较，其事实上为分开的元件。封装基材40制造完毕，而半导体芯片10的凸块尚未形成。半导体芯片10可包含半导体基材11及集成电路装置(未显示)，例如形成晶体管于半导体基材11表面上。半导体芯片10也可为翘曲的(warpage)。金属连接元件12(标记为12_1、12_2)，可为形成于半导体芯片10表面上的凸块下金属(under bump metallurgies，UBMs)或连接垫。凸块下金属12_1、12_2之间的节距(pitch)为P1。图示中两元件之间的节距由两元件的中央开始测量，或也可测量相对应的侧边。封装基材40包含金属绕线(routing metal lines)及通孔(未显示)，其可电性连接封装基材40一侧的焊料凸块44(标记为44_1、44_2)至另一相反侧。封装基材40更包含金属连接元件(metallic connections)42(标记为42_1、42_2)，其可为凸块下金属或连接垫。焊料凸块44形成于凸块下金属42上，在凸块下金属42_1、42_2之间的节距为P1’。
在随后工艺步骤中，凸块14_1、14_2(未显示于图3A，请参见图6及图7)各自形成于凸块下金属12_1、12_2上，用以各自与凸块44_1、44_2接合。因此，凸块44_1、44_2之间所预设的节距(其可能会与凸块下金属42_1、42_2之间的节距相同)与凸块14_1、14_2之间的节距P1’相同。然而，由于封装基材40(或可能是半导体芯片10)中因材料不同而导致的应力(例如不同材料层的热膨胀系数的差异)，封装基材40及/或半导体芯片10可能是歪曲的(distorted)，例如弯曲(bent)，造成节距P1’与预设值有所差异。因此，在图3中，节距P1与节距P1’不同。在本说明书中，词汇“歪曲”用于指称凸块的位置及节距的改变，其中歪曲可包含位置的偏移、旋转、及/或任何其他三级扭曲(third-order distortion)(非规则性的扭曲)。为了举例说明，凸块下金属12间的节距P1小于凸块44间的节距P1’，然而其他实施例中，节距P1可大于或小于节距P1’。图3B显示图3A所示结构的俯视图。此俯视图显示半导体芯片10可包含多个凸块下金属42，及封装基材40可包含多个凸块44。图3A的剖面图来自于图3B中沿线段3A-3A的剖面。
在一实施例中，在完成封装基材40的制造后，测量凸块44间的节距(例如节距P1’)。所测量的节距可与凸块节距的预设值比较(预设与节距P1相同)以判断凸块44的位置歪曲程度。接着，形成凸块14(在图5至图7中标记为凸块14_1、14_2)以使其间的节距与所测量得到的节距P1’相同。图4所示的制造步骤显示对光致抗蚀剂进行曝光(光致抗蚀剂16也可由其他掩模层来替代，例如干膜)。值得注意的是，所举例的光致抗蚀剂16形状是在曝光及显影后的形状，而非仅进行曝光时的形状。光致抗蚀剂16定义出凸块14的图案及位置(图6及图7)。在一实施例中，使用光刻掩模18来对光致抗蚀剂16进行曝光，此光刻掩模18包含可使光穿透的透明图案及阻挡光的不透明图案。此光刻掩模18的图案不会考虑封装基材40中歪曲的凸块。因此，所定义的凸块14的图案间的节距仍为P1。
为了确保直接形成在凸块下金属12_1、12_2上的凸块对齐凸块44_1、44_2，欲形成在凸块下金属12_1、12_2上的凸块需具有节距P1’。因此，在对光致抗蚀剂16进行曝光时，于此曝光步骤中施予叠对补偿(overlay offset)，其中叠对补偿(标记为倾斜箭头20)由进行曝光的装置来进行，例如图示所举例的步进曝光机台(stepper)22。此叠对补偿使曝光后的光致抗蚀剂16具有与光刻掩模的节距P1不同的节距P1’。如未施予叠对补偿，光致抗蚀剂16中的开口边界将位在如16’所示的位置。如节距P1’大于节距P1，叠对补偿将造成图案扩张(尺寸缩放(scaling)的一种)。在其他实施例中，依照凸块44的位置歪曲程度，可调整步进曝光机台22以使叠对补偿造成光致抗蚀剂16中的曝光图案缩小、旋转及/或其他三度空间的扭曲。
参见图5，由例如电镀形成凸块14(标记为14_1、14_2)。凸块14可由镀铜(plated copper)形成，且更可包含镀镍层(未显示)于此镀铜层上。再者，也可形成一电镀焊料薄层(未显示)于此镀镍层上。在形成凸块14之后，移除光致抗蚀剂16，最终结构如图6所示。可知的是，由于叠对补偿，凸块14及凸块44具有相同的节距P1’，因此凸块14及凸块44的接合可无任何错位。此外，更可观察到凸块14与其所对应的下方的凸块下金属12无任何错位。
图7显示本发明另一实施例，其中凸块14为焊料凸块，用以取代图5及图6的铜凸块。在形成焊料凸块14时，也可由施予叠对补偿来定义焊料凸块14的位置。此叠对补偿可在对光致抗蚀剂(未显示)进行图案化时施予，光致抗蚀剂可为用以图案化介电层24的光致抗蚀剂。借此，凸块下金属12与凸块14接合。施予叠对补偿的细节基本上如同前述，故在此不再重复赘述。
图8显示以图3至图7的步骤制造的半导体芯片10的俯视图。为了显示叠对补偿的效果，以实线所示的图案为经过叠对补偿的图案，且为经上述步骤制造的图案。以虚线圆圈所示的图案为不经叠对补偿的图案，且此图案仅为光刻掩模18的图案(图4)。虚线圆圈的位置亦为凸块下金属12的位置。值得注意的是，凸块14间的节距在在X方向上具有尺寸补偿。
图9显示半导体芯片10与封装基材40的接合。随着在形成凸块14时施予叠对补偿，凸块14准确对齐其所对应的凸块44。在形成如图9所示的结构后，在凸块44及/或14中的焊料回流以形成封装总成。
图10显示本发明另一实施例的剖面图，其中不仅对半导体芯片10施予叠对补偿，且对封装基材40施予额外的叠对补偿。在此实施例中，结合形成凸块14时的叠对补偿及形成凸块44时的额外的叠对补偿，可以抵销半导体芯片10及封装基材40之间的位置/节距的差异，因此凸块14及44可互相对齐。凸块44可具有与凸块14相同或不同的结构，用于施予叠对补偿至凸块44的工艺，基本上与前述相同。值得注意的是，对于凸块14的叠对补偿(标记为箭头26)及对于凸块44时的叠对补偿(标记为箭头56所示)为相反(inversed)的。亦即，如叠对补偿26是使凸块14间的节距增加，则叠对补偿56是使凸块44间的节距缩短，反之亦然。
图11及图12显示另两种可能的实施例。图11显以二维的叠对补偿形成凸块14，其对半导体芯片10(或封装基材40)的X及Y方向施予叠对补偿。再者，可能会发生凸块14及44的错位需要旋转凸块14及/或44凸块的情况。图12显示的实施例中，对凸块14及/或44施予叠对补偿，使其相较于其所预设的位置及相较于其下方元件(例如凸块下金属12)的方向有所旋转。
可知的是，仍有多种变化例可用以实施本发明的实施例。例如，可在形成凸块14及/或44时施予叠对补偿，但不对例如凸块下金属12及/或42的下层元件(underlying features)施予叠对补偿，以使制造成本得以降低。然而，在另一实施例中，可在形成一或多个例如凸块下金属12及/或42的下层元件时施予叠对补偿，然所剩余的下层元件不施予任何叠对补偿。在又一实施例中，可结合各种叠对补偿，例如扩展、缩减、旋转及三级扭曲，以使凸块14及凸块44尽可能的对齐。
叠对补偿可施予至整个在晶片中的全部芯片或仅施予至晶片中的部分芯片。当使用步进曝光机台22(参见图4)以曝光光致抗蚀剂16时，在同一晶片中的每一半导体芯片10皆需曝光。因此，为了对每一半导体芯片10进行曝光，可单独对半导体芯片进行叠对补偿，或对全部芯片进行叠对补偿。图13至图15更显示对同一晶片中多个芯片进行总体性叠对补偿的各阶段。在图13中，晶片2中的半导体芯片10的歪曲程度皆相同，且在全部芯片中形成凸块14(未显示)时皆施予相同的叠对补偿(称为位置转移)。在图14中，晶片2中的半导体芯片10具有不同的旋转的歪曲，靠近晶片2中央的芯片相较于远离晶片2中央的芯片具有较小的旋转的歪曲。因此，进行对称的旋转补偿。在图15中，晶片2中的半导体芯片10具有不同的偏移的歪曲，靠近晶片2中央的芯片较远离晶片2中央的芯片具有较小的移位歪曲(shift distortions)。因此，进行对称的尺寸调整，以使对靠近晶片中央的芯片施予较小的叠对补偿，而对远离晶片中央的芯片施予较大的叠对补偿。
本发明具有众多优点，例如可消除半导体芯片上及封装基材上凸块不对齐的情况，且此解决方法不需增加制造成本，既然其仅包含进行一测量步骤，剩余步骤均可由步进曝光机台自动化完成。
虽然本发明已以数个优选实施例公开如上，然其并非用以限定本发明，任何所属技术领域中的普通技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰，因此本发明的保护范围当视随附的权利要求所界定的保护范围为准。此外，本领域普通技术人员将可依照本发明所揭示的现有或未来所发展的特定程序、机器、制造、物质的组合、功能、方法或步骤达成相同的功能或相同的结果。因此本发明的保护范围包含这些程序、机器、制造、物质的组合、功能、方法或步骤。再者，每一权利要求皆可视为建构一单独的实施例，且各权利要求及实施例的结合皆在本发明的范围中。

Claims (11)

1.一种集成电路结构，包括：
一第一工件，择自一半导体芯片及一封装基材所组成的群组，其中该第一工件包含：
多个第一凸块下金属，分布于该第一工件的主要表面上；以及
多个第一金属凸块，其中每一第一金属凸块直接位于一个该第一凸块下金属上并与其电性连接，其中所述多个第一凸块下金属及所述多个第一金属凸块之间的配置具有一叠对补偿，且至少一部分的第一凸块下金属与其对应的所述第一金属凸块具有错位。
2.如权利要求1所述的集成电路结构，其中该叠对补偿包含尺寸补偿，所述多个第一金属凸块具有第一节距，及其所对应的第一凸块下金属具有与该第一节距不同的第二节距。
3.如权利要求1所述的集成电路结构，其中该叠对补偿包含旋转补偿，所述多个第一金属凸块配置于相对于所述多个第一凸块下金属有所旋转的位置。
4.如权利要求1所述的集成电路结构，其中靠近该第一工件中央的金属凸块与其下方所对应的所述第一金属凸块的错位较远离该第一工件中央的金属凸块大。
5.如权利要求1所述的集成电路结构，还包含：
一第二工件，其中该第二工件与该第一工件通过所述多个第一金属凸块接合，且其中该第二工件包含多个第二凸块下金属，且每一所述第二凸块下金属与一个所述第一金属凸块接合，
其中该第二工件还包含多个第二金属凸块，所述多个第二凸块下金属与所述多个第二金属凸块具有额外的叠对补偿，且每一第一金属凸块与其所对应的第二金属凸块对齐。
6.一种集成电路结构，包括：
一半导体芯片，包含多个第一凸块下金属分布于该半导体芯片的主要表面上；
一封装基材，包含多个第二凸块下金属分布于该封装基材的主要表面上；以及
多个含铜凸块，且每一含铜凸块通过焊接方式与所述多个第一凸块下金属或所述多个第二凸块下金属其中一者电性连接，并通过非焊接方式与另一者电性连接，且其中所述多个含铜凸块与所述多个第一凸块下金属或所述多个第二凸块下金属之间具有一叠对补偿。
7.如权利要求6所述的集成电路结构，其中该叠对补偿介于所述多个含铜凸块及所述多个第一凸块下金属之间或介于所述多个含铜凸块及所述多个第二凸块下金属之间。
8.如权利要求6所述的集成电路结构，还包含一额外的叠对补偿介于所述多个第一及第二凸块下金属两者的剩余未有叠对补偿者与所述多个含铜凸块之间。
9.一种集成电路结构，包括：
一半导体芯片及一封装基材，包含：
多个凸块下金属，分布于该半导体芯片的主要表面上；以及
多个金属凸块，其中至少一部分的多个凸块下金属与其下方所对应的金属凸块错位，且其中靠近该半导体芯片中央的金属凸块与其下方所对应的金属凸块的错位较远离该半导体芯片中央的金属凸块大。
10.如权利要求9所述的集成电路结构，其中所述多个金属凸块以一第一尺寸为节距分布，且所述多个凸块下金属以一不同于该第一尺寸的第二尺寸为节距分布。
11.如权利要求9所述的集成电路结构，其中所述多个金属凸块相对于所述多个凸块下金属有所旋转。
CN2010105128624A 2009-10-20 2010-10-08 集成电路结构 Active CN102044501B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US25330509P 2009-10-20 2009-10-20
US61/253,305 2009-10-20
US12/784,327 US8446007B2 (en) 2009-10-20 2010-05-20 Non-uniform alignment of wafer bumps with substrate solders
US12/784,327 2010-05-20

Publications (2)

Publication Number Publication Date
CN102044501A true CN102044501A (zh) 2011-05-04
CN102044501B CN102044501B (zh) 2012-12-19

Family

ID=43878668

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2010105128624A Active CN102044501B (zh) 2009-10-20 2010-10-08 集成电路结构

Country Status (3)

Country Link
US (2) US8446007B2 (zh)
CN (1) CN102044501B (zh)
TW (1) TWI440149B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109407358A (zh) * 2018-10-29 2019-03-01 深圳市华星光电技术有限公司 一种显示面板的修复方法及显示面板
CN109524412A (zh) * 2018-11-14 2019-03-26 长江存储科技有限责任公司 三维存储器及其制造方法

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8581399B2 (en) * 2011-07-28 2013-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Metal bump structure
US20130153645A1 (en) * 2011-11-17 2013-06-20 Princeton Lightwave, Inc. Process for Hybrid Integration of Focal Plane Arrays
US8987884B2 (en) 2012-08-08 2015-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. Package assembly and methods for forming the same
US11183482B2 (en) * 2019-09-17 2021-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Shift control method in manufacture of semiconductor device
US11094668B2 (en) * 2019-12-12 2021-08-17 Micron Technology, Inc. Solderless interconnect for semiconductor device assembly
US20230021655A1 (en) * 2021-07-22 2023-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacturing the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6015652A (en) * 1998-02-27 2000-01-18 Lucent Technologies Inc. Manufacture of flip-chip device
US20080230901A1 (en) * 2007-03-20 2008-09-25 International Business Machines Corporation Structure for controlled collapse chip connection with displaced captured pads

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4581680A (en) * 1984-12-31 1986-04-08 Gte Communication Systems Corporation Chip carrier mounting arrangement
US5777855A (en) * 1996-06-18 1998-07-07 Eastman Kodak Company Method and apparatus for connecting flexible circuits to printed circuit boards
US7007833B2 (en) * 1997-05-27 2006-03-07 Mackay John Forming solder balls on substrates
JP3028791B2 (ja) * 1997-08-06 2000-04-04 日本電気株式会社 チップ部品の実装方法
US6335222B1 (en) * 1997-09-18 2002-01-01 Tessera, Inc. Microelectronic packages with solder interconnections
JP2000252613A (ja) * 1999-02-26 2000-09-14 Canon Inc 電子回路基板及びその半田付け方法
US6274474B1 (en) * 1999-10-25 2001-08-14 International Business Machines Corporation Method of forming BGA interconnections having mixed solder profiles
US6444561B1 (en) * 2000-10-02 2002-09-03 Industrial Technology Research Institute Method for forming solder bumps for flip-chip bonding by using perpendicularly laid masking strips
EP1332654B1 (en) * 2000-11-10 2005-01-12 Unitive Electronics, Inc. Methods of positioning components using liquid prime movers and related structures
US6974330B2 (en) * 2002-08-08 2005-12-13 Micron Technology, Inc. Electronic devices incorporating electrical interconnections with improved reliability and methods of fabricating same
TW582077B (en) * 2002-12-18 2004-04-01 Advanced Semiconductor Eng Flip-chip substrate and the flip-chip bonding process thereof
US7211736B2 (en) * 2003-10-31 2007-05-01 Hewlett-Packard Development Company, L.P. Connection pad layouts
US7767493B2 (en) * 2005-06-14 2010-08-03 John Trezza Post & penetration interconnection
US7759776B2 (en) * 2006-03-28 2010-07-20 Taiwan Semiconductor Manufacturing Co., Ltd. Space transformer having multi-layer pad structures
US7772104B2 (en) * 2007-02-02 2010-08-10 Freescale Semiconductor, Inc. Dynamic pad size to reduce solder fatigue
US7833881B2 (en) 2007-03-02 2010-11-16 Micron Technology, Inc. Methods for fabricating semiconductor components and packaged semiconductor components
US7834449B2 (en) * 2007-04-30 2010-11-16 Broadcom Corporation Highly reliable low cost structure for wafer-level ball grid array packaging
US8178392B2 (en) * 2007-05-18 2012-05-15 Stats Chippac Ltd. Electronic system with expansion feature
US7547630B2 (en) 2007-09-26 2009-06-16 Texas Instruments Incorporated Method for stacking semiconductor chips
US7666780B2 (en) * 2007-12-12 2010-02-23 International Business Machines Corporation Alignment verification for C4NP solder transfer
US8080884B2 (en) * 2008-06-27 2011-12-20 Panasonic Corporation Mounting structure and mounting method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6015652A (en) * 1998-02-27 2000-01-18 Lucent Technologies Inc. Manufacture of flip-chip device
US20080230901A1 (en) * 2007-03-20 2008-09-25 International Business Machines Corporation Structure for controlled collapse chip connection with displaced captured pads

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109407358A (zh) * 2018-10-29 2019-03-01 深圳市华星光电技术有限公司 一种显示面板的修复方法及显示面板
CN109524412A (zh) * 2018-11-14 2019-03-26 长江存储科技有限责任公司 三维存储器及其制造方法

Also Published As

Publication number Publication date
TWI440149B (zh) 2014-06-01
US20110089560A1 (en) 2011-04-21
US8835193B2 (en) 2014-09-16
TW201115702A (en) 2011-05-01
US8446007B2 (en) 2013-05-21
US20130236994A1 (en) 2013-09-12
CN102044501B (zh) 2012-12-19

Similar Documents

Publication Publication Date Title
CN102044501B (zh) 集成电路结构
CN106465545B (zh) 半导体器件和用于通过动态通孔剪切进行的板式封装的自适性图案化方法
KR100818534B1 (ko) 칩-형 전자 부품 및 그 제조 방법 및 그 제조에 사용하는 유사 웨이퍼 및 그 제조 방법
KR101650670B1 (ko) 패드 인터커넥트 구조체 상의 필러, 이러한 인터커넥트 구조체를 포함하는 반도체 다이 및 다이 조립체, 및 관련 방법
CN103794569B (zh) 封装结构及其制法
CN103258750B (zh) 半导体器件及其制作方法
US11011487B2 (en) Semiconductor package having varying conductive pad sizes
TW201010020A (en) Semiconductor device and method for manufacturing it
TWI453839B (zh) 半導體裝置及其製造方法
KR20100005112A (ko) 인터포저를 갖는 플립칩 및 그 제조 방법
US7960837B2 (en) Semiconductor package
TWI772829B (zh) 半導體封裝之佈線校正方法
JP2010016332A (ja) チップ・レベルのアンダーフィル・プロセスおよびその構造
TWI742485B (zh) 半導體裝置製造中的移位控制方法
CN103681516A (zh) 制造半导体装置的方法
US11158600B2 (en) Lithography process for semiconductor packaging and structures resulting therefrom
TWI440412B (zh) 超薄多層基板之封裝方法
CN101290891A (zh) 晶片级芯片尺寸封装方法
CN109791894A (zh) 单元特定渐进式对准的半导体装置及方法
US7576551B2 (en) Test socket and test board for wafer level semiconductor testing
CN103915397B (zh) 多裸晶、高电流晶圆级封装
JP2692620B2 (ja) マルチチップモジュールの実装構造
US7399695B2 (en) Integrated die bumping process
JPH10303151A (ja) 電子部品の製造方法
CN105633034B (zh) 半导体晶圆凸点结构

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant