CN101993031B - Protection structure and semiconductor structure of contact pad - Google Patents
Protection structure and semiconductor structure of contact pad Download PDFInfo
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- CN101993031B CN101993031B CN200910165776.8A CN200910165776A CN101993031B CN 101993031 B CN101993031 B CN 101993031B CN 200910165776 A CN200910165776 A CN 200910165776A CN 101993031 B CN101993031 B CN 101993031B
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- contact pad
- insulating barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
Abstract
The invention provides a protection device of a contact pad. The contact pad is arranged in a dielectric layer on a semiconductor substrate, and comprises a connecting region and a peripheral region surrounding the connecting region; a protection structure comprises at least one retaining wall, an insulating layer and a mask layer; the retaining wall is arranged in the dielectric layer on the peripheral region, and surrounds the connecting region; the insulating layer is arranged on the dielectric layer; and the mask layer is arranged on the dielectric layer, covers the insulating layer, and is provided with an opening for exposing the connecting region of the contact pad.
Description
Technical field
The present invention discloses a kind of protective device, particularly a kind of protective device being applied in MEMS and contact pad.
Background technology
Along with scientific and technological development and the development of semiconductor technology, electronic component is successfully applied to various life aspects.MEMS (Micro-electro-mechanical system, MEMS) technology, be to utilize known semi-conductive technique to manufacture small mechanical organ, by modes such as plating, etching of semiconductor technology, can complete the mechanical organ with micron-scale.Common application has the voltage controlled element using in ink-jet table printing machine, in automobile, as the gyroscope of detecting tilting of automobile, or in microphone, is used for the shake film etc. of sensing sound.Micro electro mechanical system (MEMS) technology, owing to frame for movement and electronic circuit can being integrated, therefore can be manufactured (batch fabrication) in batches, and has the advantages such as low cost, high-quality and high integration.
At present, MEMS is with System on Chip/SoC (system on chip, SOC) concept is incorporated on one chip, particularly with the prepared chip of standard CMOS (CMOS) technique, for example, on same a slice tube core (die), form MEMS region and CMOS region simultaneously.And integrating in the technique of existing CMOS and MEMS, may produce many problems, for example, when carrying out technique with formation CMOS region element or forming MEMS, between each region, how avoiding technologic and influence each other and subsequent product is used interference each other, is at present must research and the problem solving.
Summary of the invention
So the present invention proposes a kind of protection structure; a kind of boundary that is applied in micro electronmechanical region and non-micro electronmechanical region particularly; or be applied to the protective device of contact pad in non-micro electronmechanical region, to guarantee in semiconductor technology, micro electronmechanical region and non-micro electronmechanical region can be not interfering with each other.
On the one hand, the invention provides a kind of protective device of contact pad.Contact pad is arranged in the dielectric layer on semiconductor base, and contact pad comprises join domain and the neighboring area that is surrounded on join domain.This protection structure comprises at least one barricade, insulating barrier and mask layer.In the dielectric layer of dams setting on neighboring area, and surround join domain.Insulating barrier is arranged on dielectric layer.Mask layer is arranged on dielectric layer and covers insulating barrier, and has opening to expose the join domain of contact pad.
On the other hand, the present invention separately provides a kind of semiconductor structure, and it has comprised semiconductor base, dielectric layer, protection structure and mask layer.Semiconductor base comprises micro electronmechanical region and non-micro electronmechanical region, and dielectric layer arranges on semiconductor base.Protection structure is located between micro electronmechanical region district and non-micro electronmechanical region, and it includes and is arranged at the top metal level of dielectric layer, the first barricade at least one dielectric layer being arranged on the metal level of top, and is arranged at the insulating barrier on dielectric layer.Mask layer is arranged on dielectric layer and covers insulating barrier.
The protection structure that the present invention proposes; be useful in the boundary of contact pad or MEMS and non-MEMS; the protection structure of its sealing can effectively be avoided for example erosion of hydrofluoric acid of etching gas; can protect the element in non-micro electronmechanical region can be not destroyed, and improve product yield and reliability.
Accompanying drawing explanation
Fig. 1 is the floor map in micro electronmechanical region and non-micro electronmechanical region in the present invention.
Fig. 2 is the generalized section of contact pad protection structure in the present invention.
Fig. 3 is the plane figure schematic diagram of barricade of the present invention.
Fig. 4 to Fig. 6 is the embodiment schematic diagram of contact pad protection structure in the present invention.
Fig. 7 is the generalized section of the protection structure between micro electronmechanical region and non-micro electronmechanical region in the present invention.
Fig. 8 is another embodiment schematic diagram that the present invention protects structure.
Description of reference numerals
50: tube core 118: insulating barrier
100: micro electronmechanical region 120: mask layer
101: protection structural region 122: etchant
102: non-micro electronmechanical region 123: opening
104: contact pad 124: bottom
106: semiconductor base 126: adhesion coating
108: join domain 128: metal level
110: neighboring area 130: top metal level
112: 132: the second barricades of dielectric layer
116: 134: the first barricades of barricade
The specific embodiment
Please refer to Fig. 1; Fig. 1 is the micro electronmechanical region of the preferred embodiments of the present invention and the floor map in non-micro electronmechanical region; this sentences tube core (die) and illustrates for example; the present invention is applied in the protective device of MEMS and contact pad, and actual process is still performed on the wafer that includes a plurality of tube cores.As shown in Figure 1, on tube core 50, there is micro electronmechanical region 100 and non-micro electronmechanical region 102.In micro electronmechanical region 100, be provided with various microcomputer electric component (not shown)s, such as vibrating diaphragm, motor etc., but not 102, micro electronmechanical region can be logic region, storage area or peripheral circuit area etc., in it, be provided with various semiconductor element (not shown)s, for example various active components or passive element.The surface in non-micro electronmechanical region 102 has a plurality of contact pads 104, makes extraneous signal be able to drive the element in non-micro electronmechanical region 102 by corresponding contact pad 104, and carries out the I/O of each signal.
Conventionally when preparing microcomputer electric component, can be after completing the various semiconductor technologies such as all microcomputer electric components, semiconductor element and metal interconnecting, by this System on Chip/SoC through etch process at least one times, with etchants such as etching gas (such as hydrofluoric acid (HF)) or etching solutions, remove the dielectric layer between metal layers (IMD) in micro electronmechanical region 100, various movable or there is the mechanical organ of space micro-structural to form in micro electronmechanical region 100.And while carrying out in order to ensure etching; etchant can or not infiltrate non-micro electronmechanical region 102 via micro electronmechanical region 100 and the intersection in non-micro electronmechanical region 102 via the edge of each contact pad 104; and destroy the element in non-micro electronmechanical region 102; the present invention proposes a kind of protective device; it can be applicable to the boundary in micro electronmechanical region 100 and non-micro electronmechanical region 102, or is applied to contact pad 104 in non-micro electronmechanical region 102.
First, take the protective device of each contact pad 104 in non-micro electronmechanical region 102 as example explains, please refer to Fig. 2, the generalized section of the contact pad protection structure that Fig. 2 is the preferred embodiments of the present invention, it is drawn along AA ' tangent line in Fig. 1.As shown in Figure 2, on the semiconductor base 106 of tube core 50, be provided with dielectric layer 112 and contact pad 104.The material of dielectric layer 112 can be silica (SiO
2), tetraethoxysilane (TEOS), plasma enhanced tetraethoxysilane (PETEOS) or various interlayer dielectric layer material.The contact pad 104 being arranged in dielectric layer 112 can comprise various conductive materials, such as tungsten, aluminium or copper etc.In addition, contact pad 104 comprises join domain 108 and neighboring area 110, join domain 108 is defined as the region that contact pad 104 is exposed, therefore the contact pad 104 being positioned at herein can come out, required in order to follow-up various packaging technology wiring, solder joint, neighboring area 110 surrounds join domain 108, please also refer to the illustration of Fig. 1.
As previously mentioned, during in order to ensure etching, etchant 122 can not corrode the dielectric layer 112 of neighboring area 110, and then infiltrates and destroy the element of 102 inside, non-micro electronmechanical region, and this preferred embodiment is all designed with protection structure in each contact pad 104.This protection structure comprises at least one barricade 116, insulating barrier 118 and mask layer 120.As shown in Figure 2, after completing the technique of contact pad 104, such as techniques such as can utilizing path connector (via plug), make required barricade 116, barricade 116 is arranged in the dielectric layer 112 on neighboring area 110, and surrounds join domain 108; 118 of insulating barriers are arranged on dielectric layer 112 and barricade 116.
Barricade 116 is continuous circulus, and its material can comprise the etched material of etchant 122 that tungsten, metallic aluminium, non-crystalline silicon (amorphous silicon) or silicon nitride (silicon nitride) or other can anti-hydrofluoric acid (HF) etc.Barricade 116, with regard to the plane figure structure of Fig. 1, has surrounded join domain 108, and has exposed the join domain 108 of contact pad 104; And with regard to the illustrative vertical stratification of Fig. 2; barricade 116 is essence contact insulation layer 118 upwards, to next essence contact contact pad 104, thus; can form protection structure complete and sealing, effectively prevent that thus etchant 122 from infiltrating in non-micro electronmechanical region 102 from contact pad 104 peripheries.It can have single barricade 116 the protection structure of the present embodiment, or optionally has a plurality of barricades 116, is set parallel to each other between insulating barrier 118 and contact pad 104 and jointly around join domain 108.The plane figure of barricade 116 can be the enclosed constructions such as various polygons, circle, please refer to Fig. 3, the embodiment schematic diagram of the plane figure that Fig. 3 is barricade of the present invention.As shown in Figure 3, barricade 116 is polygon, preferred person, and this polygon has the interior angle that is about 130 degree.
The material of insulating barrier 118 comprises non-crystalline silicon or silicon nitride, and depending on product demand, the material of insulating barrier 118 and barricade 116 can be identical, for example, be similarly non-crystalline silicon, but also can be different, and for example insulating barrier 118 is non-crystalline silicon, and barricade 116 is tungsten.Insulating barrier 118 is covered on barricade 116 and contacts barricade 116, and it can have the shape of patterning, for example, be the circulus corresponding with barricade 116 layout patterns, and and barricade 116 jointly around join domain 108.In another embodiment of the present invention, insulating barrier 118 can also be for cover the layer structure in non-micro electronmechanical region 102 comprehensively, as shown in Figure 4, itself and mask layer 120 have identical topology pattern can same Patternized technique etching and obtain, therefore insulating barrier 118 is not only covered in neighboring area 110, also can cover other regions in addition, neighboring area 110, but take, expose join domain 108 as principle.
Refer again to Fig. 2, Fig. 4, mask layer 120 has opening 123 to expose the join domain 108 of contact pad 104, it is to cover the layer structure in non-micro electronmechanical region 102 comprehensively, it is covered on dielectric layer 112 and insulating barrier 118, and etchant 122 is had to high resistance to corrosion ability, with the surface of guaranteeing whole non-micro electronmechanical region 102 can etched dose 122 corroded.For example, when etchant 122 is hydrofluoric acid (HF), the material of mask layer 120 can comprise the metal of aluminium etc.Therefore owing to thering is insulating barrier 118 below mask layer 120, can avoid mask layer 120 to be directly electrically connected and generation short circuit phenomenon with contact pad 104.
Please refer to Fig. 5 figure, Fig. 5 is another preferred embodiment schematic diagram of contact pad protection structure of the present invention.As shown in Figure 5, for reinforced insulation effect, bottom 124 also can be set up in insulating barrier 118 belows, and it is positioned at the bottom of insulating barrier 118, contacts dielectric layer 112 and barricade 116, as shown in Figure 5 simultaneously; Or bottom 124 is positioned at the top of insulating barrier 118, and contact mask layer 120.The material of bottom 124 comprises silicon nitride (SiN), nitrogen-oxygen-silicon compound (silicon oxynitride), hafnium silicon oxynitride (HfSiON), zirconium dioxide (ZrO
2) or hafnium oxide (HfO
2) or other high-dielectric coefficients (high-k dielectric) material.Also or when insulating barrier 118 is non-crystalline silicon, can when it forms, add gradually the reacting gas such as oxygen, to form the insulating barrier 118 of graded bedding, its anti-etching ability in bottom is stronger, and top insulation effect is preferred.
Please refer to Fig. 6, Fig. 6 is the another preferred embodiment schematic diagram of contact pad protection structure of the present invention.As shown in Figure 6; contact pad protection structure of the present invention, also alternative comprises adhesion coating 126, is arranged between insulating barrier 118 and dielectric layer 112; or be arranged between insulating barrier 118 and mask layer 120, or all arrange between insulating barrier 118, dielectric layer 112 and mask layer 120.The material of adhesion coating 126 can comprise Titanium or titanium nitride (Ti/TiN).Therefore it should be noted that the material due to adhesion coating 126 can conduct electricity, if while being arranged between insulating barrier 118 and barricade 116, need avoid adhesion coating 126 to touch mask layer 120 and barricade 116 and the phenomenon of generation short circuit simultaneously.
As previously mentioned, the present invention forms protection structure on can be applicable to each contact pad, can also between micro electronmechanical region and non-micro electronmechanical region, form protection structure.Please refer to Fig. 7, Fig. 7 is the generalized section of the protection structure between micro electronmechanical region and non-micro electronmechanical region in the present invention, and its tangent line BB ' along Fig. 1 draws.As shown in Figure 7, have micro electronmechanical region 100 and non-micro electronmechanical region 102 on semiconductor base 106, protection structural region 101 is arranged between micro electronmechanical region 100 and non-micro electronmechanical region 102.Dielectric layer 112 is arranged on semiconductor base 106; special; dielectric layer 112 can be arranged in protection structural region 101 and non-micro electronmechanical region 102; and dielectric layer in micro electronmechanical region 100 112 can remove for etched dose 122, various movable or there is the mechanical organ (not shown) of space micro-structural to form.
For fear of etchant 122, infiltrate in non-micro electronmechanical region 102, the present invention is provided with protection structure at 101 of structural regions of protection.This protection structure comprises insulating barrier 118, at least one the first barricade 134, top metal level 130, multiple layer metal layer 128 and a plurality of the second barricade 132.Multiple layer metal layer 128 is arranged in dielectric layer 112 with a plurality of the second barricades 132, and each metal level 128 is connected up and down with each second barricade 132, its contact top, top metal level 130, and bottom is contact semiconductor substrate 106.On multiple layer metal layer 128 and a plurality of the second barricades 132, be relatively set with top metal level 130.The material of multiple layer metal layer 130, a plurality of the second barricade 132 and top metal level 130 comprises metallic aluminium, tungsten, metallic copper or various metal that can anti-hydrofluoric acid etch, and follows metal interconnecting technique to be formed in protection structural region 101.Metal level 130 tops in top are provided with the first barricade 134 and insulating barrier 118.The material of the first barricade 134 comprises tungsten, metallic aluminium, non-crystalline silicon or silicon nitride or other can anti-etching dose of 122 etched materials.It can have the first barricade 134 of simple layer protection structure of the present invention, or optionally has a plurality of the first barricades 134, be arranged in parallel each other.The material of insulating barrier 118 comprises non-crystalline silicon or silicon nitride, depending on the demand on various technique or product, the material of insulating barrier 118 and the first barricade 134 can be similarly non-crystalline silicon, but also can be different, for example insulating barrier 118 is non-crystalline silicon, and the first barricade 134 is tungsten.In addition; mask layer 120 is for be covered in the layer structure of non-micro electronmechanical region 102 and protection structural region 101 comprehensively; it is covered on dielectric layer 112 and insulating barrier 118, to guarantee that the surface in whole non-micro electronmechanical region 102 can etched dose of 122 etchings.
Same, protection structure of the present invention can also comprise adhesion coating 126; Or, also can comprise bottom 124, it implements aspect as mentioned before, at this, is seldom repeated in this description.
As shown in Figure 7; protection structure of the present invention is between micro electronmechanical region 100 and non-micro electronmechanical region 102; its multiple layer metal layer 128, a plurality of the second barricade 132, top metal level 130, the first barricade 134 and insulating barrier 118 have formed complete anti-etching structure by upper from lower, so can effectively prevent that etching gas 122 from infiltrating non-micro electronmechanical regions 102 from micro electronmechanical region 100.In addition, protection structure of the present invention is between micro electronmechanical region 100 and non-micro electronmechanical region 102, and its embodiment can be linear structure as the protection structural region 101 of Fig. 1, and it is across between micro electronmechanical region 100 and non-micro electronmechanical region 102.Or as shown in Figure 8, around whole micro electronmechanical region 100, and form the protection structure of sealing, otherwise or, be centered around whole non-micro electronmechanical region 102.In this embodiment, the first barricade 134 can be for forming closed polygon, preferred person, and this polygon has the interior angle that is about 130 degree, as shown in Figure 4.
In sum; the present invention proposes a kind of protection structure; be useful in general semi-conductive contact pad or MEMS; the protection structure of its sealing can effectively be avoided for example erosion of hydrofluoric acid of etchant; can protect the element in non-micro electronmechanical region can be not destroyed, can improve product yield and reliability.
The foregoing is only the preferred embodiments of the present invention, all equivalent variations of doing according to the claims in the present invention and modification, all should belong to covering scope of the present invention.
Claims (20)
1. a protection structure for contact pad, is characterized in that:
This contact pad is arranged in the dielectric layer on semiconductor base and this contact pad comprises join domain and the neighboring area that is surrounded on this join domain, and this protection structure comprises:
At least one barricade, is arranged in this dielectric layer on this neighboring area, and wherein this barricade surrounds this join domain;
Insulating barrier, is arranged on this dielectric layer, and this barricade contacts this insulating barrier and this contact pad up and down; And
Mask layer, is arranged on this dielectric layer and covers this insulating barrier, and this mask layer has opening to expose this join domain of this contact pad.
2. the protection structure of contact pad as claimed in claim 1, wherein this barricade comprises tungsten, aluminium, non-crystalline silicon or silicon nitride.
3. the protection structure of contact pad as claimed in claim 1, wherein this insulating barrier comprises non-crystalline silicon or silicon nitride.
4. the protection structure of contact pad as claimed in claim 1, separately comprises bottom, is located at this insulating barrier bottom.
5. the protection structure of contact pad as claimed in claim 4, wherein this bottom comprises silicon nitride, carborundum, tetraethoxysilane, non-doped silicon glass, phosphorosilicate glass or boron-phosphorosilicate glass.
6. the protection structure of contact pad as claimed in claim 1, wherein this mask layer comprises metal.
7. the protection structure of contact pad as claimed in claim 1, also comprises adhesion coating, is arranged between this insulating barrier and this mask layer.
8. the protection structure of contact pad as claimed in claim 7, wherein this adhesion coating comprises Titanium or titanium nitride.
9. the protection structure of contact pad as claimed in claim 1, also comprises adhesion coating, is arranged between this insulating barrier and this dielectric layer.
10. the protection structure of contact pad as claimed in claim 9, wherein this adhesion coating comprises Titanium or titanium nitride.
11. 1 kinds of semiconductor structures, is characterized in that:
Comprise:
Semiconductor base, comprises micro electronmechanical region and non-micro electronmechanical region;
Dielectric layer, arranges on this semiconductor base;
Protection structure, be located between this micro electronmechanical region and this non-micro electronmechanical region, and this protection structure comprises:
Top metal level, is arranged in this dielectric layer;
At least one the first barricade, is arranged in this dielectric layer on this top metal level; And
Insulating barrier, is arranged on this dielectric layer, and this first barricade contacts this insulating barrier and this top metal level up and down; And
Mask layer, is arranged on this dielectric layer and covers this insulating barrier.
12. as the semiconductor structure of claim 11, and wherein this protection structure also comprises multiple layer metal layer and a plurality of the second barricade, is connected up and down, is arranged between this top metal level and this semiconductor base.
13. as claim 11 semiconductor structure, and wherein this first barricade comprises tungsten, aluminium, non-crystalline silicon or silicon nitride.
14. as the semiconductor structure of claim 11, and wherein this insulating barrier comprises non-crystalline silicon or silicon nitride.
15. as the semiconductor structure of claim 11, separately comprises bottom, is located at this insulating barrier bottom.
16. as the semiconductor structure of claim 11, and wherein this mask layer comprises metal.
17. as the semiconductor structure of claim 11, also comprises adhesion coating, is arranged between this insulating barrier and this mask layer.
18. as the semiconductor structure of claim 17, and wherein this adhesion coating comprises Titanium or titanium nitride.
19. as the semiconductor structure of claim 11, also comprises adhesion coating, is arranged between this insulating barrier and this dielectric layer.
20. as the semiconductor structure of claim 19, and wherein this adhesion coating comprises Titanium or titanium nitride.
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| CN200910165776.8A CN101993031B (en) | 2009-08-13 | 2009-08-13 | Protection structure and semiconductor structure of contact pad |
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| CN200910165776.8A CN101993031B (en) | 2009-08-13 | 2009-08-13 | Protection structure and semiconductor structure of contact pad |
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| CN101993031B true CN101993031B (en) | 2014-04-09 |
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| CN1494106A (en) * | 2002-08-09 | 2004-05-05 | Pts公司 | Method and device used for protecting wiring and integrated circuit device |
| EP1405821A2 (en) * | 2002-10-04 | 2004-04-07 | Dalsa Semiconductor Inc. | Wafer level packaging technique for microdevices |
| CN1893070A (en) * | 2005-07-01 | 2007-01-10 | 株式会社东芝 | Semiconductor device advantageous in improving water resistance and oxidation resistance |
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