CN101986569A - Digital costas loop - Google Patents
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- CN101986569A CN101986569A CN 201010523680 CN201010523680A CN101986569A CN 101986569 A CN101986569 A CN 101986569A CN 201010523680 CN201010523680 CN 201010523680 CN 201010523680 A CN201010523680 A CN 201010523680A CN 101986569 A CN101986569 A CN 101986569A
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Abstract
The invention discloses a digital COSTAS loop. The digital COSTAS loop comprises a first phase discriminator, a second phase discriminator, a signal phase-shift module, a voltage controlled oscillator and a loop filter, wherein the output ends of the first phase discriminator and the second phase discriminator are coupled with the input end of the loop filter through a first multiplier, the output end of the loop filter is coupled with the input end of the voltage controlled oscillator, the output end of the voltage controlled oscillator is coupled with the input end of the first phase discriminator through a seocnd multiplier, the output end of the voltage controlled oscillator is also coupled with the input end of the signal phase-shift module, the output end of the signal phase-shift module is coupled with the input end of the second phase discriminator through a third multiplier; and the loop filter contains a PID controller. The digital COSTAS loop has simplified structure, and can demodulate the carrier signal stably and fast.
Description
Technical field
The present invention relates to a kind of phase-locked loop, relate in particular to a kind of digital COSTAS ring, belong to the modulating and demodulating signal field.
Background technology
When receiver carries out coherent demodulation, need to recover and the synchronous local carrier of transmission modulated carrier same frequency.The carrier component that contains in the vestigial sideband modulation signal for ordinary amplitude modulation broadcast singal, radiovision emission, adopt phase-locked loop directly to lock the work that carrier component in the received signal can be finished the reinsertion of carrier, but in a lot of the application, in order to improve the power efficiency of transmission, often adopt the modulation system of suppressed carrier to communicate transmission.At this moment, just must carry out the higher harmonic components of Nonlinear Processing to receiving modulation signal with the acquisition carrier wave, and with this harmonic component of pll lock, again by the frequency divider frequency division reinsertion of carrier.And for the suppressed-carrier double side band modulation, adopt quadratic loop or COSTAS to encircle usually and extract carrier wave.
Numeral section's Stas (COSTAS) ring is usually used in extracting carrier wave in relevant adjusting of 2PSK (also claiming BPSK) in microwave communication and satellite communication.COSTAS ring has two branch roads, and one is branch road in the same way, and another is a quadrature branch, so COSTAS encircles and is called again in the same way-orthogonal loop.Controlled voltage behind the output multiplication of its two branch road, the frequency of control voltage controlled oscillator (voltage-controlled oscillator is called for short VCO).When system is in synchronous regime, VCO is output as the reinsertion of carrier, the data of branch road output are the demodulation output of 2PSK in the same way, if θ is the phase difference between VCO output voltage and the reception 2PSK signal carrier, resulting control voltage v (θ) is directly proportional with phase error theta behind loop filter (low-pass filtering), it is equivalent to the output of phase discriminator, goes to control the frequency of VCO with this control voltage.Wherein, loop filter plays the mean effort to input signal.Also promptly, the design of whole phase-locked loop should make that the steady state phase error θ of phase-locked loop is very little, and at this moment, the output of VCO is exactly the carrier wave of required extraction.The advantage of COSTAS ring is that the loop operating frequency is a carrier frequency, well below the operating frequency of quadratic loop, realizes that cost is lower.
Although digital COSTAS ring in use constantly is improved, the structure of existing digital COSTAS ring is still simplified inadequately, and the speed of the stability of the carrier signal of its output and response still can not better meet demand.
Summary of the invention
The technical problem to be solved in the present invention is that existing digital COSTAS ring structure is simplified inadequately, and the speed of the stability of the carrier signal of its output and response can not better meet the problem of demand.
For solving the problems of the technologies described above, the invention provides a kind of digital COSTAS ring, it comprises first phase discriminator, second phase discriminator, the signal phase shift block, voltage controlled oscillator, loop filter, the output of described first phase discriminator and second phase discriminator is coupled to the input of described loop filter by one first multiplier, the output of described loop filter is coupled to the input of described voltage controlled oscillator, the output of described voltage controlled oscillator is coupled to the input of described first phase discriminator by one second multiplier, the output of described voltage controlled oscillator also is coupled to the input of described signal phase shift block, the output of described signal phase shift block is coupled to the input of described second phase discriminator by one the 3rd multiplier, wherein, described loop filter comprises the PID controller.
Digital COSTAS ring provided by the invention is by merging PID controller (proportional plus integral plus derivative controller) in the loop filtering circuit, not only structure is simplified, and can stablize, demodulate carrier signal fast, also, the output initialize signal not have to shake and the delay of signal very little.
According to a kind of preferred implementation of above-mentioned digital COSTAS ring, wherein, described loop filter is a PID controller.
According to a kind of preferred implementation of above-mentioned digital COSTAS ring, wherein, the voltage-controlled low-pass filter circuit of proportional integral that described PID controller is a second order.
According to a kind of preferred implementation of above-mentioned digital COSTAS ring, wherein, described PID controller is for opening and closing the loop self-adaptive structure.
A kind of preferred implementation according to above-mentioned digital COSTAS ring, wherein, described PID controller comprises: one first resistance is connected in the positive input of an operational amplifier by one second resistance, the positive input of this operational amplifier also is connected in ground by one first electric capacity, the reverse input end of this operational amplifier respectively by one the 3rd resistance and the 4th resistance be connected in its output, be connected with one second electric capacity between the node of the output of this operational amplifier and this first resistance and second resistance.
According to a kind of preferred implementation of above-mentioned digital COSTAS ring, wherein, described first phase discriminator is identical with the second phase discriminator structure.
A kind of preferred implementation according to above-mentioned digital COSTAS ring, wherein, described first phase discriminator or second phase discriminator comprise: one first resistance, one second resistance is connected successively with one the 3rd resistance and is connected with the positive input of one first operational amplifier, the output of this first operational amplifier is by one the 4th resistance and one the 5th resistance positive input that is connected in one second operational amplifier of series connection, the node of this first resistance and second resistance is connected in ground by one first electric capacity, the node of this second resistance and the 3rd resistance is connected in the positive input and the output of this first operational amplifier simultaneously by one second electric capacity, the positive input of this first operational amplifier is connected in ground by one the 3rd electric capacity, the node of the 4th resistance and the 5th resistance is connected in the reverse input end and the output of this second operational amplifier by one the 4th electric capacity, and the positive input of this second operational amplifier is connected in ground by one the 5th electric capacity.
A kind of preferred implementation according to above-mentioned digital COSTAS ring, wherein, described signal phase shift block comprises: the source electrode of one first field effect transistor is connected in an end of one first resistance simultaneously, the one first variable-resistance convertible tip and first stiff end, this first variable-resistance second stiff end is connected in the grid of one second field effect transistor, the drain electrode of this first field effect transistor is connected in the grid of described second field effect transistor by one first electric capacity, the source electrode of described second field effect transistor is connected in an end of one second resistance simultaneously, the convertible tip of one the second adjustable resistance and first stiff end, second stiff end of this second adjustable resistance is connected in the grid of one the 3rd field effect transistor, the drain electrode of this second field effect transistor is connected in the grid of described the 3rd field effect transistor by one second electric capacity, the drain electrode of this first field effect transistor is connected in an end of one the 3rd resistance, an end that is connected in one the 4th resistance of the drain electrode of this second field effect transistor, the other end of the 3rd resistance, the drain electrode of the other end of the 4th resistance and the 3rd field effect is connected simultaneously with an end of one the 5th resistance, the other end of the 5th resistance is connected in the grid of this first field effect transistor, the grid of this first field effect transistor also is connected in an end of one the 6th resistance, and the other end of the 6th resistance is connected in the other end of the other end of this first resistance and this second resistance simultaneously and is connected in the source electrode of the 3rd field effect transistor by one the 7th resistance.
According to a kind of preferred implementation of above-mentioned digital COSTAS ring, wherein, described first field effect transistor, second field effect transistor and the 3rd field effect transistor are metal oxide semiconductor field effect tube.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the principle structure schematic diagram of the preferred embodiment of the present invention.
Embodiment
Below in conjunction with accompanying drawing of the present invention, technical scheme of the present invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that is obtained under the creative work prerequisite.
Simplify inadequately in order to solve the existing digital COSTAS ring structure of prior art, and the speed of the stability of the carrier signal of its output and response can not better meet the problem of demand, the invention provides a kind of digital COSTAS ring.
Need to prove that at first in Fig. 1, only as the usefulness that schematically shows each circuit module of the preferred embodiment of the present invention, it does not do any qualification to the practical structures of this preferred embodiment to dotted line.
As shown in Figure 1, the preferred embodiment of the present invention provided by the invention comprises two phase discriminators 1 and 2, signal phase shift block 5, voltage controlled oscillator 4, loop filter 3, phase discriminator 1,2 output is coupled to the input of loop filter 3 by multiplier M3, the output of loop filter 3 is coupled to the input of voltage controlled oscillator 4, the output of voltage controlled oscillator 4 is coupled to the input of phase discriminator 1 by multiplier M1, the output of voltage controlled oscillator 4 also is coupled to the input of signal phase shift block 5 with frequency division and phase shift, the output of signal phase shift block 5 is coupled to the input of phase discriminator 2 by multiplier M2, wherein, loop filter 3 is a switching loop self-adaptive structure PID control device.
This preferred embodiment adopts the PID controller to realize the loop filtering function.In as loop filter 3, if P (ratio) control is only arranged, steady-state error can appear in system; Adding I (integration) control can make system stability steady-state error can not occur later on; The D derivative controller then has the function of " prediction is following ", therefore with the PID controller as loop filter, and set P, I, three parameter values of D according to the system requirements of this preferred embodiment, can be so that this preferred embodiment realizes that system responds fast, and reach steady-state value.In addition, also have simple in structure, reliable operation, good stability, modulate advantage easily.
As shown in Figure 1, the PID controller of this preferred embodiment is the voltage-controlled low-pass filter circuit of proportional integral of second order, wherein, one end of resistance R 31 is connected in the positive input of operational amplifier A 31 by resistance R 33, the positive input of operational amplifier A 31 also is connected in ground by capacitor C 32, the reverse input end of operational amplifier A 31 also respectively by resistance R 32 and resistance R 34 be connected in its output, be connected with capacitor C 31 between the node of the positive input of operational amplifier A 31 and resistance R 31 and resistance R 33, so, the other end of resistance R 31, the output of operational amplifier A 31 just is respectively the input and the output of loop filter 3 (being the PID controller).The parameter value of PID controller shown in Figure 1 can calculate by following general formula (1), (2):
The relation of formula (1) expression frequency f and resistance R, capacitor C; In the formula (2): u
I, u
OThe input of PID controller, the output voltage values of representing this preferred embodiment respectively;
Be proportionality coefficient,
Be integral coefficient, R
32C
32Be differential coefficient, shown in (1), (2) formula, with R
32Zero setting has then obtained the proportional integral computing circuit, or with C
31Zero setting has then obtained proportional plus derivative controller.
In this preferred embodiment, phase discriminator 1 is identical with phase discriminator 2 structures, and as shown in Figure 1, for simplifying accompanying drawing, the Reference numeral of two phase discriminators, 1,2 each parts is identical.One of two phase discriminators comprise: resistance R 11, resistance R 12 is connected successively with resistance R 13 and then is connected with the positive input of operational amplifier A 11, the output of operational amplifier A 11 is by the resistance R 14 and resistance R 15 positive input that is connected in operational amplifier A 12 of series connection, the node of resistance R 11 and resistance R 12 is connected in ground by capacitor C 11, the node of resistance R 12 and resistance R 13 is connected in the positive input and the output of operational amplifier A 11 simultaneously by capacitor C 12, the positive input of operational amplifier A 11 is connected in ground by capacitor C 13, the node of resistance R 14 and resistance R 15 is connected in the reverse input end and the output of operational amplifier A 12 by capacitor C 14, the positive input of operational amplifier A 12 is connected in ground by capacitor C 15, the end that resistance R 11 is connected with multiplier M1, the output of operational amplifier A 12 is the input and the output of phase discriminator.
Two phase discriminators 1,2 are made up of analogue multiplier and two parts of low pass filter, the improved realization that focuses on low pass filter of the phase discriminator of this preferred embodiment, low pass filter must be by the frequency of carrier signal, because the frequency of baseband signal and carrier signal differs many times, therefore should not be used as the low pass filter of this preferred embodiment with band pass filter.The low pass filter of this preferred embodiment is the single order active low-pass filter, it adopts the output at low-pass first order filter to add a voltage follower, this follower makes the whole filtering networking can be along with the size variation of output resistance, and therefore the frequency characteristic of the filter network that obtains is fixed.
This preferred embodiment also improves for the signal phase shift block of prior art, the signal phase shift block of this preferred embodiment has adopted metal oxide semiconductor field effect tube (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) realize 90 degree phase shifts, promptly the field effect transistor of the signal phase shift block of this preferred embodiment is MOSFET.Wherein, the source electrode of field effect transistor Q1 is connected in an end of resistance R 51, the convertible tip and first stiff end of variable resistor R52 simultaneously, second stiff end of variable resistor R52 is connected in the grid of field effect transistor Q2, and the drain electrode of field effect transistor Q1 is connected in the grid of field effect transistor Q2 by capacitor C 51.The source electrode of field effect transistor Q2 is connected in an end of resistance R 53, the convertible tip and first stiff end of variable resistor R54 simultaneously, second stiff end of variable resistor R53 is connected in the grid of field effect transistor Q3, and the drain electrode of field effect transistor Q2 is connected in the grid of field effect transistor Q3 by capacitor C 52.The drain electrode of field effect transistor Q1 is connected in an end of resistance R 56, an end that is connected in resistance R 59 of the drain electrode of field effect transistor Q2.The drain electrode of the other end of the other end of resistance R 56, resistance R 59 and field effect Q3 is connected simultaneously with an end of resistance R 56, and this node is connected in circuit power VCC.The other end of resistance R 56 is connected in the grid of field effect transistor Q1, the grid of field effect transistor Q1 also is connected in an end of resistance R 57, the other end of resistance R 57 is connected in the other end of the other end of resistance R 51 and resistance R 53 simultaneously and is connected in the source electrode of field effect transistor Q3 by resistance R 55, the node of field effect transistor Q3 and resistance R 55 is the output of this signal phase shift block 5, and the node of resistance R 56 and resistance R 57 is the input of this signal phase shift block 5.
The essence of voltage controlled oscillator 4 is " voltage-frequency " converting means, and conduct is by controlled oscillator in this preferred embodiment, and its frequency of oscillation is with the variation of input control voltage linearity.So voltage controlled oscillator 4 comes down to a frequency-modulated generator with Linear Control characteristic.This preferred embodiment can adopt the sinusoidal wave voltage controlled oscillator of variable capacitance diode+LC bikini, realizes the voltage control sinewave output.
In order to test the beneficial effect of this preferred embodiment, Fig. 1 also shows signal generator 6, zero-crossing comparator 7 and oscilloscope 6,9.Signal generator 6 can be exported for example baseband signal of 200Hz and the carrier signal of 2000Hz, and when test, baseband signal can be square-wave signal, and carrier signal can be sine wave signal.For the validity of this preferred embodiment is described, but be without loss of generality, square-wave signal can not adopt binary signal at random, but adopts the square-wave signal of fixed duty cycle.The output of signal generator 6 is coupled to multiplier M1 and M2 simultaneously.
In brief, zero-crossing comparator 7 is that signal is become " 1 " greater than zero part; Minus part becomes " 0 ", in Fig. 1, it can have been become " 1 ".As shown in Figure 1; only realized zero balancing, do not add overload protection with an integrated transporting discharging, this be because of the amplitude of selected signal in circuit simulation and current value all compare little; there is no need in the emulation, but the essential overload protecting circuit that adds of side circuit.
Oscilloscope 6,9 is mainly used in the waveform that shows the circuit node that the two coupled, and in addition, signal generator 6 also comprises an oscilloscope 61, because Fig. 1 has clearly shown the position that couples of above-mentioned three oscilloscopes 6,9, therefore repeats no more.
Three parameters (proportionality coefficient P, integral coefficient I, differential coefficient D) of the PID of preferred embodiment shown in Figure 1 control can be calculated according to the parameter of frequency, collection period and the circuit elements device of signal etc., perhaps are aided with experiment and determine.Above-mentioned three parameters also can obtain with the method for machine learning such as artificial neural net.
Though Fig. 1 and above description have clearly shown structure of the present invention; it will be appreciated by those skilled in the art that the present invention does not limit to above execution mode; for example can also being transformed into other loop filterings, to adopt proportionality coefficient P, integral coefficient I, differential coefficient D be PID (as increment type PID, linear PID, dynamic PID, the fuzzy etc.) controller of algorithm pattern and version; no matter be conventional pattern, intellectual or self-adapting type; so long as the loop filtering circuit of digital COSTAS ring adopts the PID controller, all should belong to protection scope of the present invention.
In sum, by merging the PID controller in the loop filtering link, introduce parameter adaptive proportional plus integral plus derivative controller and realize loop filtering, rather than adopt the loop filtering algorithm of existing phase-locked loop, perhaps as first-order phase-locked loop, directly save, digital COSTAS ring provided by the invention has improved the carrier wave demodulation recovery capability, with respect to existing C OSTAS ring, have response speed fast, stablize, do not have initial oscillator signal, can not produce the advantage of disturbing signal.
The above; only be the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; can expect easily changing or replacing, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion by described protection range with claim.
Claims (9)
1. a digital COSTAS encircles, comprise first phase discriminator, second phase discriminator, the signal phase shift block, voltage controlled oscillator, loop filter, the output of described first phase discriminator and second phase discriminator is coupled to the input of described loop filter by one first multiplier, the output of described loop filter is coupled to the input of described voltage controlled oscillator, the output of described voltage controlled oscillator is coupled to the input of described first phase discriminator by one second multiplier, the output of described voltage controlled oscillator also is coupled to the input of described signal phase shift block, the output of described signal phase shift block is coupled to the input of described second phase discriminator by one the 3rd multiplier, it is characterized in that described loop filter comprises the PID controller.
2. digital COSTAS ring according to claim 1 is characterized in that described loop filter is a PID controller.
3. digital COSTAS ring according to claim 1 is characterized in that the voltage-controlled low-pass filter circuit of proportional integral that described PID controller is a second order.
4. digital COSTAS ring according to claim 1 is characterized in that described PID controller is for opening and closing the loop self-adaptive structure.
5. digital COSTAS ring according to claim 1, it is characterized in that, described PID controller comprises: one first resistance is connected in the positive input of an operational amplifier by one second resistance, the positive input of this operational amplifier also is connected in ground by one first electric capacity, the reverse input end of this operational amplifier respectively by one the 3rd resistance and the 4th resistance be connected in its output, be connected with one second electric capacity between the node of the output of this operational amplifier and this first resistance and second resistance.
6. digital COSTAS ring according to claim 1 is characterized in that described first phase discriminator is identical with the second phase discriminator structure.
7. digital COSTAS ring according to claim 6, it is characterized in that, described first phase discriminator or second phase discriminator comprise: one first resistance, one second resistance is connected successively with one the 3rd resistance and is connected with the positive input of one first operational amplifier, the output of this first operational amplifier is by one the 4th resistance and one the 5th resistance positive input that is connected in one second operational amplifier of series connection, the node of this first resistance and second resistance is connected in ground by one first electric capacity, the node of this second resistance and the 3rd resistance is connected in the positive input and the output of this first operational amplifier simultaneously by one second electric capacity, the positive input of this first operational amplifier is connected in ground by one the 3rd electric capacity, the node of the 4th resistance and the 5th resistance is connected in the reverse input end and the output of this second operational amplifier by one the 4th electric capacity, and the positive input of this second operational amplifier is connected in ground by one the 5th electric capacity.
8. digital COSTAS ring according to claim 1, it is characterized in that, described signal phase shift block comprises: the source electrode of one first field effect transistor is connected in an end of one first resistance simultaneously, the one first variable-resistance convertible tip and first stiff end, this first variable-resistance second stiff end is connected in the grid of one second field effect transistor, the drain electrode of this first field effect transistor is connected in the grid of described second field effect transistor by one first electric capacity, the source electrode of described second field effect transistor is connected in an end of one second resistance simultaneously, the convertible tip of one the second adjustable resistance and first stiff end, second stiff end of this second adjustable resistance is connected in the grid of one the 3rd field effect transistor, the drain electrode of this second field effect transistor is connected in the grid of described the 3rd field effect transistor by one second electric capacity, the drain electrode of this first field effect transistor is connected in an end of one the 3rd resistance, an end that is connected in one the 4th resistance of the drain electrode of this second field effect transistor, the other end of the 3rd resistance, the drain electrode of the other end of the 4th resistance and the 3rd field effect is connected simultaneously with an end of one the 5th resistance, the other end of the 5th resistance is connected in the grid of this first field effect transistor, the grid of this first field effect transistor also is connected in an end of one the 6th resistance, and the other end of the 6th resistance is connected in the other end of the other end of this first resistance and this second resistance simultaneously and is connected in the source electrode of the 3rd field effect transistor by one the 7th resistance.
9. digital COSTAS ring according to claim 8 is characterized in that described first field effect transistor, second field effect transistor and the 3rd field effect transistor are metal oxide semiconductor field effect tube.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9967086B2 (en) | 2016-07-01 | 2018-05-08 | Mstar Semiconductor, Inc. | Frequency modulation receiver and frequency modulation receiving method |
| CN112362963A (en) * | 2020-10-15 | 2021-02-12 | 中国科学院上海天文台 | Doppler frequency measurement method based on improved phase-locked loop |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1705234A (en) * | 2004-05-26 | 2005-12-07 | 华为技术有限公司 | Clock synthesizing method and system |
| CN201846333U (en) * | 2010-10-25 | 2011-05-25 | 北京科技大学 | Digital costas loop |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1705234A (en) * | 2004-05-26 | 2005-12-07 | 华为技术有限公司 | Clock synthesizing method and system |
| CN201846333U (en) * | 2010-10-25 | 2011-05-25 | 北京科技大学 | Digital costas loop |
Non-Patent Citations (1)
| Title |
|---|
| 《武汉理工大学学报（交通科学与工程版）》 20100831 封小钰、鄢文飞、刘必刚 数字Costas环在FPGA中的实现 第34卷, 第4期 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9967086B2 (en) | 2016-07-01 | 2018-05-08 | Mstar Semiconductor, Inc. | Frequency modulation receiver and frequency modulation receiving method |
| CN112362963A (en) * | 2020-10-15 | 2021-02-12 | 中国科学院上海天文台 | Doppler frequency measurement method based on improved phase-locked loop |
| CN112362963B (en) * | 2020-10-15 | 2023-07-14 | 中国科学院上海天文台 | Doppler frequency measurement method based on improved phase-locked loop |
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