CN101958537A

CN101958537A - High-voltage ESD (Electronic Static Discharge) protection circuit

Info

Publication number: CN101958537A
Application number: CN2009100550513A
Authority: CN
Inventors: 肖国庆; 李茂登
Original assignee: SHANGHAI SANDHILL MICROELECTRONICS CO Ltd
Current assignee: SHANGHAI SANDHILL MICROELECTRONICS CO Ltd
Priority date: 2009-07-17
Filing date: 2009-07-17
Publication date: 2011-01-26

Abstract

The invention relates to a high-voltage ESD (Electronic Static Discharge) protection circuit which comprises a power supply port, an NMOS (N-channel Metal Oxide Semiconductor) discharge tube, an ESD detection resistor and a pull-down resistor, and a drain of the NMOS discharge tube is connected with the power supply port and the ESD detection resistor. The high-voltage ESD protection circuit is characterized in that the drain and a grid of the NMOS discharge tube are respectively connected with a drain and a source of an NMOS pull-up tube, and a grid of the NMOS pull-up tube is earthed after being connected with the pull-down resistor. Compared with the traditional ESD protection circuit, the NMOS pull-up tube is introduced as the pull-up tube in place of a detection capacitor Ca, parasitic capacitors Cgd and Cgs of the NMOS pull-up tube per se are used for conducting the NMOS discharge tube, and the purpose of ESD protection is realized.

Description

The high pressure esd protection circuit

[technical field]

The present invention relates to integrated circuit (IC) design, specifically, relevant with the high pressure esd protection circuit that adopts the trigger-type discharge in the integrated circuit.

[background technology]

The static of integrated circuit discharges (being called for short ESD) protective circuit many types; wherein a class is an ESD trigger-type discharge protection circuit; when promptly an esd detection circuit detected the ESD impact, this circuit discharged a signal and opens discharge tube, and discharge tube discharges the ESD electric current.

Fig. 1 is a kind of esd protection circuit commonly used, and NMOS1 is a discharge tube among the figure, and R1 is a pull down resistor; R2 is that ESD detects resistance, and Cgd (the grid leak interpolar of NMOS1) and Cgs (between the grid source electrode of NMOS1) are parasitic capacitance, and Ca is that ESD detects electric capacity; in low pressure process, this electric capacity can save.

When the ESD electric current impacted integrated circuit by the I/O power port, the voltage of node 1 (being the drain electrode line of NMOS1) can raise rapidly, and the voltage of node 2 (being the gate trace of NMOS1) will be by ratio and the decision of R1 resistance value of Cgd and Cgs.In low pressure process, Cgd value and Cgs value are more or less the same, and the voltage of node 2 reaches a high voltage opens NMOS1, and electric current flows to ground by NMOS1, and pull down resistor R1 pulls down the voltage of node 2 gradually, so NMOS1 closes; And in high-pressure process, NMOS1 adopts high-voltage discharge tube, the Cgd value is little more a lot of than the Cgs value, when the ESD rush of current, the voltage of node 2 is difficult to reach the higher voltage value, causes the NMOS1 conducting insufficient, can not fully bleed off the ESD electric current, need to add detection capacitor C a and improve node 2 voltages, thereby strengthen the ducting capacity of NMOS1.

Fig. 2 is another kind of esd protection circuit commonly used, and NMOS1 is the esd discharge pipe, and R1 is a pull down resistor, and Ca is that an ESD detects electric capacity, and R2 is that ESD detects resistance, and INV1 and INV2 are inverter.When the ESD electric current impacts integrated circuit by the I/O power port, the voltage of node 1 (being the drain electrode line of NMOS1) can raise rapidly, according to the electric capacity principle of can not suddenling change, the voltage of node 2 (being INV1 inverter input link) raises rapidly, reverse by INV1 and INV2, the voltage of node 3 (being INV2 inverter output line) also raises rapidly, and NMOS1 is opened like this, and electric current flows to ground by NMOS1.Pull down resistor R1 pulls down the voltage of node 2 gradually, when the voltage of node 2 is lower than certain voltage, and the voltage reversal of inverter INV1 and INV2, NMOS1 closes.

In these two kinds of circuit, the appearance value and the puncture voltage that detect capacitor C a should reach certain value, if puncture voltage is too low, when integrated circuit operate as normal or ESD bombardment, electric capacity may be breakdown; If the appearance value is too little, NMOS1 just can not open.But the capacity ratio that satisfies high-pressure process and prepare high-breakdown-voltage, high capacitance density is difficulty, and therefore under the input voltage situation of higher (voltage surpasses 7V), these two kinds of esd protection circuits all can not use.

[summary of the invention]

The present invention improves existing esd protection circuit, proposes a kind of high pressure esd protection circuit, can overcome the deficiency that present esd protection circuit exists, and is applied in the high-pressure process.

Technical scheme of the present invention is: a kind of high pressure esd protection circuit; comprise that power port, NMOS discharge tube, ESD detect resistance and pull down resistor; the drain electrode of NMOS discharge tube connects power port, ESD detects resistance; it is characterized in that: the drain electrode that NMOS goes up trombone slide and source electrode are connected the drain and gate of NMOS discharge tube respectively, and the grid that described NMOS goes up trombone slide connects ground connection behind the described pull down resistor.

Compare with existing esd protection circuit, the present invention introduces the NMOS pipe and substitutes detection capacitor C a as last trombone slide, utilizes NMOS upward the parasitic capacitance Cgd and the Cgs conducting NMOS discharge tube of trombone slide itself, realizes the purpose of esd protection.

[description of drawings]

The existing esd protection circuit structure of Fig. 1.

The another kind of existing esd protection circuit structure of Fig. 2.

The circuit structure of Fig. 3 embodiment of the invention one.

The circuit structure of Fig. 4 embodiment of the invention two.

[embodiment]

Be described further below in conjunction with embodiments of the invention and accompanying drawing thereof.

Consult Fig. 3, two kinds of high pressure esd protection circuits shown in Figure 4; comprise that power port 3, NMOS discharge tube 1, ESD detect resistance R 3 and pull down resistor R1; the drain electrode of NMOS discharge tube 1 connects power port 3, ESD detects resistance R 3; the drain electrode that NMOS goes up trombone slide 2 and source electrode are connected the drain and gate of NMOS discharge tube 1 respectively, and the grid of the last trombone slide 2 of NMOS connects ground connection behind the described pull down resistor R1.

The line that the drain electrode of power port 3, NMOS discharge tube 1, ESD detect the drain electrode of resistance R 3, the last trombone slide 2 of NMOS constitutes first node 10, the grid of the last trombone slide 2 of NMOS constitutes Section Point 20 to the line of the pull down resistor R1 of its connection, and the line of the source electrode of the last trombone slide 2 of NMOS and the grid of NMOS discharge tube 1 constitutes the 3rd node 30.The grid of NMOS discharge tube 1 connects a voltage clamp circuit 4 back ground connection, and the effect of voltage clamp circuit 4 is the voltage of restriction the 3rd node 30, makes it to be operated in the safe range.The grid of NMOS discharge tube 1 also connects a pull-down circuit 5 back ground connection.Pull-down circuit 5 can adopt the voltage inversion circuit, and embodiment one as shown in Figure 3; Also can adopt pull down resistor R2, embodiment two as shown in Figure 4.Voltage clamp circuit 4 of the present invention, pull-down circuit 5 repeat no more for the circuit that those of ordinary skills can both grasp.

When the ESD electric current impacts IC interior by I/O power port 3, first node 10 voltages raise rapidly, because last trombone slide 2 exists parasitic capacitance Cgd and Cgs, Section Point 20 voltages also and then rise to a certain magnitude of voltage and make trombone slide 2 conductings, so the 3rd node 30 voltages rise, Section Point 20 voltages can rise along with the voltage of the 3rd node 30 and rise, and Section Point 20 and the 3rd node 30 voltage differences will maintain on a certain magnitude of voltage.The conducting of last trombone slide 2 makes the voltage of the 3rd node 30 reach a higher voltage value rapidly, thereby makes discharge tube 1 abundant conducting, finishes the esd discharge process, and the voltage of first node 10 can progressively descend, and final release finishes.Then pull down resistor R1 can move the voltage of Section Point 20 to ground gradually, and last trombone slide 2 is turned off; Pull-down circuit 5 is moved the voltage of the 3rd node 30 to ground gradually, and discharge tube 1 is turned off.Because the pressure reduction of Section Point 20 and the 3rd node 30 is very little among the present invention, can utilize the parasitic capacitance cgs of trombone slide 2 to open trombone slide 2, and then open discharge tube 1, do not need extra electric capacity.

Claims

1. high pressure esd protection circuit; comprise that power port, NMOS discharge tube, ESD detect resistance and pull down resistor; the drain electrode of NMOS discharge tube connects power port, ESD detects resistance; it is characterized in that: the drain electrode that NMOS goes up trombone slide and source electrode are connected the drain and gate of described NMOS discharge tube respectively, and the grid that described NMOS goes up trombone slide connects ground connection behind the described pull down resistor.

2. according to the described high pressure esd protection circuit of claim 1, the grid that it is characterized in that the NMOS discharge tube connects ground connection behind the voltage clamp circuit.

3. according to claim 1 or 2 described high pressure esd protection circuits, the grid that it is characterized in that the NMOS discharge tube connects ground connection behind the pull-down circuit.

4. according to the described high pressure esd protection circuit of claim 3, it is characterized in that described pull-down circuit is the voltage inversion circuit.

5. according to the described high pressure esd protection circuit of claim 3, it is characterized in that described pull-down circuit is a pull down resistor.