CN101951343A - Device, network switching equipment and method for realizing port configuration - Google Patents
Device, network switching equipment and method for realizing port configuration Download PDFInfo
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Abstract
The invention discloses a device, network switching equipment and a method for realizing port configuration. The device comprises a sampling logic unit, a plurality of port filtering registers, and an interrupt register, wherein the sampling logic unit is used for sampling port state signals transmitted by a plurality of ports respectively; the plurality of port filtering registers are used for recording preset high-level identification when the result of the sampling of the corresponding port state signal in the current period by the sampling logic unit is effective high level and recording preset low-level identification when the result of the sampling of the corresponding port state signal in the current period by the sampling logic unit is effective low level; and the interrupt register is used for reporting an interrupt request signal to a central processing unit (CPU) when monitoring high and low level identification change of data stored by the port filtering registers. The device, network switching equipment and the method reduce the occupation of CPU and bus resources in the conventional port configuration process to the maximum extent and guarantee the rapid switching performance of the network switching equipment.
Description
Technical field
The present invention relates to network switching equipment field, relate in particular to a kind of device, the network switching equipment and method that realizes port arrangement.
Background technology
In the prior art, when the network switching equipment has the operation of plug cable or opposite equip. change speed or change dual-mode, the port status of network switching equipment Switching Module (connection, speed, duplex etc.) can correspondingly change, and this moment, the network switching equipment need carry out the port of Switching Module could continuing communication after the relevant configuration again.
Existing port arrangement mode, the CPU of the network switching equipment generally passes through the mode of periodic each port status of regularly active poll, judge each port demand whether ports having is disposed, so that carry out corresponding configuration service, along with the port number of network switching equipment Switching Module increases gradually, add its management bus bandwidth constraints of Switching Module, the also corresponding thereupon increase of the CPU that polling mode takies and the resource of bus, port arrangement too much takies CPU's, the quick forwarding performance of the Switching Module of the network switching equipment is brought very adverse influence, and forwarding performance is an important indicator weighing the router performance quality fast.
In addition on the one hand, CPU carries out the mode of poll to each port status, in the time of also can causing the port status of network switching equipment Switching Module to change, can't obtain the configuration service of CPU in time, make the port status changed port can't recover communication in time, also influenced the performance of the network switching equipment to a certain extent.
Summary of the invention
The embodiment of the invention provides a kind of device, the network switching equipment and method that realizes port arrangement, the resource occupation of CPU is too much brought the problem of adverse effect to network switching equipment performance in order to solve mode that existing each port status of CPU poll is configured port.
A kind of device of realizing port arrangement that the embodiment of the invention provides comprises: sampling logical block, interrupt register and at least one port filter; Wherein:
The sampling logical block is used for the port status signal of a plurality of port outputs is sampled respectively;
Each described port filter registers, corresponding with a port status signal, be used for when the sampled result of logical block to described port status signal current period of sampling is effective high level, be recorded as default high level sign position; And when the sampled result of logical block to described port status signal current period of sampling is effective low level, be recorded as default low level sign position;
Interrupt register is used to monitor the variation whether each described port filter registers high-low level sign position occurs, and when the variation of high-low level sign position occurring, reports to CPU to be used to ask CPU to interrupt carrying out the interrupt request singal of port arrangement.
A kind of network switching equipment that the embodiment of the invention provides comprises CPU and at least one Switching Module that links to each other with CPU; Each Switching Module comprises a plurality of ports; And at least one realizes the device of port arrangement; The device of each described realization port arrangement links to each other with a Switching Module with CPU; Wherein:
Described CPU is used to receive the interrupt request singal that the device of described realization port arrangement sends, and the port that occurs state variation in the Switching Module that the device with described realization port arrangement is linked to each other disposes accordingly.
A kind of method that realizes port arrangement that the embodiment of the invention provides comprises:
Port status signal to a plurality of port outputs is sampled respectively;
At each port status signal, when the sampled result of this port status signal current period is effective high level, be recorded as default high level sign position; And when the sampled result to this port status signal current period is effective low level, be recorded as default low level sign position;
When the sign position of writing down monitoring out becomes low level sign position by high level sign position or becomes high level sign position by low level sign position, report to CPU to be used to ask described CPU to interrupt carrying out the interrupt request singal of port arrangement;
Described CPU receives described interrupt request singal, and the port that occurs state variation in the described Switching Module is disposed accordingly.
The beneficial effect of the embodiment of the invention comprises:
The device of the realization port arrangement that the embodiment of the invention provides, in the network switching equipment and the method, the sampling logical block is sampled respectively to the port signal of a plurality of port outputs, each port filter registers, when the sampled result of logical block to its corresponding port status signal current period of sampling is effective high level, be recorded as high level sign position, when the sampled result of logical block to its corresponding port status signal current period of sampling is effective low level, be recorded as low level sign position, when interrupt register the variation of high-low level sign position occurred in the data that monitor the storage of certain or certain port filter registers, report to CPU and to be used to ask this CPU to interrupt carrying out the interrupt request singal of port arrangement, CPU is after receiving this interrupt request singal, the operation that can interrupt carrying out, then the port that changing is appearred in state provides corresponding configuration service.The device of the above-mentioned realization port arrangement that the embodiment of the invention provides, the network switching equipment and method, whether the port status signal that active monitoring can characterize port status effective high-low level variation occurs, and when the port status signal effective high-low level occurs and changes, initiatively report interrupt requests to CPU, CPU receives after the interrupt requests, the state changed port is disposed accordingly, with the state of inquiring about each port in the prior art by CPU employing periodic polls mode, judge whether that according to port status needs are that the scheme that port carries out corresponding configuration service is compared, farthest reduced port arrangement service process taking to CPU and bus resource, ensured the fast commentaries on classics performance of the network switching equipment, on the other hand, also make network switching equipment state changed port can obtain the configuration of CPU more in time, recover its communication function as early as possible.
Description of drawings
One of apparatus structure schematic diagram of the realization port arrangement that Fig. 1 provides for the embodiment of the invention;
Two of the apparatus structure schematic diagram of the realization port arrangement that Fig. 2 provides for the embodiment of the invention;
The signal waveforms that Fig. 3 provides for the embodiment of the invention;
The structural representation of the network switching equipment that Fig. 4 provides for the embodiment of the invention;
The structural representation of the example of the network switching equipment that Fig. 5 provides for the embodiment of the invention;
The flow chart of the method for the realization port arrangement that Fig. 6 provides for the embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing, a kind of method of device, the network switching equipment and the realization port arrangement of port arrangement that realizes that the embodiment of the invention is provided is described in detail.
At first a kind of structure and operation principle of the device of port arrangement of realizing that the embodiment of the invention is provided is described in detail.
As shown in Figure 1, the device of the realization port arrangement that the embodiment of the invention provides comprises: sampling logical block 101, interrupt register 102 and at least one port filter registers (among Fig. 1 be example to comprise port filter registers 103 and 104); Wherein:
Sampling logical block 101 is used for the port status signal of a plurality of port outputs is sampled respectively; In other words, sampling logical block 101 is used for converting each port status signal period ground continuous in time to the time and goes up still continuous discrete signal on discrete, the amplitude, in the specific implementation, this sampling logical block 101 for example can adopt logical device such as comparator to realize.
For the purpose of simple declaration, below to the device of realization port arrangement shown in Figure 1, the port status signal of exporting respectively with two ports on the Switching Module of 101 pairs of network switching equipment of sampling logical block (being the port status signal 1 of port one output and the port status signal 2 of port 2 outputs) is sampled as example respectively and describes.
In the device of the realization port arrangement that the embodiment of the invention provides, the quantity of port filter registers is consistent with the quantity of the port of Switching Module, and just the quantity with the port status signal of each port output is consistent.Respectively port status signal 1 and port status signal 2 are sampled as example with the sampling logical block, so, correspondingly, need comprise two corresponding with these two port status signals respectively port filter registers in this device is port filter registers 103 and port filter registers 104.
For instance, when 101 pairs of port status signals of sampling logical block, 1 current sampled result is effective high level, the data record that port filter registers 103 self is stored is " 1 ", when 101 pairs of port status signals of port sampling logical block, 1 current sampled result was effective low level, the data record that port filter registers 103 self is stored was " 0 "; Perhaps conversely, when 101 pairs of port status signals of sampling logical block, 1 current sampled result is effective high level, the data record that port filter registers 103 self is stored is " 0 ", when 101 pairs of port status signals of port sampling logical block, 1 current sampled result was effective low level, the data record that port filter registers 103 self is stored was " 1 ".
Particularly, interrupt register 102, link to each other with 104 with port filter registers 103 respectively, but these interrupt register 102 storage bit numbers data corresponding with port number, the initial value of these data can be set to 00...0 (0 number is consistent with port number), each of these data all with the port status signal corresponding (corresponding with this port status signal corresponding port filter registers in other words) of port output, interrupt register 102 is the variation of monitoring port filter registers 103 and 104 record simultaneously, in case judging the data of certain port filter registers storage occurs changing, for example the data of port filter registers 103 storages become " 1 " by " 0 ", when perhaps becoming " 0 " (variation has taken place the connection status of expression port one) by " 1 ", interrupt register 102 just can be noted this variation, just that one digit number that will be corresponding with port filter registers 103 is according to the interruption sign position that is become default non-zero by " 0 " for example " 1 ", changing does not appear in the record of other port filter registers such as port filter registers 104, and that one digit number certificate of keeping this port filter correspondence so is constant for " 0 ".When a certain position of the data in interrupting register or a few appearance " 1 ", promptly report interrupt request singal to CPU.
CPU reads after the interrupt request singal that interrupt register 102 reports, interrupt the current program of handling, then carry out following operation: the data that read interrupt register 102 storages, according to the sign of the interruption in the data of interrupt register 102 storages position, determine that state variation has appearred in which or which port, thereby the port of determining is configured.For example CPU reads " 10 " data of storing in the interrupt register, according to " 1 " data bit position in the interrupt request singal, the port one of determining port filter registers 103 corresponding port status signals 1 place is the port of state variation, need be configured it, and provide corresponding configuration service to port one by management bus, make port one can proceed communication.
In the device of the realization port arrangement that the embodiment of the invention provides, adopt the interrupt register of a multidigit that the situation of change of the port status signal of each port output is monitored and record simultaneously, and do not adopt a plurality of one interrupt registers respectively the situation of change of the port status signal of each port output to be monitored respectively and record, the benefit of doing like this is, adopt the interrupt register of a multidigit, CPU can be by the operation of once reading to interrupt register, whether the port status that just can know each port changes, make CPU can realize quickly, can also save the spent bus resource of data that CPU reads the interrupt register storage simultaneously a plurality of configuring ports.
Since at the Switching Module of the network switching equipment in concrete use, may have interference signal for various reasons in the port status signal of each port output, whether these interference signals may be that effective high level (low level) produces erroneous judgement to the sampled result of port status signal to the port filter registers.If the port filter registers is recorded as effective high level (low level) with non-effective high level (low level), to cause CPU so and produce unnecessary interruption because non-effective high-low level changes, for fear of this problem occurring, preferably, the device of the realization port arrangement that the embodiment of the invention provides, on architecture basics shown in Figure 1, between sampling logical block and each port filter registers, increase high level counter and low level counter, particularly, the structure chart of this device as shown in Figure 2.
The device of realization port arrangement shown in Figure 2 is an example with two port filters still, between port filter registers 203 and sampling logical block 201, be connected with high level counter 204 and low level counter 205, these two counters are corresponding with the port status signal 1 of port one output; Between port filter registers 208 and sampling logical block 201, be connected with high level counter 206 and low level counter 207, these two counters are corresponding with the port status signal 2 of port 2 outputs.Annexation between other each several parts is identical with Fig. 1.
Sampling logical block 201 in the device of realization port arrangement as shown in Figure 2 must satisfy the sampling period that the port status signal of each port output is sampled respectively: be not less than each port and disturb high level and disturb maximum in the low level width.Because the interference signal of different interference sources is also not quite identical, in the specific implementation, can be according to measured value to each interference signal, determine that each disturbs high level and disturbs low level width, sampling period needs greater than the maximum in each interference high level and the low level, and preferably, the sampling period disturbs the maximum in high level and the low level to get final product slightly greatly than each, excessive even exceeded effective high level or effective low level width, also may cause the erroneous judgement of port filter registers.For instance, suppose that disturbing low level width on certain port is 30 μ s, disturbing the width of high level is 20 μ s, and the sampling of the logical block of sampling so 201 can equal 40 μ s.
With signal waveforms shown in Figure 3 is that example is carried out simple declaration, suppose in 1-3 the cycle (sampling period), the sampled result of 201 pairs of port status signals 1 of sampling logical block remains high level, when the 4th cycle, detect this port status signal 1 and become low level by the high level in last cycle, the counting zero clearing of low level counter 204 so prepares to begin counting work simultaneously.Just in the 4th cycle, the counting of low level counter 204 is " 0 ", the counting of high level counter 203 is compared no change with the previous cycle, when the 5th cycle, detect this port status signal 1 and still be low level, the counting of low level counter 204 becomes " 1 " so, at this moment, because the sampled result of current one-period is a low level, and the counting of low level counter 204 be " 1 " greater than " 0 ", port filter registers 203 can judge that current low level is effective low level so; In the 6th cycle, the sampled result of port status signal 1 is maintained low level, the counting of low level counter is 1 constant (counting that this counter also can be set continues to increase by 1); In the 7th cycle, because the result of the sampling in previous cycle of port status signal is a low level, in this cycle, the sampled result of port status signal 1 transfers high level to by low level, and high level counter 205 prepares to begin counting work simultaneously with the counting zero clearing of self.To the 8th cycle, the sampled result of 201 pairs of port status signals 1 of sampling logical block is a low level, the count results of low level counter 204 is cleared once more, and the counting of high level counter 205 remain " 0 " constant, to the 9th cycle, the sampled result of port status signal 1 still is a low level, the counting of low level counter 204 becomes " 1 " so, because the sampled result in this cycle is a low level, and the count results of low level counter is greater than " 0 ", and port filter registers 203 can judge that current low level is effective low level so.From said process as can be seen, the interference high level signal that occurs between the cycle of 6-7 is not judged to be effective high level by port filter registers 203.
Method how to judge effective high level is also consistent with said method, does not repeat them here.
From signal waveforms shown in Figure 3 as can be seen, through said method, port status signal 1 occur twice is transformed into effective low level state variation by effective low level, all with interrupt register in the variation corresponding (having four high level to occur) of the corresponding data bit of this port signal.
In the device of as shown in Figure 2 realization port arrangement, can also comprise further: Clock dividers 209, be used for the global clock signal is carried out frequency division, generate reference clock signal and also export sampling logical block 201 to; The clock cycle of reference clock signal is not less than each port and disturbs high level and the maximum of disturbing in the low level width;
Sampling logical block 201 further also is used for the clock cycle according to the reference clock signal of Clock dividers 209 outputs, and the port status signal of a plurality of port inputs is sampled respectively.
Still be that 40 μ s are example with aforementioned sampling period value, suppose that the global clock cycle that network-switching equipment offers the device of this realization port arrangement is 40ns, can adopt 1024 frequency divisions to global clock, clock cycle behind the frequency division is 40.96 μ s, adopt the frequency division global clock, to the global clock frequency division, make each sampling period be a bit larger tham each port and disturb high level and the maximum of disturbing in the low level width, not only can eliminate and disturb high level and disturb low level of the harmful effect of port filter registers to the judgement of port status, can also reduce the required figure place of the high level counter and the low level counter of each port correspondence, save hardware resource.
The device (as depicted in figs. 1 and 2) of the above-mentioned realization port arrangement that the embodiment of the invention provides, in the specific implementation, can adopt CPLD (Complex Programmable Logic Device, CPLD) or other logical devices realize.
The embodiment of the invention also provides a kind of network switching equipment, as shown in Figure 4, comprising: the device 403 of CPU 401, at least one Switching Module 402 that links to each other with CPU and at least one realization port arrangement; Each Switching Module 402 comprises a plurality of ports, and each realizes that the device 403 of port arrangement links to each other with a Switching Module 402 with CPU401; Wherein:
Realize the device 403 of port arrangement, be used for the port status signal of each port output of the Switching Module 402 of its connection is sampled respectively; At each port status signal, when the sampled result of this port status signal current period is effective high level, be recorded as default high level sign position; And when the sampled result to this port status signal current period is effective low level, be recorded as default low level sign position; When the sign position of writing down monitoring out becomes low level sign position by high level sign position or becomes high level sign position by low level sign position, report to CPU401 to be used to ask CPU401 to interrupt carrying out the interrupt request singal of port arrangement;
CPU401 is used to receive the interrupt request singal that the device 403 of realizing the echo port configuration reports, to Switching Module 402 that the device 403 of realizing port arrangement links to each other in state variation appears and port dispose accordingly.
Further, realize the device 403 of port arrangement, also be used for the port status signal of each port output being sampled respectively according to interference high level that is not less than each port and interference peaked cycle of low level width; And at each port status signal, be low level in the sampled result to previous cycle of described port status, when the sampled result of current period is high level, the count results of zero clearing high level; In the sampled result to previous cycle of described port status is high level, when the sampled result of current period continues as high level, makes the count results of high level increase by 1; And the sampled result in the previous cycle of described port status is high level, when the sampled result of current period is low level, and the low level count results of zero clearing; In the sampled result to previous cycle of described port status is low level, when the sampled result of current period continues as low level, makes low level count results increase by 1;
The sampled result to described port status signal current period be the count results of high level and high level greater than zero the time, the sampled result of determining this port status signal current period is effective high level; And be low level and low level count results greater than zero the time in the sampled result to described port status signal current period, the sampled result of determining this port status signal current period is effective low level.
Further, the device 403 of above-mentioned realization port arrangement, when also being used to monitor the port status signal and the variation of high-low level sign position occurring, the interruption sign position of the non-zero that the data bit corresponding with this port status signal is set to preset in the data of self storage;
Correspondingly, CPU401 after specifically being used to receive interrupt request singal, reads the data of its storage from the device 403 of this realization port arrangement; Determine that interrupting identifying a port at corresponding port status signal place in these data is the port that state variation occurs, disposes accordingly to the port of determining.
Further, the device 403 of above-mentioned realization port arrangement specifically is used for the global clock signal is carried out frequency division, generates reference clock signal; The clock cycle of described reference clock signal is not less than each port and disturbs high level and the maximum of disturbing in the low level width; According to the clock cycle of described reference clock signal, the port status signal of a plurality of port inputs is sampled respectively.
The network switching equipment that the embodiment of the invention provides in the specific implementation, can be the equipment that router etc. has the network exchange function, the device 403 of realizing port arrangement can adopt programmable logic device realizations such as CPLD, Fig. 5 is an instantiation of the network switching equipment that provides of the embodiment of the invention, to each Switching Module (Switching Module 1, Switching Module 2 and Switching Module 3), a CPLD is set respectively, this CPLD possesses every function of the device of above-mentioned realization port arrangement, with each port (port one on each Switching Module, port 2 and port 3) the port status signal of output introduces CPLD on this Switching Module, and the output that the CPLD on each Switching Module draws an interrupt request singal again links to each other with the interruption input pin of CPU.
Based on same inventive concept, the embodiment of the invention also provides a kind of method that realizes port arrangement, because the principle that this method is dealt with problems is similar with the network switching equipment to the device of aforementioned realization port arrangement, therefore the enforcement of this method can repeat part and repeat no more referring to the enforcement of the device and the network switching equipment of aforementioned realization port arrangement.
A kind of method that realizes port arrangement that the embodiment of the invention provides as shown in Figure 6, comprising:
S601, the port status signal of a plurality of ports output is sampled respectively;
S602, at each port status signal, when the sampled result of this port status signal current period is effective high level, the high level sign position that record is default; And when the sampled result to this port status signal current period is effective low level, the low level sign position that record is default;
When S603, the sign position of writing down monitoring out become low level sign position by high level sign position or become high level sign position by low level sign position, report to CPU to be used to ask this CPU to interrupt carrying out the interrupt request singal of port arrangement;
S604, CPU receive this interrupt request singal, and the port that occurs state variation in this Switching Module is disposed accordingly.
Further, among the above-mentioned steps S602, determine that sampled result is effective high level, realizes by following manner:
According to the peaked cycle in interference high level that is not less than each port and the low level width of interference, the port status signal of a plurality of ports outputs is sampled respectively;
At each port status signal, be low level in sampled result to previous cycle of described port status signal, when the sampled result of current period is high level, the count results of zero clearing high level;
In the sampled result to previous cycle of this port status signal is high level, when the sampled result of current period continues as high level, makes the count results of described high level increase by 1;
The sampled result to described port status signal current period be the count results of high level and high level greater than zero the time, the sampled result of determining this port status signal current period is effective high level.
Further, among the above-mentioned steps S602, determine that sampled result is effective low level, realizes by following manner:
According to the peaked cycle in interference high level that is not less than each port and the low level width of interference, the port status signal of a plurality of ports outputs is sampled respectively;
At each port status signal, be high level in sampled result to previous cycle of described port status signal, when the sampled result of current period is low level, the low level count results of zero clearing;
In the sampled result to previous cycle of this port status signal is low level, when the sampled result of current period continues as low level, makes described low level count results increase by 1;
In the sampled result to described port status signal current period is low level and low level count results greater than zero the time, and the sampled result of determining this port status signal current period is effective low level.
Further, among the step S601, the cycle of sampling can obtain by following manner: the global clock signal is carried out frequency division, generate reference clock signal; The clock cycle of reference clock signal is not less than port and disturbs high level and port to disturb higher value in the low level width; With cycle clock cycle of described reference clock signal as sampling.
The device of the realization port arrangement that the embodiment of the invention provides, in the network switching equipment and the method, the sampling logical block is sampled respectively to the port signal of a plurality of port outputs, each port filter registers, when the sampled result of logical block to its corresponding port status signal current period of sampling is effective high level, be recorded as high level sign position, when the sampled result of logical block to its corresponding port status signal current period of sampling is effective low level, be recorded as low level sign position, when interrupt register the variation of high-low level sign position occurred in the data that monitor the storage of certain or certain port filter registers, report to CPU and to be used to ask this CPU to interrupt carrying out the interrupt request singal of port arrangement, CPU is after receiving this interrupt request singal, can carry out the operation that interruption is being carried out, then the port that changing is appearred in state provides corresponding configuration service.The device of the above-mentioned realization port arrangement that the embodiment of the invention provides, the network switching equipment and method, whether the port status signal that active monitoring can characterize port status effective high-low level variation occurs, and when the port status signal effective high-low level occurs and changes, initiatively report interrupt requests to CPU, CPU receives after the interrupt requests, the state changed port is configured service, with the state of inquiring about each port in the prior art by CPU employing periodic polls mode, judge whether that according to port status needs are that the scheme that port carries out corresponding configuration service is compared, farthest reduced port arrangement service process taking to CPU and bus resource, ensured the fast commentaries on classics performance of the network switching equipment, on the other hand, also make network switching equipment state changed port can obtain the configuration of CPU more in time, recover its communication function as early as possible.
Further, the device of the realization port arrangement that the embodiment of the invention provides, the network switching equipment and method, between sampling logical block and each port filter registers, also be provided with high level counter and low level counter, the sampling logical block is according to the peaked cycle in interference high level that is not less than each port and the low level width of interference, port status signal to a plurality of port outputs is sampled respectively, filter registers is passed through the result of current period sampling and the counting of high level counter or low level counter, whether the port status signal of judging current period is effective high level or effective low level, avoided the ports filter register that the high-low level erroneous judgement of disturbing is effective high-low level, thereby caused CPU because non-effective high-low level changes the problem of the unnecessary interruption that produces.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (11)
1. a device of realizing port arrangement is characterized in that, comprising: sampling logical block, interrupt register and at least one port filter; Wherein:
The sampling logical block is used for the port status signal of a plurality of port outputs is sampled respectively;
Each described port filter registers, corresponding with a port status signal, be used for when the sampled result of logical block to described port status signal current period of sampling is effective high level, be recorded as default high level sign position; And when the sampled result of logical block to described port status signal current period of sampling is effective low level, be recorded as default low level sign position;
Interrupt register is used to monitor the variation whether each described port filter registers high-low level sign position occurs, and when the variation of high-low level sign position occurring, reports to CPU to be used to ask CPU to interrupt carrying out the interrupt request singal of port arrangement.
2. device as claimed in claim 1 is characterized in that, between described sampling logical block and each port filter registers, also comprises: high level counter and low level counter;
Described sampling logical block also is used for according to interference high level that is not less than each port and interference peaked cycle of low level width the port status signal of a plurality of ports outputs being sampled respectively;
Described high level counter, being used in the sampling logical block is low level to the sampled result in the previous cycle of described high level counter corresponding port status signal, when the sampled result of current period is high level, zero clearing self count results; And be high level in the sampling logical block to the sampled result in the previous cycle of described high level counter corresponding port status signal, when the sampled result of current period continues as high level, make self count results increase by 1;
Described low level counter, being used in the sampling logical block is high level to the sampled result in the previous cycle of described low level counter corresponding port status signal, when the sampled result of current period is low level, zero clearing self count results; And be low level in the sampling logical block to the sampled result in the previous cycle of described high level counter corresponding port status signal, when the sampled result of current period continues as low level, make self count results increase by 1;
The described port filter registers that links to each other with the low level counter with described high level counter, also be used for described sampling logical block to the sampled result of this port status signal current period be the counting of high level and described high level counter greater than zero the time, the sampled result of determining this port status signal current period is effective high level; And described sampling logical block to the sampled result of this port status signal current period be the counting of low level and described low level counter greater than zero the time, the sampled result of determining this port status signal current period is effective high level.
3. device as claimed in claim 1 or 2, it is characterized in that, described interrupt register, when also being used for the monitoring port filter and the variation of high-low level sign position occurring, the interruption sign position of the non-zero that the data bit of this port filter correspondence is set to preset in the data of self storage.
4. device as claimed in claim 3 is characterized in that, described interrupt register also is used for CPU reads the data of this interrupt register storage according to described interrupt request singal after, the interruption sign position in the data of the described interrupt register storage of zero clearing.
5. device as claimed in claim 1 or 2 is characterized in that, also comprises: Clock dividers, be used for the global clock signal is carried out frequency division, and generate reference clock signal and export described sampling logical block to; The clock cycle of described reference clock signal is not less than each port and disturbs high level and the maximum of disturbing in the low level width;
Described sampling logical block also is used for the clock cycle according to described reference clock signal, and the port status signal of a plurality of port inputs is sampled respectively.
6. a network switching equipment comprises CPU and at least one Switching Module that links to each other with CPU; Each Switching Module comprises a plurality of ports; It is characterized in that, also comprise: at least one is as the device of the realization port arrangement of claim 1 or 2; The device of each described realization port arrangement links to each other with a Switching Module with CPU; Wherein:
Described CPU is used to receive the interrupt request singal that the device of described realization port arrangement sends, and the port that occurs state variation in the Switching Module that the device with described realization port arrangement is linked to each other disposes accordingly.
7. the network switching equipment as claimed in claim 6, it is characterized in that, the device of described realization port arrangement, when also being used to monitor the port status signal and the variation of high-low level sign position occurring, the interruption sign position of the non-zero that the data bit corresponding with this port status signal is set to preset in the data of self storage;
Described CPU after specifically being used to receive described interrupt request singal, reads the data of its storage from the device of described realization port arrangement; Determine that interrupting identifying a port at corresponding port status signal place in these data is the port that state variation occurs, disposes accordingly to the described port of determining.
8. a method that realizes port arrangement is characterized in that, comprising:
Port status signal to a plurality of port outputs is sampled respectively;
At each port status signal, when the sampled result of this port status signal current period is effective high level, be recorded as default high level sign position; And when the sampled result to this port status signal current period is effective low level, be recorded as default low level sign position;
When the sign position of writing down monitoring out becomes low level sign position by high level sign position or becomes high level sign position by low level sign position, report to CPU to be used to ask described CPU to interrupt carrying out the interrupt request singal of port arrangement;
Described CPU receives described interrupt request singal, and the port that occurs state variation in the described Switching Module is disposed accordingly.
9. method as claimed in claim 8 is characterized in that, determines that sampled result is effective high level, realizes by following manner:
According to the peaked cycle in interference high level that is not less than each port and the low level width of interference, the port status signal of a plurality of ports outputs is sampled respectively;
At each port status signal, be low level in sampled result to previous cycle of described port status signal, when the sampled result of current period is high level, the count results of zero clearing high level;
In the sampled result to previous cycle of described port status signal is high level, when the sampled result of current period continues as high level, makes the count results of described high level increase by 1;
The sampled result to described port status signal current period be the count results of high level and high level greater than zero the time, the sampled result of determining this port status signal current period is effective high level.
10. method as claimed in claim 8 is characterized in that, determines that sampled result is effective low level, realizes by following manner:
According to the peaked cycle in interference high level that is not less than each port and the low level width of interference, the port status signal of a plurality of ports outputs is sampled respectively;
At each port status signal, be high level in sampled result to previous cycle of described port status signal, when the sampled result of current period is low level, the low level count results of zero clearing;
In the sampled result to previous cycle of described port status signal is low level, when the sampled result of current period continues as low level, makes described low level count results increase by 1;
In the sampled result to described port status signal current period is low level and low level count results greater than zero the time, and the sampled result of determining this port status signal current period is effective low level.
11., it is characterized in that as claim 9 or 10 described methods, according to the peaked cycle in interference high level that is not less than each port and the low level width of interference, the port status signal of a plurality of ports outputs is sampled respectively, comprising:
The global clock signal is carried out frequency division, generate reference clock signal; The clock cycle of described reference clock signal is not less than each port and disturbs high level and the maximum of disturbing in the low level width;
According to the clock cycle of described reference clock signal, the port status signal of a plurality of port inputs is sampled respectively.
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| CN2010102905043A CN101951343A (en) | 2010-09-21 | 2010-09-21 | Device, network switching equipment and method for realizing port configuration |
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| CN2010102905043A CN101951343A (en) | 2010-09-21 | 2010-09-21 | Device, network switching equipment and method for realizing port configuration |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108667515A (en) * | 2018-04-23 | 2018-10-16 | 新华三技术有限公司 | Port configuration method and communication equipment |
| CN109635355A (en) * | 2018-11-19 | 2019-04-16 | 北京时代民芯科技有限公司 | A kind of adjustable filter circuit of frequency towards GPIO |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10333920A (en) * | 1997-05-30 | 1998-12-18 | Mitsubishi Heavy Ind Ltd | Interruption processing circuit |
| CN1298519A (en) * | 1998-04-29 | 2001-06-06 | 英特尔公司 | Interrupt controller |
| CN1811480A (en) * | 2005-01-26 | 2006-08-02 | 华为技术有限公司 | Method and apparatus for real-time monitoring level signal |
-
2010
- 2010-09-21 CN CN2010102905043A patent/CN101951343A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10333920A (en) * | 1997-05-30 | 1998-12-18 | Mitsubishi Heavy Ind Ltd | Interruption processing circuit |
| CN1298519A (en) * | 1998-04-29 | 2001-06-06 | 英特尔公司 | Interrupt controller |
| CN1811480A (en) * | 2005-01-26 | 2006-08-02 | 华为技术有限公司 | Method and apparatus for real-time monitoring level signal |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108667515A (en) * | 2018-04-23 | 2018-10-16 | 新华三技术有限公司 | Port configuration method and communication equipment |
| CN109635355A (en) * | 2018-11-19 | 2019-04-16 | 北京时代民芯科技有限公司 | A kind of adjustable filter circuit of frequency towards GPIO |
| CN109635355B (en) * | 2018-11-19 | 2023-04-18 | 北京时代民芯科技有限公司 | GPIO-oriented frequency-adjustable filter circuit |
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