CN101944315B - Source driver and display employing source driver - Google Patents
Source driver and display employing source driver Download PDFInfo
- Publication number
- CN101944315B CN101944315B CN200910140244.9A CN200910140244A CN101944315B CN 101944315 B CN101944315 B CN 101944315B CN 200910140244 A CN200910140244 A CN 200910140244A CN 101944315 B CN101944315 B CN 101944315B
- Authority
- CN
- China
- Prior art keywords
- receiver
- output node
- node
- input node
- coupled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Electronic Switches (AREA)
Abstract
The invention discloses a source driver, which comprises a receiver and a channel. The receiver is used for receiving a digital signal at an input node so as to generate a received signal at an output node, and comprises a first switch, a second switch and a voltage-limiting circuit, wherein the first switch selectively connects the output node of the receiver to first reference voltage based on the digital signal; the second switch connects the output node of the receiver to second reference voltage based on the digital signal; the voltage-limiting circuit is coupled between the input node and the output node of the receiver and is used for limiting the voltage level of the input node of the receiver; and the channel generates driving voltage based on the received signal.
Description
Technical field
The present invention relates to forwarder and receiver, be especially applied to forwarder and the receiver of display.
Background technology
Please refer to Fig. 1, Fig. 1 is the schematic diagram of known transistors-transistor logic (transistor-transistor logic, TTL) interface 100.As shown in Figure 1, TTL interface 100 includes a forwarder 110 and a receiver 120, and wherein receiver 120 receives a digital signal via a single data line L.Yet, concerning TTL interface 100, generally speaking this digital signal needs to have the larger amplitude of oscillation (swing), and electromagnetic interference (EMI) (electronic-magnetic interference, EMI) can be therefore comparatively serious, cause its frequency that can operate to be restricted.
In order to solve electromagnetic interference (EMI) in TTL interface 100 and problem that can operation frequency, therefore a kind of low-swing differential signal transmission (reduced swing differential signaling, RSDS) circuit is suggested.Fig. 2 is the schematic diagram of the known circuits 200 of application low-swing differential signal transmission.As shown in Figure 2, circuit 200 includes a forwarder 210 and a receiver 220, and wherein receiver 220 is via a pair of single data line together with being coupled in forwarder 210.The amplitude of oscillation transmitting on to single data line at this due to circuit 200 is less, thus electromagnetic interference (EMI) with can on operation frequency, have good performance.Yet, the current source IS1 in forwarder 210 and IS2 need to provide larger electric current (approximately 2 milliampere) to this on single data line, thereby cause a large amount of power consumption.Moreover the single data line number that circuit 200 is used is the twice of TTL interface, and then has increased cost of manufacture.
Summary of the invention
One of object of the present invention is to provide a kind of display that includes time schedule controller and one source pole driver, to address the above problem, wherein this display have less electromagnetic interference (EMI) with preferably can operation frequency, and between this time schedule controller and this source electrode driver, there is lower circuit layout's complexity.
According to one embodiment of the present of invention, disclose a kind of source electrode driver, this source electrode driver includes a receiver and a passage, and this receiver is used for receiving a digital signal to produce a received signal at an output node at an input node.This receiver includes one first switch, a second switch, a pressure limiting circuit.This first switch is optionally connected to the first reference voltage by this output node of this receiver based on this digital signal.This second switch is optionally connected to the second reference voltage by this output node of this receiver based on this digital signal.This pressure limiting circuit is coupled between this input node and this output node of this receiver, in order to limit the voltage quasi position of this input node of this receiver.This passage produces driving voltage based on this received signal.
According to another embodiment of the present invention, disclose a kind of display.This display includes time schedule controller and above-mentioned source electrode driver.This time schedule controller receives an input signal and produces a digital signal, and this source electrode driver includes a receiver, via a single data line, be coupled to this output node of this reverser, in order to receive this digital signal via this single data line from this time schedule controller.This time schedule controller includes a reverser, one first current source and one second current source.This reverser has for receiving an input node of this input signal, and produces this digital signal at an output node.This first current source supply one first electric current is given the first power supply node of this reverser.This second current source supply one second electric current is given the second source node of this reverser.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of known transistors-transistor logic interface.
Fig. 2 is the schematic diagram of known low-swing differential signal circuit.
Fig. 3 is the forwarder and the schematic diagram of receiver that is applied to the source electrode driver of display that is applied to the time schedule controller of display in one embodiment of the invention.
Fig. 4 is the schematic diagram of another embodiment of the pressure limiting circuit shown in Fig. 3.
Fig. 5 is the schematic diagram of another embodiment again of the pressure limiting circuit shown in Fig. 3.
Embodiment
In instructions and follow-up claims, used some vocabulary to censure specific element.Those skilled in the art should understand, and hardware manufacturer may be called same element with different nouns.This instructions and follow-up claims are not used as distinguishing the mode of element with the difference of title, but the difference in function is used as the criterion of distinguishing with element.In the whole text, in the middle of instructions and follow-up claims, be an open language mentioned " comprising ", therefore should be construed to " comprise but be not limited to ".In addition, " coupling " word comprises directly any and is indirectly electrically connected means at this.Therefore, if describe a first device in literary composition, be coupled to one second device, represent that this first device can directly be electrically connected in this second device, or be indirectly electrically connected to this second device by other devices or connection means.
Please refer to Fig. 3, Fig. 3 is a forwarder 310 in one embodiment of the invention and the schematic diagram of a receiver 320.Forwarder 310 can be used for the time schedule controller in a display, and receiver 310 can be used for the one source pole driver in this display.As shown in Figure 3, forwarder 310 includes a reverser 312 and a plurality of power supply I
1with I
2, wherein reverser 312 includes a P transistor npn npn M
p1with a N-type transistor M
n1.Current source I
1supply with one first electric current to the power supply node in reverser 312, and current source I
2supply with one second electric current to another power supply node in reverser 312.
Receiver 320 includes one first switch M
p2, a second switch M
n2an and pressure limiting circuit 322.In this embodiment, the first switch M
p2to realize with a P transistor npn npn, and second switch M
n2to realize with a N-type transistor; In addition, pressure limiting circuit 322 includes the N-type transistor M that a diode mode connects (diode-connected)
n3the P transistor npn npn M being connected with a diode mode
p3.Forwarder 310 is to couple via a single data line and receiver 320, and the resistance R shown in Fig. 3
loadwith a capacitor C
loadrepresent respectively an equivalent dead resistance and an equivalent parasitic capacitances of this single data line.
In the middle of the running of forwarder 310 and receiver 320, reverser 312 is at an input node N
iN- tXupper reception one input signal V
i, and at output node N
oUT-TXupper generation one digital signal V
dig, and digital signal V
digthen via this single data line, be sent to an input node N in receiver 320
iN-RX.The first switch M
p2based on digital signal V
digcome optionally by an output node N of receiver 320
oUT-RXbe connected to one first reference voltage V
dD-RX, and second switch M
n2based on digital signal V
digcome optionally by the output node N of receiver 320
oUT-RXbe connected to one second reference voltage GND, and output node N
oUT-RXupper meeting produces a received signal V
out.At the same time, pressure limiting circuit 322 can limit the input node N of receiver 320
iN-RXvoltage quasi position.
Receiver 320 also optionally (optionally) comprises a reverser 324 by received signal V
outoppositely to produce a reverse received signal V
outb, last, the passage in this source electrode driver is just based on reverse received signal V
outbproduce driving voltage.
For instance, as input signal V
iwhen " 0 " logic state (electronegative potential), by forwarder 310 to the current path of receiver 320 by current source I
1start, then through P transistor npn npn M
p1, this single data line, meet the input node N of putting device 320
iN-RX, N-type transistor M
n3, N-type transistor M
n2, and finally enter a node with the second reference voltage GND, and now, the input node N of receiver 320
iN-RXvoltage quasi position be N-type transistor M
n3a drain electrode-source voltage V
dSwith N-type transistor M
n2a grid-source voltage V
gSsummation, and this voltage quasi position is less than a service voltage V of forwarder 310
dD-TX, in addition, the output node N of receiver 320
oUT-RXcan be in lower voltage quasi position.Transistor M
n3with M
n2critical voltage (threshold voltage) can be via suitable design so that input node N
iN-RXon voltage quasi position enough large so that state at this moment under close transistor M
p2and in order to avoid transistor M
p2with M
n2be switched on simultaneously.
Similarly, as input signal V
iwhen " 1 " logic state (noble potential), by forwarder 310 to the current path of receiver 320 by P transistor npn npn M
p2start, then the output node N of process receiver 320
oUT-RX, P transistor npn npn M
p3, meet the input node N of putting device 320
iN-RX, this single data line, N-type transistor M
n1, current source I
2, and finally enter earth terminal (ground), and now, the input node N of receiver 320
iN-RXvoltage quasi position be P transistor npn npn M
p2a drain electrode-source voltage V
dSwith P transistor npn npn M
p3a grid-source voltage V
gSsummation and the first reference voltage V
dD-RXpoor, and this voltage quasi position is greater than the ground voltage of forwarder 310, in addition, the output node N of receiver 320
oUT-RXcan be in higher voltage quasi position.Transistor M
p3with M
p2critical voltage can be via suitable design so that input node N
iN-RXon voltage quasi position enough little so that state at this moment under close transistor M
n2and avoid transistor M
p2with M
n2be switched on simultaneously.
For instance, suppose V
dD-RXwith V
dD-TXbe all 1.8 volts, when the amplitude of oscillation of digital signal is about 1 volt in the present invention (0.4V-1.4V), much smaller than the amplitude of oscillation (0V-1.8V) of digital signal in TTL interface 100.Therefore, display proposed by the invention is in electromagnetic interference (EMI) and can on operation frequency, have preferably performance, in addition, and because receiver 320 is connected with forwarder 310 via this single data line, therefore fairly simple and uncomplicated in circuit layout.
In addition, in the middle of circuit 200, the current source I of forwarder 210
s1with I
s2need to supply more electric current (approximately 2 milliampere) and give these data lines to maintain the fixed voltage of these data lines, and in the present invention, this fixed voltage (digital voltage V
diga medium voltage) by forwarder 310 and receiver 320 institute itself, produced so current source I
s1with I
s2only need to supply with less electric current to these data lines to maintain the fixed voltage of these data lines.
It should be noted that in the present invention, forwarder 310 is applied in time schedule controller, yet so design is only the use of explanation, is not used for limiting the implementation of time schedule controller.For example, forwarder 310 can be implemented between any control circuit and source electrode driver, and these design on variations still belong to category of the present invention within.
In addition, in the present embodiment, receiver 320 includes reverser 324, and the passage in source electrode driver can be based on reverse received signal V
outbproduce driving voltage, yet in other embodiment of the present invention, reverser 324 can remove in receiver 320, and passage in source electrode driver is just based on received signal V
outproduce driving voltage.
Fig. 4 and Fig. 5 are the schematic diagram of other embodiment of pressure limiting circuit of the present invention.In Fig. 4, pressure limiting circuit 400 includes one first N-type transistor M
n4with one second N-type transistor M
n5, the first N-type transistor M wherein
n4with the second N-type transistor M
n5the input node N that connects and be coupled to receiver 320 in diode mode
iN-RXwith output node N
oUT-RXbetween, the first N-type transistor M
n4grid be connected in the input node N of receiver 320
iN-RX, and the second N-type transistor M
n5grid be connected in the output node N of receiver 320
oUT-RX.In Fig. 5, pressure limiting circuit 500 includes one the one P transistor npn npn M
p4with one the 2nd P transistor npn npn M
p5, a P transistor npn npn M wherein
p4with the 2nd P transistor npn npn M
p5the input node N that connects and be coupled to receiver 320 in diode mode
iN-RXwith output node N
oUT-RXbetween, a P transistor npn npn M
p4grid be connected in the input node N of receiver 320
iN-RX, and the 2nd P transistor npn npn M
p5grid be connected in the output node N of receiver 320
oUT-RX.
The foregoing is only the preferred embodiments of the present invention, all equivalent variations of doing according to the claims in the present invention book and modification, all should belong to covering scope of the present invention.
Claims (14)
1. a source electrode driver, includes:
One receiver, is used for receiving a digital signal to produce a received signal at an output node at an input node, and this receiver includes:
One first switch, in order to be optionally connected to the first reference voltage by this output node of this receiver based on this digital signal;
One second switch, in order to be optionally connected to the second reference voltage by this output node of this receiver based on this digital signal; And
One pressure limiting circuit, is coupled between this input node and this output node of this receiver, in order to limit the voltage quasi position of this input node of this receiver; And
One passage, in order to produce driving voltage based on this received signal.
2. source electrode driver according to claim 1, wherein this receiver also includes:
One reverser, is coupled between this output node and this passage.
3. source electrode driver according to claim 1, wherein this pressure limiting circuit includes:
The transistor that one diode mode connects, is coupled between this input node and this output node of this receiver.
4. source electrode driver according to claim 1, wherein this pressure limiting circuit includes:
One P transistor npn npn, is coupled between this input node and this output node of this receiver, and wherein the grid of this P transistor npn npn is connected to this input node of this receiver; And
One N-type transistor, is coupled between this input node and this output node of this receiver, and wherein the transistorized grid of this N-type is connected to this input node of this receiver.
5. source electrode driver according to claim 1, wherein this pressure limiting circuit includes:
One first N-type transistor, is coupled between this input node and this output node of this receiver, and wherein the transistorized grid of this first N-type is connected to this input node of this receiver; And
One second N-type transistor, is coupled between this input node and this output node of this receiver, and wherein the transistorized grid of this second N-type is connected to this output node of this receiver.
6. source electrode driver according to claim 1, wherein this pressure limiting circuit includes:
One the one P transistor npn npn, is coupled between this input node and this output node of this receiver, and wherein the grid of a P transistor npn npn is connected to this input node of this receiver; And
One the 2nd P transistor npn npn, is coupled between this input node and this output node of this receiver, and wherein the grid of the 2nd P transistor npn npn is connected to this output node of this receiver.
7. source electrode driver according to claim 1, wherein this first switch is a P transistor npn npn, this second switch is a N-type transistor, and this first reference voltage is greater than this second reference voltage.
8. a display, includes:
Time schedule controller, produces a digital signal in order to receive an input signal, and this time schedule controller includes:
One reverser, has for receiving an input node of this input signal, and produces this digital signal at an output node;
One first current source, in order to supply first power supply node of one first electric current to this reverser; And
One second current source, in order to supply the second source node of one second electric current to this reverser; And
One source pole driver, it includes a receiver, it is coupled to this output node of this reverser via a single data line, in order to receive this digital signal via this single data line from this time schedule controller, wherein this receiver receives a digital signal to produce a received signal at an output node at an input node, and this receiver includes:
One first switch, in order to be optionally connected to the first reference voltage by this output node of this receiver based on this digital signal;
One second switch, in order to be optionally connected to the second reference voltage by this output node of this receiver based on this digital signal; And
One pressure limiting circuit, is coupled between this input node and this output node of this receiver, in order to limit the voltage quasi position of this input node of this receiver;
Wherein this source electrode driver also includes a passage, in order to produce driving voltage based on this received signal.
9. display according to claim 8, wherein this receiver also includes:
One reverser, is coupled between this output node and this passage of this receiver.
10. display according to claim 8, wherein this pressure limiting circuit includes:
The transistor that one diode mode connects, is coupled between this input node and this output node of this receiver.
11. displays according to claim 8, wherein this pressure limiting circuit includes:
One P transistor npn npn, is coupled between this input node and this output node of this receiver, and wherein the grid of this P transistor npn npn is connected to this input node of this receiver; And
One N-type transistor, is coupled between this input node and this output node of this receiver, and wherein the transistorized grid of this N-type is connected to this input node of this receiver.
12. displays according to claim 8, wherein this pressure limiting circuit includes:
One first N-type transistor, is coupled between this input node and this output node of this receiver, and wherein the transistorized grid of this first N-type is connected to this input node of this receiver; And
One second N-type transistor, is coupled between this input node and this output node of this receiver, and wherein the transistorized grid of this second N-type is connected to this output node of this receiver.
13. displays according to claim 8, wherein this pressure limiting circuit includes:
One the one P transistor npn npn, is coupled between this input node and this output node of this receiver, and wherein the grid of a P transistor npn npn is connected to this input node of this receiver; And
One the 2nd P transistor npn npn, is coupled between this input node and this output node of this receiver, and wherein the grid of the 2nd P transistor npn npn is connected to this output node of this receiver.
14. displays according to claim 8, wherein this first switch is a P transistor npn npn, this second switch is a N-type transistor, and this first reference voltage is greater than this second reference voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910140244.9A CN101944315B (en) | 2009-07-09 | 2009-07-09 | Source driver and display employing source driver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910140244.9A CN101944315B (en) | 2009-07-09 | 2009-07-09 | Source driver and display employing source driver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101944315A CN101944315A (en) | 2011-01-12 |
| CN101944315B true CN101944315B (en) | 2014-04-02 |
Family
ID=43436289
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910140244.9A Expired - Fee Related CN101944315B (en) | 2009-07-09 | 2009-07-09 | Source driver and display employing source driver |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101944315B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9595217B2 (en) * | 2013-12-05 | 2017-03-14 | Samsung Display Co., Ltd. | Trace structure for improved electrical signaling |
| US10795392B1 (en) * | 2019-04-16 | 2020-10-06 | Novatek Microelectronics Corp. | Output stage circuit and related voltage regulator |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5680069A (en) * | 1993-12-28 | 1997-10-21 | Nec Corporation | Driver/receiver circuit including receiver circuit with p-channel MOSFET and N-channel MOSFET |
| CN1746963A (en) * | 2004-09-07 | 2006-03-15 | 精工爱普生株式会社 | Source driver, electro-optical device, electronic apparatus, and driving method |
| CN101097701A (en) * | 2006-06-30 | 2008-01-02 | 奇景光电股份有限公司 | Source driver of liquid crystal display and the driving method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5621342A (en) * | 1995-10-27 | 1997-04-15 | Philips Electronics North America Corporation | Low-power CMOS driver circuit capable of operating at high frequencies |
| US5929656A (en) * | 1997-05-16 | 1999-07-27 | Motorola, Inc. | Method and apparatus for driving a capacitive display device |
| TW200904002A (en) * | 2007-07-03 | 2009-01-16 | Toppoly Optoelectronics Corp | Level shifter, interface driving circuit, and image display system |
-
2009
- 2009-07-09 CN CN200910140244.9A patent/CN101944315B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5680069A (en) * | 1993-12-28 | 1997-10-21 | Nec Corporation | Driver/receiver circuit including receiver circuit with p-channel MOSFET and N-channel MOSFET |
| CN1746963A (en) * | 2004-09-07 | 2006-03-15 | 精工爱普生株式会社 | Source driver, electro-optical device, electronic apparatus, and driving method |
| CN101097701A (en) * | 2006-06-30 | 2008-01-02 | 奇景光电股份有限公司 | Source driver of liquid crystal display and the driving method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101944315A (en) | 2011-01-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7199617B1 (en) | Level shifter | |
| US9443608B2 (en) | Shift register having multiple output units connected in cascade as display device scan line driving circuit | |
| JP4960833B2 (en) | Interface circuit capable of switching between single-ended transmission and differential transmission | |
| CN111696469B (en) | Shift register, scanning circuit and display panel | |
| US8952725B2 (en) | Low voltage differential signal driving circuit and electronic device compatible with wired transmission | |
| KR100232661B1 (en) | Analog switching circuit | |
| US8750391B2 (en) | Differential signal output device and portable device | |
| CN111243502B (en) | Pixel driving circuit and display device | |
| CN113763859B (en) | Shift register and driving method thereof, grid driving circuit, panel and device | |
| CN101944315B (en) | Source driver and display employing source driver | |
| US8212758B2 (en) | Source driver and display utilizing the source driver | |
| US11005477B2 (en) | Driver circuit and control method therefor, and transmission/reception system | |
| CN101888239B (en) | Output buffer, source electrode driver and electronic system | |
| KR100713907B1 (en) | Circuit for driving lines of a semiconductor | |
| US8279155B2 (en) | Source driver and display utilizing the source driver | |
| CN210864699U (en) | Interface circuit of display device and IIC device | |
| KR101067330B1 (en) | Apparatus for high-speed rf signal switching | |
| TWI409783B (en) | Source driver and display utilizing the source driver | |
| CN101123431B (en) | Current mode logic-cmos converter | |
| CN116232311B (en) | Input circuit of single bus communication chip and chip | |
| US20130135037A1 (en) | Voltage multiplying circuit, signal switch chip and impedance adjusting method thereof | |
| CN109817153B (en) | Gate driving unit, gate driving method, gate driving circuit and display device | |
| JP2003224460A (en) | Receiving circuit | |
| US7288981B2 (en) | Voltage translator circuits using capacitive techniques | |
| CN115862513A (en) | Shift register and driving method thereof, scanning driving circuit and display panel |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140402 Termination date: 20200709 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |