CN101924074A - CMOS (Complementary Metal Oxide Semiconductor) sensor and manufacturing method thereof - Google Patents
CMOS (Complementary Metal Oxide Semiconductor) sensor and manufacturing method thereof Download PDFInfo
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Abstract
The invention relates to a CMOS (Complementary Metal Oxide Semiconductor) sensor and a manufacturing method thereof, wherein the manufacturing method of the CMOS sensor comprises the following steps of: forming a second metal layer and a first electrode of a capacitor on the surface of a first metal interlamination medium layer; forming a second metal interlamination medium layer covering the first metal interlamination medium layer, the second metal layer and the first electrode of the capacitor; forming a groove exposing the first electrode of the capacitor in the second metal interlamination medium layer; forming a medium layer on the side wall and the bottom of the groove; forming a through hole exposing the second metal layer in the second metal interlamination medium layer; filling the groove and the through hole by using metal; and forming a second electrode corresponding to the first electrode of the capacitor on the groove, and forming a third metal layer corresponding to the second metal layer on the through hole. The invention saves process steps, reduces the total thickness of the first metal interlamination medium layer and the second metal interlamination medium layer of the CMOS sensor and improves the sensitivity of the CMOS image sensor.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly a kind of cmos sensor and manufacture method thereof.
Background technology
Cmos image sensor (CMOS Image Sensor, CIS) higher and produce in order to overcome charge-coupled device (CCD) manufacturing process complexity and energy consumption, used the CMOS manufacturing technology, adopted the quantity MOS transistor corresponding with the quantity of unit picture element in the Semiconductor substrate.CIS can be integrated in pixel unit array and peripheral circuit on the same chip owing to adopted the CMOS technology, compares with CCD, and CIS has that volume is little, in light weight, low in energy consumption, programming makes things convenient for, be easy to control and advantage that average unit cost is low.
In being the american documentation literature of US2008/0265295A1, publication number can find a kind of manufacturing process of conventional images transducer.As shown in Figure 1, cmos image sensor comprises substrate 100, is positioned at photoelectricity active area 110, the transistor active area 120 of substrate 100 and the shallow trench isolation regions 101 of isolating photoelectricity active area 110 and transistor active area 120; Be positioned at the transistor surfaces of active regions gate regions 102, be positioned at the side wall 103 on gate regions 102 both sides; Be positioned at the interlayer dielectric layer 130 of substrate 100 surfaces and covering gate polar region 102 and side wall 103; Be positioned at the first metal layer 105, second metal level 107 and the 3rd metal level 109 of interlayer dielectric layer 130; First contact hole 104 that connects the first metal layer 105 and gate regions 102 connects second contact hole 106 of the first metal layer 105 and second metal level 107, connects the 3rd contact hole 108 of second metal level 107 and the 3rd metal level 109; The electric capacity that is positioned at interlayer dielectric layer 130 and is electrically connected with the 3rd metal level 109, described electric capacity comprise first electrode 113, second electrode 111 and the dielectric layer 112 between first electrode 113 and second electrode 111; The 4th contact hole 114 that connects second electrode 111 and the 3rd metal level 109.
As everyone knows, a parameter weighing the cmos image sensor performance is susceptibility (Sensitivity), described susceptibility and incident light arrive the inversely proportional relation of distance of photoelectricity active area 110, in other words, if the described interlayer dielectric layer 130 that includes the first metal layer 105, second metal level 107, the 3rd metal level 109, first contact hole 104, second contact hole 106, the 3rd contact hole 108 and electric capacity is thin more, described cmos image sensor susceptibility is high more.
Summary of the invention
The problem that the present invention solves provides a kind of manufacture method of cmos sensor, can reduce the gross thickness of dielectric layer and second metal interlamination medium layer between the first metal layer, improves the cmos image sensor susceptibility.
For addressing the above problem, the invention provides a kind of manufacture method of cmos sensor, comprising: substrate is provided; Form the first metal layer at described substrate surface; Form dielectric layer between the first metal layer that covers described substrate and described the first metal layer in described substrate and described the first metal layer surface; Between described the first metal layer, form first conductive plunger corresponding in the dielectric layer with described the first metal layer; The dielectric layer surface forms second metal level and capacitor first electrode between described the first metal layer; Form second metal interlamination medium layer that covers dielectric layer, described second metal level and described capacitor first electrode between described the first metal layer at dielectric layer, described second metal level and described capacitor first electrode surface between described the first metal layer; In described second metal interlamination medium layer, form the groove that exposes described capacitor first electrode; Dielectric layer is formed on sidewall and bottom at described groove; In described second metal interlamination medium layer, form the through hole that exposes described second metal level; With metal filled described groove and through hole; On groove, form second electrode of answering, on through hole, form three metal level corresponding with described second metal level with described capacitor first electrode pair.
The present invention also provides a kind of cmos sensor, comprising: substrate; Be positioned at suprabasil the first metal layer; Be positioned in the substrate and cover dielectric layer between the first metal layer of the first metal layer; Be positioned at first electrode of the capacitor on the dielectric layer and second metal level between the first metal layer; First conductive plunger that connects the first metal layer and second metal level; Be positioned at second metal interlamination medium layer on the dielectric layer and covering capacitor first electrode and second metal level between the first metal layer; Be positioned at the U type dielectric layer on capacitor first electrode; Be positioned at the conductive electrode of U type dielectric layer; Be positioned at capacitor second electrode on the conductive electrode and second metal interlamination medium layer; Be positioned at the 3rd metal level on second metal interlamination medium layer; Second conductive plunger that connects second metal level and the 3rd metal level.
Compared with prior art, the present invention has the following advantages: first electrode of capacitor and the first metal layer of cmos sensor are positioned at one deck and by synchronous process and form, second electrode of capacitor and the first metal layer of cmos sensor are positioned at one deck and by synchronous process and form, the dielectric layer of capacitor is a U type structure, not only saved processing step, also reduce the gross thickness of dielectric layer and second metal interlamination medium layer between the first metal layer of cmos sensor, improved the cmos image sensor susceptibility.And the U type dielectric layer of two or more capacitor is between second metal level and the 3rd metal level, U type dielectric layer the corresponding electric capacity that forms compose in parallel a capacitance group, improve the stored charge ability of capacitor, thereby reach the thickness of attenuate U type dielectric layer and reduce by first electrode of capacitor and the spacing of second electrode; Can also reduce the difficulty of filling metal level on the U type dielectric layer of capacitor, make that filling metal in U type dielectric layer is not easy to occur the metal space, has improved the reliability of the capacitor that forms.
Description of drawings
Fig. 1 is the structural representation of imageing sensor in the prior art;
Fig. 2 is the implementing procedure figure of cmos sensor of the present invention in first embodiment;
Fig. 3 to Figure 16 is the manufacturing flow chart of first embodiment of cmos sensor of the present invention;
Figure 17 to Figure 21 figure is the manufacturing flow chart of second embodiment of cmos sensor of the present invention.
Embodiment
By background technology as can be known, if the imageing sensor interlayer dielectric layer is thin more, the susceptibility of imageing sensor is just high more.The present inventor finds, in imageing sensor, the existence of existing capacitance structure makes the further attenuate of thickness of interlayer dielectric layer of imageing sensor, thereby makes the susceptibility of imageing sensor further to improve.
Through a large amount of work, the inventor makes first electrode of electric capacity of imageing sensor and second metal level in the imageing sensor interlayer dielectric layer prepare simultaneously and is positioned at same one deck, and second electrode of the electric capacity of imageing sensor and the 3rd metal level in the imageing sensor interlayer dielectric layer prepare simultaneously and be positioned at same one deck; And the electric capacity of described imageing sensor can be to be made of a plurality of electric capacity parallel connections.Not only reduced the thickness of the interlayer dielectric layer of imageing sensor, and the electric capacity of the imageing sensor of the formation of a plurality of electric capacity parallel connections can also avoid forming the problem that trench fill in the capacitive process easily is formed with slot.
For this reason, the invention provides a kind of manufacture method of cmos sensor.Fig. 2 is the first embodiment process flow diagram of the manufacture method of cmos sensor of the present invention, specifically comprises the steps:
Step S100 provides substrate;
Step S101 forms the first metal layer at described substrate surface;
Step S102 forms dielectric layer between the first metal layer that covers described substrate and described the first metal layer in described substrate and described the first metal layer surface;
Step S103 forms first conductive plunger corresponding with described the first metal layer in the dielectric layer between described the first metal layer;
Step S104, the dielectric layer surface forms second metal level and capacitor first electrode between described the first metal layer, and described second metal level and capacitor first electrode are positioned at same one deck;
Step S105 forms second metal interlamination medium layer that covers dielectric layer, described second metal level and described capacitor first electrode between described the first metal layer at dielectric layer, described second metal level and described capacitor first electrode surface between described the first metal layer;
Step S106 forms the groove that exposes described capacitor first electrode in described second metal interlamination medium layer;
Step S107 forms dielectric layer in the sidewall and the bottom of described groove;
Step S108 forms the through hole that exposes described second metal level in described second metal interlamination medium layer;
Step S109 is with metal filled described groove and through hole;
Step S110 forms second electrode of answering with described capacitor first electrode pair on groove, form three metal level corresponding with described second metal level on through hole, and described second electrode and the 3rd metal level are positioned at same one deck.
Below in conjunction with accompanying drawing, be elaborated for the manufacture method of cmos sensor of the present invention.
At first, with reference to figure 3, substrate 200 is provided, described substrate can or not be patterned substrate for substrate (part that comprises integrated circuit and other elements), the patterning of multi layer substrate (silicon substrate that for example, has covering dielectric and metal film), classification substrate, silicon-on-insulator substrate, epitaxial silicon substrate, section processes.
With reference to figure 4, form the first metal layer 201 on described substrate 200 surfaces.Described the first metal layer 201 is used for being electrically connected with source electrode, grid or the drain electrode of the active area of cmos sensor; Described the first metal layer material is selected from one or several in copper, aluminium, tungsten, nickel, the titanium, the perhaps alloy of above-mentioned metal; The thickness of described the first metal layer 201 is 200 nanometers to 10 micron.
The formation processing step of described the first metal layer 201 comprises: form one deck first metallic film (not shown) on described substrate 200 surfaces, described first thickness of metal film is 200 nanometers to 10 micron, described first metallic film material is selected from one or several in copper, aluminium, tungsten, nickel, the titanium, the perhaps alloy of above-mentioned metal; Form the described first metallic film technology and can be known physical vaporous deposition or chemical vapour deposition technique deposition.
Form the first photoresist figure (not shown) on described first metallic film surface, concrete technology comprises, spin coating photoresist on described first metallic film, then by exposing with transferring on the photoresist on the mask with the first metal layer 201 graphs of a correspondence, utilize developer solution that the photoresist of corresponding site is removed to form and the first metal layer 201 graphs of a correspondence then, form the first photoresist figure.
With the described first photoresist figure is mask, and described first metallic film of etching forms described the first metal layer 201 until exposing substrate 200.Described etching technics can or be a dry etching for known wet etching, is preferably dry etching.
After etching technics is finished, remove the first photoresist figure.The described removal first photoresist figure can adopt known photoresist to remove technology, comprises adopting photoresist to remove solution removal or plasma bombardment removal etc.
With reference to figure 5, form dielectric layer 210 between the first metal layer that covers described substrate 200 and described the first metal layer 201 in described substrate 200 and described the first metal layer 201 surfaces.
With reference to figure 6, between described the first metal layer, form first conductive plunger 211 corresponding in the dielectric layer 210 with described the first metal layer 201.Described conductive plunger 211 act as second metal level 212 (referring to Fig. 7) that is electrically connected the first metal layer 201 and follow-up formation.
Forming first conductive plunger 211 corresponding with described the first metal layer 201 between described the first metal layer in the dielectric layer 210 comprises: the dielectric layer 210 surface formation second photoresist figure (not shown) corresponding with first conductive plunger 211 between described the first metal layer, concrete technology comprises, spin coating photoresist on dielectric layer 210 between described the first metal layer, then by exposing with transferring on the photoresist on the mask with first conductive plunger, 211 graphs of a correspondence, utilize developer solution that the photoresist of corresponding site is removed to form and first conductive plunger, 211 graphs of a correspondence then, form the second photoresist figure.
With the described second photoresist figure is mask, and dielectric layer 210 forms opening until exposing described the first metal layer 201 between the described the first metal layer of etching, and described etching technics can or be a dry etching for known wet etching, is preferably dry etching.
In the present embodiment, dielectric layer 210 forms opening and can adopt dry etch process until exposing described the first metal layer 201 between the described the first metal layer of described etching, carries out in inductively coupled plasma etching apparatus (ICP), and described etching gas comprises C
4F
8, CO, Ar, O
2
Filled conductive material in described opening forms first conductive plunger 211; Described conductive materials is selected from one or several in copper, aluminium, tungsten, nickel, the titanium, perhaps the alloy of above-mentioned metal; The technology of filled conductive material can be physical gas-phase deposition, chemical vapor deposition method and electrochemistry electroplating technique in described opening.In described opening, after the filled conductive material, can also select the dielectric layer 210 and first conductive plunger 211 between CMP (Chemical Mechanical Polishing) process planarization the first metal layer for use, be beneficial to the subsequent technique preparation.
With reference to figure 7, dielectric layer 210 surfaces form second metal level 212 and capacitor first electrode 213 between described the first metal layer, and described second metal level 212 and capacitor first electrode 213 are positioned at same one deck.Described second metal level 212 is used for the transition zone between the 3rd metal level of the first metal layer 201 and follow-up formation, perhaps is used for interconnecting between second metal level 212.
Specifically comprise: dielectric layer 210 surfaces form second metallic film (not shown) between described the first metal layer, described second thickness of metal film is 200 nanometers to 10 micron, described second metallic film material is selected from one or several in copper, aluminium, tungsten, nickel, the titanium, the perhaps alloy of above-mentioned metal; Form the described second metallic film technology and can be known physical vaporous deposition or chemical vapour deposition technique deposition.
Form the 3rd photoresist layer (not shown) on described second metallic film surface, concrete technology comprises, spin coating photoresist on described second metallic film, then by exposing with transferring on the photoresist on the mask with second metal level 212 and capacitor first electrode 213 graphs of a correspondence, utilize developer solution that the photoresist of corresponding site is removed to form and second metal level 212 and capacitor first electrode 213 graphs of a correspondence then, form the 3rd photoresist layer.
With described the 3rd photoresist figure is mask, and described second metallic film of etching forms described second metal level 212 and capacitor first electrode 213 until exposing dielectric layer 210 between the first metal layer.Described etching technics can or be a dry etching for known wet etching, is preferably dry etching.
After etching technics is finished, remove the 3rd photoresist figure.Described removal the 3rd photoresist figure can adopt known photoresist to remove technology, comprises adopting photoresist to remove solution removal or plasma bombardment removal or the like.
Described second metal level 212 and capacitor first electrode 213 form by etching second metallic film, and are positioned at same one deck, have saved processing step.
With reference to figure 8, form second metal interlamination medium layer 220 that covers dielectric layer 210, described second metal level 212 and described capacitor first electrode 213 between described the first metal layer on dielectric layer 210, described second metal level 212 and described capacitor first electrode 213 surfaces between described the first metal layer.
Described second metal interlamination medium layer, 220 thickness are 200 nanometers to 100 micron, and described second metal interlamination medium layer, 220 materials are selected from SiO
2, the BPSG (SiO of boron-doping phosphorus
2), PSG (mixes the SiO of phosphorus
2), the BSG (SiO of boron-doping
2) one or several, the technology of described formation second metal interlamination medium layer 220 can be CVD technology.
With reference to figure 9, in described second metal interlamination medium layer 220, form the groove 214 that exposes described capacitor first electrode 213.
Wherein, form the 4th photoresist layer (not shown) on described second metal interlamination medium layer 220 surfaces, concrete technology comprises, spin coating photoresist on described second metal interlamination medium layer 220, then 214 graphs of a correspondence of the groove on the mask are transferred on the photoresist by exposure, utilize developer solution that the photoresist of corresponding site is removed to form the groove graph of a correspondence then, form the 4th photoresist layer.
With described the 4th photoresist layer is mask, and etching second metal interlamination medium layer 220 forms groove 214 until exposing described capacitor first electrode 213, and described etching technics can or be a dry etching for known wet etching, is preferably dry etching.
In the present embodiment, described second metal interlamination medium layer 220 of described etching is until exposing described capacitor first electrode 213, form groove and can adopt dry etch process, carry out in inductively coupled plasma etching apparatus (ICP), described etching gas comprises C
4F
8, CO, Ar, O
2
Concrete described second metal interlamination medium layer 220 of etching is until exposing described capacitor first electrode 213, the process conditions that form groove 214 are: the chamber pressure of etching apparatus is 10 millitorr to 50 millitorrs, the top radio-frequency power is 200 watts to 500 watts, the bottom radio-frequency power is 150 watts to 300 watts, C
4F
8Flow is that per minute 10 standard cubic centimeters (SCCM) are to per minute 50 standard cubic centimeters, the CO flow is that per minute 100 standard cubic centimeters are to per minute 200 standard cubic centimeters, the Ar flow is that per minute 300 standard cubic centimeters are to per minute 600 standard cubic centimeters, O
2Flow is that per minute 10 standard cubic centimeters are to per minute 50 standard cubic centimeters.Adopt above-mentioned etch technological condition, described second metal interlamination medium layer 220 of etching forms groove 214 until exposing described capacitor first electrode 213.
Described second metal interlamination medium layer 220 of etching is removed the 4th photoresist figure after expose described capacitor first electrode 213, formation groove 214 technologies are finished.Described removal the 4th photoresist figure can adopt known photoresist to remove technology, comprises adopting photoresist to remove solution removal or plasma bombardment removal or the like.
With reference to Figure 10, Figure 11, Figure 12, form dielectric layer in the sidewall and the bottom of described groove 214; In described second metal interlamination medium layer 220, form the through hole 217 that exposes described second metal level 212.
Dielectric layer is formed on described sidewall and bottom at described groove 214; The step that forms the through hole 217 that exposes described second metal level 212 in described second metal interlamination medium layer 220 comprises: at sidewall and the bottom and second metal interlamination medium layer, the 220 surface formation dielectric films 216 of described groove 214; Form the 5th photoresist figure 218 on described dielectric film 216 surfaces; With the 5th photoresist figure 218 is mask, forms the through hole 217 that exposes described second metal level 212; Remove the 5th photoresist figure 218.
Wherein, with reference to Figure 10, at sidewall and the bottom and second metal interlamination medium layer, the 220 surface formation dielectric films 216 of described groove 214; Described dielectric film 216 materials are selected from SiN, SiO
2, SiON, Ta
2O
5, Al
2O
3The insulating material of contour K value, described dielectric film thickness can be 50 dusts to 2 micron; Can be CVD technology at the sidewall of described groove 214 and the technology of bottom and second metal interlamination medium layer, 220 surface formation dielectric films 216.
With reference to Figure 11, form the 5th photoresist figure 218 on described dielectric film 216 surfaces; Form the 5th photoresist figure 218 technologies on described dielectric film 216 surfaces and be included in spin coating photoresist on the described dielectric film 216, then 217 graphs of a correspondence of the through hole on the mask are transferred on the photoresist by exposure, utilize developer solution that the photoresist of corresponding site is removed to form through hole 217 graphs of a correspondence then, form the 5th photoresist layer 218.
With reference to Figure 12, with described the 5th photoresist layer 218 is mask, etching dielectric film 216, second metal interlamination medium layer 220 are until exposing described second metal level 212 successively, form through hole 217, described etching technics can or be a dry etching for known wet etching, is preferably dry etching.
In the present embodiment, described etching dielectric film 216 can adopt dry etch process, carries out in inductively coupled plasma etching apparatus (ICP), and described etching gas comprises C
4F
8, CO, Ar or O
2
The technological parameter of described etching dielectric film 216 is: the chamber pressure of etching apparatus is 10 millitorr to 50 millitorrs, and the top radio-frequency power is 200 watts to 500 watts, and the bottom radio-frequency power is 150 watts to 300 watts, C
4F
8Flow is that per minute 10 standard cubic centimeters (SCCM) are to per minute 50 standard cubic centimeters, the CO flow is that per minute 100 standard cubic centimeters are to per minute 200 standard cubic centimeters, the Ar flow is that per minute 300 standard cubic centimeters are to per minute 600 standard cubic centimeters, O
2Flow is that per minute 10 standard cubic centimeters are to per minute 50 standard cubic centimeters.Adopt above-mentioned etch technological condition, etching dielectric film 216 is until exposing second metal interlamination medium layer 220.
Etching second metal interlamination medium layer 220 forms through hole 217 and can adopt dry etch process until exposing described second metal level 212, carries out in inductively coupled plasma etching apparatus (ICP), and described etching gas comprises C
4F
8, CO, Ar, O
2
The technological parameter of described etching second metal interlamination medium layer 220 is: the chamber pressure of etching apparatus is 10 millitorr to 50 millitorrs, and the top radio-frequency power is 200 watts to 500 watts, and the bottom radio-frequency power is 150 watts to 300 watts, C
4F
8Flow is that per minute 10 standard cubic centimeters (SCCM) are to per minute 50 standard cubic centimeters, the CO flow is that per minute 100 standard cubic centimeters are to per minute 200 standard cubic centimeters, the Ar flow is that per minute 300 standard cubic centimeters are to per minute 600 standard cubic centimeters, O
2Flow is that per minute 10 standard cubic centimeters are to per minute 50 standard cubic centimeters.Adopt above-mentioned etch technological condition, etching second metal interlamination medium layer 220 forms through hole 217 until exposing described second metal level 212.
With reference to Figure 13, remove the 5th photoresist figure 218.Described removal the 5th photoresist figure 218 can adopt known photoresist to remove technology, comprises adopting photoresist to remove solution removal or plasma bombardment removal or the like.
With reference to Figure 14, Figure 15,, form second conductive plunger 221 and the conductive electrode 222 that is positioned on the U type dielectric layer 215 that are positioned on second metal level 212 with metal filled described groove 214 and through hole 217.
With reference to Figure 14, metal filled described groove 214 of described usefulness and through hole 217 form the processing step that is positioned at second conductive plunger 221 on second metal level 212 and is positioned at the conductive electrode 222 on the U type dielectric layer 215 and comprise: at described groove 214 and through hole 217 and dielectric film 216 surface formation metal levels 219; Described metal level 219 materials are selected from one or several in copper, aluminium, tungsten, nickel, the titanium, the perhaps alloy of above-mentioned metal; Described metal level can be the simple layer structure, also can be multiple-level stack layer structure; The technology that forms described metal level can be known physical gas-phase deposition, chemical vapor deposition method and electrochemistry electroplating technique.
In other embodiments, in described groove 214 and through hole 217 and dielectric film 216 surfaces can also form one deck TiN layer, the technology of described formation TiN layer can be physical vaporous deposition or chemical vapour deposition technique deposition, and the thickness of described TiN layer is 5 nanometer to 200 nanometers.In described groove 214 and through hole 217 and the dielectric film 216 surface TiN that act as that form one deck TiN layers make the sidewall of metal level 219 and groove 214 and through hole 217 of follow-up formation that better adhesive attraction be arranged.
Form the tungsten metal level then on TiN, the depositing operation of described tungsten metal level can be chemical vapour deposition technique.Described tungsten metal layer thickness is 300 nanometers to 10 micron.
With reference to Figure 15, adopt chemico-mechanical polishing to remove unnecessary metal level 219 and dielectric film 216, form dielectric layer 215, conductive electrode 222, groove 214 and second conductive plunger 221 until sidewall and bottom at described groove 214.In order to guarantee to remove unnecessary metal level 219 and dielectric film 216 fully, can adopt chemico-mechanical polishing to remove a part of second metal interlamination medium layer 220.
With reference to Figure 16, on groove 214, form and the second corresponding electrode 223 of described capacitor first electrode 213, form on through hole 217 and the 3rd corresponding metal level 224 of described second metal level 212, described second electrode 223 and the 3rd metal level 224 are positioned at same one deck.Described the 3rd metal level 224 is used to connect between second metal level 212 and the 3rd metal level 224 and is connected to each other, and can also provide input window for applied voltage.
Specifically comprise: form the 3rd metallic film (not shown) on described second metal interlamination medium layer 220 surfaces, described the 3rd thickness of metal film is 200 nanometers to 10 micron, described the 3rd metallic film material is selected from one or several in copper, aluminium, tungsten, nickel, the titanium, the perhaps alloy of above-mentioned metal; Form described the 3rd metallic film technology and can be known physical vaporous deposition or chemical vapour deposition technique deposition.
Form the 6th photoresist figure (not shown) on described the 3rd metallic film surface, concrete technology comprises, spin coating photoresist on described the 3rd metallic film, then by exposing with transferring on the photoresist on the mask with second electrode 223 and the 3rd metal level 224 graphs of a correspondence, utilize developer solution that the photoresist of corresponding site is removed to form and second electrode 223 and the 3rd metal level 224 graphs of a correspondence then, form the 6th photoresist figure.
With described the 6th photoresist figure is mask, and described the 3rd metallic film of etching forms described second electrode 223 and the 3rd metal level 224 until exposing second metal interlamination medium layer 220.Described etching technics can or be a dry etching for known wet etching, is preferably dry etching.
After etching technics is finished, remove the 6th photoresist figure.Described removal the 6th photoresist figure can adopt known photoresist to remove technology, comprises adopting photoresist to remove solution removal or plasma reaction etching removal or the like.
Described second electrode 223 and the 3rd metal level 224 form by etching the 3rd metallic film, and are positioned at same one deck, have saved processing step.
Cmos sensor according to above-mentioned processing step forms comprises: substrate 200; Be positioned at the first metal layer 201 in the substrate 200; Be positioned in the substrate 200 and cover dielectric layer 210 between the first metal layer of the first metal layer 201; Be positioned at first electrode 213 of the capacitor on the dielectric layer 210 and second metal level 212 between the first metal layer; First conductive plunger 211 that connects the first metal layer 201 and second metal level 212; Be positioned at second metal interlamination medium layer 220 on the dielectric layer 210 and covering capacitor first electrode 213 and second metal level 212 between the first metal layer; Be positioned at the U type dielectric layer 215 on capacitor first electrode 213; Be positioned at the conductive electrode 222 of U type dielectric layer 215; Be positioned at capacitor second electrode 223 on the conductive electrode 222 and second metal interlamination medium layer 220; Be positioned at the 3rd metal level 224 on second metal interlamination medium layer 220; Second conductive plunger 221 that connects second metal level 212 and the 3rd metal level 224.
The present invention forms first electrode 213 of capacitor when forming second metal level 212, form second electrode 223 of capacitor when forming the 3rd metal level 224, and described second metal level 212 is positioned at same one deck with described first electrode 213, described the 3rd metal level 224 is positioned at same one deck with described second electrode 223, the U type dielectric layer 215 of capacitor is between second metal level 212 and the 3rd metal level 224, the capacitor of described formation is used for interim store electrons, in the circuit working process as the place of the temporary transient store data of some computing circuits.The cmos sensor that the present invention forms has not only been saved processing step, and has reduced the gross thickness of dielectric layer 210 and second metal interlamination medium layer 220 between the first metal layer.
The invention provides a kind of second embodiment of manufacture method of cmos sensor, in a second embodiment, provide substrate; Form the first metal layer at described substrate surface; Form dielectric layer between the first metal layer that covers described substrate and described the first metal layer in described substrate and described the first metal layer surface; Between described the first metal layer, form first conductive plunger corresponding in the dielectric layer with described the first metal layer; The dielectric layer surface forms second metal level and capacitor first electrode between described the first metal layer, and described second metal level and capacitor first electrode are positioned at same one deck; Forming the implementation process that covers second metal interlamination medium layer of dielectric layer, described second metal level and described capacitor first electrode between described the first metal layer at dielectric layer, described second metal level and described capacitor first electrode surface between described the first metal layer can be with reference to first embodiment.
With reference to Figure 17, in described second metal interlamination medium layer, form the groove that exposes described capacitor first electrode, described groove number is at least two,
In present embodiment, be two with groove number and do exemplary giving an example.
Specifically comprise: form photoresist layer (not shown) on described second metal interlamination medium layer 220 surfaces, concrete technology comprises, spin coating photoresist on described second metal interlamination medium layer 220, then 414 graphs of a correspondence of the groove on the mask are transferred on the photoresist by exposure, utilize developer solution that the photoresist of corresponding site is removed to form the groove graph of a correspondence then, form the photoresist figure.
With described photoresist figure is mask, and etching second metal interlamination medium layer 220 forms groove 414 until exposing described capacitor first electrode 213, and described etching technics can or be a dry etching for known wet etching, is preferably dry etching.
In the present embodiment, described second metal interlamination medium layer 220 of described etching exposes described capacitor first electrode 213 until exposing, form groove and can adopt dry etch process, carry out in inductively coupled plasma etching apparatus (ICP), described etching gas comprises C
4F
8, CO, Ar, O
2
Concrete described second metal interlamination medium layer 220 of etching is until exposing described capacitor first electrode 213, the process conditions that form groove 214 are: the chamber pressure of etching apparatus is 10 millitorr to 50 millitorrs, the top radio-frequency power is 200 watts to 500 watts, the bottom radio-frequency power is 150 watts to 300 watts, C
4F
8Flow is that per minute 10 standard cubic centimeters (SCCM) are to per minute 50 standard cubic centimeters, the CO flow is that per minute 100 standard cubic centimeters are to per minute 200 standard cubic centimeters, the Ar flow is that per minute 300 standard cubic centimeters are to per minute 600 standard cubic centimeters, O
2Flow is that per minute 10 standard cubic centimeters are to per minute 50 standard cubic centimeters.Adopt above-mentioned etch technological condition, described second metal interlamination medium layer 220 of etching forms groove 414 until exposing described capacitor first electrode 213.
Described second metal interlamination medium layer 220 is removed the photoresist figure after expose described capacitor first electrode 213, formation groove 414 technologies are finished.Described removal photoresist figure can adopt known photoresist to remove technology, comprises adopting photoresist to remove solution removal or plasma bombardment removal etc.
With reference to Figure 18,19,20,21, form dielectric layer in the sidewall and the bottom of described groove; In described second metal interlamination medium layer, form the through hole that exposes described second metal level; With metal filled described groove and through hole; Form second electrode of answering with described capacitor first electrode pair on the groove, form three metal level corresponding with described second metal level on through hole, described second electrode and the 3rd metal level are positioned at same one deck.Specific implementation process can be with reference to first embodiment.
The present invention forms first electrode 213 of capacitor when forming second metal level 212, form second electrode 223 of capacitor when forming the 3rd metal level 224, and described second metal level 212 is positioned at same one deck with described first electrode 213, described the 3rd metal level 224 is positioned at same one deck with described second electrode 223, the U type dielectric layer 215 of two or more capacitor is between second metal level 212 and the 3rd metal level 224, form two or more electric capacity in parallel, form a capacitance group.The cmos sensor that the present invention forms has not only been saved processing step, reduced the gross thickness of dielectric layer 210 and second metal interlamination medium layer 220 between the first metal layer, the stored charge ability of capacitor be can also improve, thereby thickness and first electrode 213 of capacitor and the spacing of second electrode 223 of attenuate U type dielectric layer 215 reached; And can reduce the difficulty of filling metal on the U type dielectric layer 215 of capacitor, make that filling metal U type dielectric layer 215 in is not easy to occur the space, provides the reliability of the capacitor of formation.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (11)
1. the manufacture method of a cmos sensor comprises:
Substrate is provided;
Form the first metal layer at described substrate surface;
Form dielectric layer between the first metal layer that covers described substrate and described the first metal layer in described substrate and described the first metal layer surface;
Between described the first metal layer, form first conductive plunger corresponding in the dielectric layer with described the first metal layer;
It is characterized in that, also comprise:
The dielectric layer surface forms second metal level and capacitor first electrode between described the first metal layer;
Form second metal interlamination medium layer that covers dielectric layer, described second metal level and described capacitor first electrode between described the first metal layer at dielectric layer, described second metal level and described capacitor first electrode surface between described the first metal layer;
In described second metal interlamination medium layer, form the groove that exposes described capacitor first electrode;
Dielectric layer is formed on sidewall and bottom at described groove;
In described second metal interlamination medium layer, form the through hole that exposes described second metal level;
With metal filled described groove and through hole;
On groove, form second electrode of answering, on through hole, form three metal level corresponding with described second metal level with described capacitor first electrode pair.
2. the manufacture method of cmos sensor according to claim 1 is characterized in that described second metal level and described first electrode are positioned at same one deck, adopts identical technology to finish simultaneously.
3. the manufacture method of cmos sensor according to claim 1 is characterized in that described groove is one or more.
4. the manufacture method of cmos sensor according to claim 1 is characterized in that the dielectric layer of described formation is a U type structure, and the dielectric layer material is selected from the insulating material of high K value, and described thickness of dielectric layers is 50 nanometers to 2 micron.
5. as the manufacture method of cmos sensor as described in the claim 4, it is characterized in that the insulating material of described high K value is selected from SiN, SiO
2, SiON, Ta
2O
5Or Al
2O
3Material.
6. the manufacture method of cmos sensor according to claim 1 is characterized in that described the 3rd metal level and described second electrode are positioned at same one deck, adopts identical technology to finish simultaneously.
7. cmos sensor comprises:
Substrate;
Be positioned at suprabasil the first metal layer;
Be positioned in the substrate and cover dielectric layer between the first metal layer of the first metal layer;
It is characterized in that, also comprise:
Be positioned at first electrode of the capacitor on the dielectric layer and second metal level between the first metal layer;
First conductive plunger that connects the first metal layer and second metal level;
Be positioned at second metal interlamination medium layer on the dielectric layer and covering capacitor first electrode and second metal level between the first metal layer;
Be positioned at the U type dielectric layer on capacitor first electrode;
Be positioned at the conductive electrode of U type dielectric layer;
Be positioned at capacitor second electrode on the conductive electrode and second metal interlamination medium layer;
Be positioned at the 3rd metal level on second metal interlamination medium layer;
Second conductive plunger that connects second metal level and the 3rd metal level.
8. cmos sensor as claimed in claim 7 is characterized in that, described capacitor first electrode and second metal level are positioned at same one deck.
9. cmos sensor as claimed in claim 7 is characterized in that, described U type dielectric layer material is selected from the insulating material of high K value, and described thickness of dielectric layers is 50 nanometers to 2 micron.
10. cmos sensor as claimed in claim 9 is characterized in that the insulating material of described high K value is selected from SiN, SiO
2, SiON, Ta
2O
5Or Al
2O
3Material.
11. cmos sensor as claimed in claim 7 is characterized in that, described capacitor second electrode and the 3rd metal level are positioned at same one deck.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100529438A CN101924074A (en) | 2009-06-11 | 2009-06-11 | CMOS (Complementary Metal Oxide Semiconductor) sensor and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100529438A CN101924074A (en) | 2009-06-11 | 2009-06-11 | CMOS (Complementary Metal Oxide Semiconductor) sensor and manufacturing method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN101924074A true CN101924074A (en) | 2010-12-22 |
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| CN102231381A (en) * | 2011-06-16 | 2011-11-02 | 格科微电子（上海）有限公司 | Complementary metal oxide semiconductor (CMOS) image sensor and forming method |
| CN104465690A (en) * | 2014-12-26 | 2015-03-25 | 上海集成电路研发中心有限公司 | Layout and pixel unit structure and preparing method thereof |
| CN104609359A (en) * | 2013-11-05 | 2015-05-13 | 中芯国际集成电路制造(上海)有限公司 | Method for forming capacitance MEMS inertial sensor |
| CN106887440A (en) * | 2015-12-15 | 2017-06-23 | 格科微电子（上海）有限公司 | Metal interconnection Rotating fields of imageing sensor and forming method thereof |
| WO2023241069A1 (en) * | 2022-06-17 | 2023-12-21 | 无锡华润上华科技有限公司 | Semiconductor device and preparation method therefor |
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2009
- 2009-06-11 CN CN2009100529438A patent/CN101924074A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102231381A (en) * | 2011-06-16 | 2011-11-02 | 格科微电子（上海）有限公司 | Complementary metal oxide semiconductor (CMOS) image sensor and forming method |
| CN104609359A (en) * | 2013-11-05 | 2015-05-13 | 中芯国际集成电路制造(上海)有限公司 | Method for forming capacitance MEMS inertial sensor |
| CN104609359B (en) * | 2013-11-05 | 2016-03-16 | 中芯国际集成电路制造(上海)有限公司 | The formation method of capacitive MEMS inertial sensor |
| CN104465690A (en) * | 2014-12-26 | 2015-03-25 | 上海集成电路研发中心有限公司 | Layout and pixel unit structure and preparing method thereof |
| CN104465690B (en) * | 2014-12-26 | 2018-01-26 | 上海集成电路研发中心有限公司 | Domain, pixel cell structure and preparation method thereof |
| CN106887440A (en) * | 2015-12-15 | 2017-06-23 | 格科微电子（上海）有限公司 | Metal interconnection Rotating fields of imageing sensor and forming method thereof |
| WO2023241069A1 (en) * | 2022-06-17 | 2023-12-21 | 无锡华润上华科技有限公司 | Semiconductor device and preparation method therefor |
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Application publication date: 20101222 |