CN101924037A - Method for manufacturing coreless capsulation substrates - Google Patents
Method for manufacturing coreless capsulation substrates Download PDFInfo
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- CN101924037A CN101924037A CN 200910150829 CN200910150829A CN101924037A CN 101924037 A CN101924037 A CN 101924037A CN 200910150829 CN200910150829 CN 200910150829 CN 200910150829 A CN200910150829 A CN 200910150829A CN 101924037 A CN101924037 A CN 101924037A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Abstract
The invention discloses a method for manufacturing coreless capsulation substrates, which comprises the following steps of: respectively stacking a first metal foil layer, a first dielectric layer and a second metal foil layer on both sides of a temporary core layer sequentially, wherein the first metal foil layer is provided with a smooth surface and a coarse surface, the smooth surface faces the temporary core layer, and the coarse surface faces the first dielectric layer; and patterning each second metal foil layer, and stacking at least one structure-spanning structure. The temporary core layer provides support temporarily during layer spanning. After the layer spanning is completed, the temporary core layer is removed to obtain two coreless capsulation substrates.
Description
[technical field]
The invention relates to a kind of manufacture method of coreless capsulation substrates, particularly relevant for a kind of manufacture method of utilizing the interim core layer of removable formula to increase the coreless capsulation substrates of layer program.
[background technology]
Now, the semiconductor packages industry is in order to satisfy the demand of various high-density packages, develop the packaging structure that various different types gradually, wherein common packaging structure with substrate (substrate) comprises ball grid array packaging structure (ball grid array, BGA), pin array packaging structure (pin grid array, PGA), the crosspoint array packaging structure (land grid array, chip encapsulation construction LGA) or on the substrate (board onchip, BOC) etc.In above-mentioned packaging structure, a upper surface of described substrate carries at least one chip, and several connection pads of chip is electrically connected to several weld pads of the upper surface of described substrate by routing (wire bonding) or projection (bumping) program.Simultaneously, a lower surface of described substrate also must provide a large amount of weld pads, to weld several outputs.Usually, described substrate is a multilayer circuit board, and it is except providing the surface circuit layer forming the required weld pad on upper and lower surface, its inside also have at least one in circuit layer and several vias, with the annexation of the weld pad of rearranging upper and lower surface.Therefore, how to make base plate for packaging, also be an important key technology of encapsulation industry with multilayer circuit.
For example, please refer to shown in Figure 1, it discloses a kind of structure of existing base plate for packaging 10, wherein said base plate for packaging 10 is to be the center with a core layer (core layer) 11, and outwards forms one first circuit layer 12, one first dielectric layer 13, a second circuit layer 14, one second dielectric layer 15, a surface circuit layer 16 and a welding resisting layer 17 respectively in regular turn in the both sides of described core layer 11 by Layer increasing method (build-up).Moreover during increasing layer, described core layer 11 may form several electroplating ventilating holes (plating throughhole) 111 in addition and run through therebetween, to electrically connect described first circuit layer 12 of both sides.Described first dielectric layer 13 may form several vias (conductive via) 131 to be run through therebetween, to electrically connect described first and second circuit layer 12,14.Described second dielectric layer 15 also can form several vias 151 to be run through therebetween, to electrically connect described second circuit layer 14 and surface circuit layer 16.At last, described welding resisting layer 16 forms several openings 161, with the described surface circuit layer 16 of an exposed part, so that several weld pads (being figure number 16 positions) to be provided, so that structure of electric connection (not illustrating) such as bond line, projection or tin balls.
Above-mentioned existing base plate for packaging 10 is widely applied in present manufacturing processes of semiconductor package.Yet,, therefore be necessary further to manage to reduce the integral thickness of described base plate for packaging 10 in order to meet the miniaturization demand of semiconductor packages.Yet, described base plate for packaging 10 inevitably must use the described core layer 11 with adequate thickness during increasing layer, guaranteeing providing enough support strengths, and prevent because of inhomogeneous (warpage) defectives such as warpage that take place of thermal stress (thermal stress).But, use described core layer 11 can take too much thickness space also, cause being unfavorable for reducing the integral thickness of described base plate for packaging 10.On the other hand, when integral thickness is constant, also be difficult to saved thickness space is used for increasing total number of plies of circuit layer, therefore use described core layer 11 also to be unfavorable for improving circuit level by reducing the thickness of described core layer 11.
Die, be necessary to provide a kind of manufacture method of base plate for packaging, to solve the existing in prior technology problem.
[summary of the invention]
Main purpose of the present invention is to provide a kind of manufacture method of coreless capsulation substrates, it is to utilize interim core layer that enough support strengths are provided during increasing layer, and can after increasing layer, remove interim core layer, and then help reducing substrate thickness and improve circuit level.
Secondary objective of the present invention is to provide a kind of manufacture method of coreless capsulation substrates, it is to utilize interim core layer to increase layer, manufacturing simultaneously two groups of coreless capsulation substrates, and then improve speed of production, reduce manufacturing cost and guarantee to increase a layer yield in its both sides.
Another object of the present invention is to provide a kind of manufacture method of coreless capsulation substrates, it is to utilize interim core layer to increase layer, the surface of interim core layer has the metal foil layer that can remove, can directly migrate as the surface circuit layer of coreless capsulation substrates, and then simplify and to increase a layer program, improve and increase layer efficient and the reduction cost of getting the raw materials ready.
In order to achieve the above object, the invention provides a kind of manufacture method of coreless capsulation substrates, it comprises: an interim core layer is provided; Two sides in described interim core layer are piled up one first metal foil layer, one first dielectric layer and second metal foil layer respectively in regular turn, wherein said first metal foil layer has a flat surfaces and a rough surface, described flat surfaces is towards described interim core layer, and described rough surface is towards described first dielectric layer; Each described second metal foil layer is carried out patterning, to form a second circuit layer respectively; Pile up at least one layer reinforced structure outside each described second circuit layer, described layer reinforced structure comprises one and increases layer dielectric layer and and increase a layer metal foil layer; And, remove described interim core layer, to obtain two coreless capsulation substrates, each described coreless capsulation substrates comprises described first metal foil layer, first dielectric layer, second circuit layer and at least one layer reinforced structure at least.
In one embodiment of this invention, in the step of described interim core layer was provided, described interim core layer was the core layer that contains B stage thermosetting resin.
In one embodiment of this invention, in the step that described interim core layer and described first metal foil layer of pressing are provided, each side of described interim core layer has a temporary adhesive surface, to be incorporated into the flat surfaces of described first metal foil layer.
In one embodiment of this invention, after the step of piling up described first metal foil layer, first dielectric layer and second metal foil layer, carry out heat treated, with the viscosity on the temporary adhesive surface of the described interim core layer of permanent removal.
In one embodiment of this invention, in the step that described interim core layer and described first metal foil layer of pressing are provided, each side of described interim core layer has a metal supporting layer, described metal supporting layer has a rough surface and a flat surfaces, the rough surface of described metal supporting layer is incorporated into the surface of described interim core layer, and the flat surfaces of described metal supporting layer is incorporated into the flat surfaces of described first metal foil layer.
In one embodiment of this invention, the thickness of the metal supporting layer of described interim core layer is greater than the thickness of described first metal foil layer.
In one embodiment of this invention, after piling up the step of described layer reinforced structure and before removing the step of described interim core layer, in addition to described layer reinforced structure increase layer dielectric layer and increase that a layer metal foil layer holed, filling perforation and patterning, increase a layer circuit layer to form several vias and.
In one embodiment of this invention, after obtaining the step of described coreless capsulation substrates, in addition to first metal foil layer and first dielectric layer of described coreless capsulation substrates hole, filling perforation and patterning, to form one first circuit layer and several vias.
In one embodiment of this invention, after the step that forms described first circuit layer, on described first circuit layer, form a welding resisting layer (solder mask), and described welding resisting layer carried out patterning, to form several openings, described first circuit layer of an exposed part is to provide several weld pads.
In one embodiment of this invention, after obtaining the step of described coreless capsulation substrates, in addition to described layer reinforced structure increase layer dielectric layer and increase that a layer metal foil layer holed, filling perforation and patterning, increase a layer circuit layer to form several vias and.
In one embodiment of this invention, after forming the described step that increases layer circuit layer, form a welding resisting layer on layer circuit layer described increasing, and described welding resisting layer carried out patterning, to form several openings, the described layer circuit layer that increase of an exposed part is to provide several weld pads.
In one embodiment of this invention, after the step that forms described welding resisting layer and weld pad, form one on the surface of described weld pad and help layer.
In one embodiment of this invention; described help layer be selected from electroless nickel layer, electrogilding layer, electroless nickel platingization gold layer (electroless Ni/Au), immersion silver (immersion silver), immersion tin (immersiontin) or organic protective film (organic solderability preservatives, OSP).
In one embodiment of this invention, described first metal foil layer, second metal foil layer and the thickness that increases layer metal foil layer respectively essence between 10 to 35 microns.
In one embodiment of this invention, described first dielectric layer and the thickness that increases layer dielectric layer respectively essence between 30 to 55 microns.
[description of drawings]
Fig. 1: the schematic diagram of existing base plate for packaging.
Fig. 2 A to 2H: the schematic flow sheet of the manufacture method of the coreless capsulation substrates of first embodiment of the invention.
Fig. 3: the schematic diagram of the manufacture method of the coreless capsulation substrates of second embodiment of the invention.
[embodiment]
For allowing above-mentioned purpose of the present invention, feature and advantage become apparent, preferred embodiment of the present invention cited below particularly, and conjunction with figs. are described in detail below:
Please refer to shown in Fig. 2 A to 2H, the manufacture method of the coreless capsulation substrates of first embodiment of the invention mainly comprises the following step: an interim core layer 20 is provided; Pile up one first metal foil layer 21, one first dielectric layer 22 and second metal foil layer 23 respectively in regular turn in two sides of described interim core layer 20, wherein said first metal foil layer 21 has a flat surfaces 211 and a rough surface 212, described flat surfaces 211 is towards described interim core layer 20, and described rough surface 212 is towards described first dielectric layer 22; Each described second metal foil layer 23 is carried out patterning, to form a second circuit layer 230 respectively; Pile up at least one layer reinforced structure 30 outside each described second circuit layer 230, described layer reinforced structure 30 comprises one and increases layer dielectric layer 31 and and increase layer metal foil layer 32; And, remove described interim core layer 20, to obtain two coreless capsulation substrates 200, each described coreless capsulation substrates 200 comprises described first metal foil layer 21, first dielectric layer 22, second circuit layer 230 and at least one layer reinforced structure 30 at least.
Please refer to shown in Fig. 2 A, the manufacture method first step of the coreless capsulation substrates of first embodiment of the invention is: an interim core layer 20 is provided.In this step, described interim core layer 20 preferably is selected from the core layer that contains B stage thermosetting resin (B-stage thermosetting resin), the core layer that for example contains the B stage epoxy resin, (bismaleimide triazine BT) waits thermosetting resin also may to contain bismaleimide three nitrogen resins in addition.The core layer of the above-mentioned B of containing stage thermosetting resin is by the half-dried back of the A stage thermosetting resin that packing materials such as glass fibre (glass fiber) cloth is immersed in advance raw lacquer (varnish) state and made through thermoplastic.Therefore, each side of described interim core layer 20 all has a temporary adhesive surface 201,202, so that the temporary adhesive of a predetermined extent to be provided.In the present embodiment, described interim core layer 20 can be selected from glass fiber fabric base material epoxy resin copper clad laminate, for example FR-4 or FR-5 etc., but be not limited to this.Described interim core layer 20 increases the required enough support strengths of layer program in order to provide, and therefore must possess adequate thickness, but possess under the preceding topic of enough support strengths, and the present invention does not limit the thickness range of described interim core layer 20.
Shown in Fig. 2 A, manufacture method second step of the coreless capsulation substrates of first embodiment of the invention is: pile up one first metal foil layer 21, one first dielectric layer 22 and second metal foil layer 23 respectively in regular turn in two sides of described interim core layer 20.In this step, described first metal foil layer 21 and second metal foil layer 23 can be made standby by galvanoplastic (electroplating) or roll off method (rolling) in advance, wherein described at least first metal foil layer 21 must have a flat surfaces 211 and a rough surface 212, described flat surfaces 211 is towards described interim core layer 20, and described rough surface 212 is towards described first dielectric layer 22.The effect of above-mentioned stacked arrangement relation with other in hereinafter being described in detail.Moreover described first metal foil layer 21 and second metal foil layer 23 can be drawn materials from metal or alloy such as copper, aluminium, nickel, gold, silver, but are not limited to this.The preferred essence of thickness of described first metal foil layer 21 and second metal foil layer 23 is between 10 to 35 microns.It should be noted that, when selecting glass fiber fabric base material epoxy resin copper clad laminates such as FR-4 or FR-5 for use when described interim core layer 20, the temporary adhesive surface 201,202 of described interim core layer 20 each side is stained with flat surfaces metal foil layer inwardly in advance, its can be directly in order to as described first metal foil layer 21, thereby help reducing the cost or simplify stacking procedure of getting the raw materials ready.Described first dielectric layer, 22 essence comprise the insulating material such as B stage thermosetting resin that possess temporary adhesive, and for example the epoxy resin in B stage or bismaleimide three nitrogen resins (BT) etc. in case of necessity, also can add packing materials such as glass fabric.The preferred essence of the thickness of described first dielectric layer 22 is between 30 to 55 microns.When carrying out the present invention's second step, can finish pile up after, carry out heat treated, make temporary adhesive surface 201,202 its stickiness of permanent removal of described interim core layer 20.At this moment, described temporary adhesive surface 201,202 still can temporaryly be incorporated into the flat surfaces 211 of described first metal foil layer 21, and the rough surface 212 of described first metal foil layer 21 will permanent bond in described first dielectric layer 22, simultaneously described second metal foil layer 23 also can permanent bond in described first dielectric layer 22.
Please refer to shown in Fig. 2 B, the manufacture method third step of the coreless capsulation substrates of first embodiment of the invention is: each described second metal foil layer 23 is carried out patterning, to form a second circuit layer 230 respectively.In this step, the present invention can carry out patterning to described second metal foil layer 23 by existing coating photoresist, mask exposure and developing liquid developing supervisor, to remove described second metal foil layer 23 of a part, thereby forms described second circuit layer 230.In case of necessity, the present invention also can be before patterning (or afterwards), selection is holed and the program of filling perforation, in described first dielectric layer 22, to form several vias (not illustrating), described drilling program is optional from laser or machine drilling, and described filling perforation program is finished by plating mode.Only, in the present embodiment, the present invention is after the 5th step, just forms several vias 221 (shown in Fig. 2 G) in described first dielectric layer 22.The formation of above-mentioned via is not in order to restriction the present invention opportunity.
Please refer to shown in Fig. 2 C, 2D and the 2E, manufacture method the 4th step of the coreless capsulation substrates of first embodiment of the invention is: pile up at least one layer reinforced structure 30,40 outside each described second circuit layer 230.In the present embodiment, the present invention is provided with two groups of described layer reinforced structures 30,40, but its quantity is not limited to this, and it also can be provided with one group, more than three groups or three groups.Described layer reinforced structure 30 comprises one and increases layer dielectric layer 31 and and increase layer metal foil layer 32.Described layer dielectric layer 31 essence that increase are same as described first dielectric layer 22, and same essence comprises the insulating material such as B stage thermosetting resin that possess temporary adhesive, and the preferred essence of thickness is between 30 to 55 microns.Described layer metal foil layer 32 essence that increase are same as described second metal foil layer 23, can draw materials from metal or alloy such as copper, aluminium, nickel, gold, silver equally, and the preferred essence of thickness are between 10 to 35 microns.In the present embodiment, shown in Fig. 2 C, the present invention piles up described layer reinforced structure 30 earlier outside each described second circuit layer 230, and suitable heat treated, so that the described layer dielectric layer 31 that increase is incorporated into described second circuit layer 230, and makes and describedly increase layer metal foil layer 32 toward the outer side.Then, shown in Fig. 2 D, to described layer reinforced structure 30 increase layer dielectric layer 31 and increase that layer metal foil layer 32 holed, processing such as filling perforation and patterning, increase layer circuit layer 320 to form several vias 311 and one.Moreover, shown in Fig. 2 E, way with similar Fig. 2 C, further pile up another described layer reinforced structure 40 outside layer circuit layer 320 again each described increasing, described layer reinforced structure 40 comprises one and increases layer dielectric layer 41 and and increase layer metal foil layer 42, and its essence is same as and describedly increases layer dielectric layer 31 and increase layer metal foil layer 32.In case of necessity, the present invention also can to described increase layer dielectric layer 41 and increase that layer metal foil layer 42 selected to hole, the program of filling perforation and patterning, to form several vias (not illustrating) and another increases a layer circuit layer (not illustrating).Only, in the present embodiment, in order to make stacked structure have symmetry to prevent inhomogeneous warpage (warpage) defective that causes of thermal stress (thermal stress), the present invention is after the 5th step, just makes describedly to increase layer dielectric layer 41 and increase that layer metal foil layer 42 forms several vias 411 and another increases layer circuit layer 420 (shown in Fig. 2 G).
Please refer to shown in Fig. 2 F, 2G and the 2H, manufacture method the 5th step of the coreless capsulation substrates of first embodiment of the invention is: remove described interim core layer 20, to obtain two coreless capsulation substrates 200.In the present embodiment, its viscosity of permanent removal in the heating process is piled up at above-mentioned several in the temporary adhesive surface 201,202 of described interim core layer 20.At this moment, the final bond strength on described flat surfaces 211 and temporary adhesive surface 201,202 will be significantly less than the final bond strength of the described rough surface 212 and first dielectric layer 22.Therefore, shown in Fig. 2 F, the present invention can remove described interim core layer 20 by artificial or simple and easy facility easily, and stay two groups of described coreless capsulation substrates 200, wherein each described coreless capsulation substrates 200 comprises described first metal foil layer 21, first dielectric layer 22, second circuit layer 230 and at least one layer reinforced structure 30,40 at least.In the present embodiment, each described coreless capsulation substrates 200 comprises two groups of described layer reinforced structures 30,40, but is not limited to this.Then, shown in Fig. 2 G, after removing described interim core layer 20, can hole to first metal foil layer 21 and first dielectric layer 22 of each described coreless capsulation substrates 200, filling perforation and patterning, to form one first circuit layer 210 and several vias 221.Simultaneously, to described layer reinforced structure 40 increase layer dielectric layer 41 and increase that layer metal foil layer 42 holed, filling perforation and patterning, increase layer circuit layer 420 to form several vias 411 and one.Subsequently, shown in Fig. 2 H, then can on described first circuit layer 210, form a welding resisting layer (solder mask) 50, and described welding resisting layer 50 carried out patterning, to form several openings 51, described first circuit layer 210 of an exposed part is to provide several weld pads (not indicating).Simultaneously, form another welding resisting layer 50 on layer circuit layer 420 described increasing, and described welding resisting layer 50 is carried out patterning, to form several openings 51, the described layer circuit layer 420 that increase of an exposed part is to provide several weld pads (not indicating).At last; according to product demand; optionally form one and help layer 60 on the surface of the weld pad of described first circuit layer 210 (or increasing layer circuit layer 420); described help layer 60 be can be selected from electroless nickel layer, electrogilding layer, electroless nickel platingization gold layer (electroless Ni/Au), immersion silver (immersion silver), immersion tin (immersion tin) or organic protective film (organic solderability preservatives, OSP).
By above-mentioned first to the 5th step, first embodiment of the invention can utilize described interim core layer 20 that enough support strengths are provided, so that increase a layer program smoothly, and can after increasing layer, remove described interim core layer 20, so the circuit level that helps reducing the integral thickness of described coreless capsulation substrates 200 and improve described coreless capsulation substrates 200.Owing to can manufacture two groups of coreless capsulation substrates 200 simultaneously in the both sides of described interim core layer 20, therefore not only can improve speed of production relatively and reduce manufacturing cost, also can increase layer by two side symmetries, preventing the inhomogeneous warpage defective that is caused of thermal stress really, and then guarantee to increase a layer yield.
Please refer to shown in Figure 3ly, the manufacture method of the coreless capsulation substrates of second embodiment of the invention is similar in appearance to first embodiment of the invention, but the interim core layer 70 that described second embodiment uses is different from the interim core layer 20 of described first embodiment.In a second embodiment, when preparing described interim core layer 70 in advance, each side of described interim core layer 70 has had a metal supporting layer 71 and one first metal foil layer 72.For example, described interim core layer 70 can be selected glass fiber fabric base material epoxy resin copper clad laminates such as special FR-4 or FR-5 for use, that is the surface of described interim core layer 70 each side is stained with the described metal supporting layer 71 and first metal foil layer 72 in advance in regular turn, thereby helps reducing the cost or simplify stacking procedure of getting the raw materials ready.More in detail, described metal supporting layer 71 has a rough surface 711 and a flat surfaces 712, and described first metal foil layer 72 has a flat surfaces 721 and a rough surface 722 simultaneously.In the present invention, the rough surface 711 of described metal supporting layer 71 is incorporated into described interim core layer 70, and wherein said interim core layer 70 can have temporary adhesive surface (not indicating), but also can not have the temporary adhesive surface.Moreover the flat surfaces 712 of described metal supporting layer 71 is incorporated into the flat surfaces 721 of described first metal foil layer 72, and 722 of the rough surfaces of described first metal foil layer 72 are in order to pile up in regular turn in conjunction with one first interlayer electricity, 73 and 1 second metal foil layer 74.Therefore, described metal supporting layer 71 can be greater than the final bond strength of the described metal supporting layer 71 and first metal foil layer 72 with the final bond strength of interim core layer 70.When second embodiment finishes when increasing layer and desiring to remove described interim core layer 70, described interim core layer 70 will be removed together with described metal supporting layer 71, only constitute two groups of coreless capsulation substrates (not illustrating) by described first metal foil layer 72, the first interlayer electricity 73, second metal foil layer 74 and at least one layer reinforced structure (not illustrating).
It should be noted that since the metal supporting layer 71 of described interim core layer 70 only in order to providing a supporting role, so the present invention do not limit the thickness of described metal supporting layer 71, but its thickness is preferably greater than the thickness of described first metal foil layer 72.The preferred essence of the thickness of described first metal foil layer 72 is between 10 to 35 microns.Except the structure difference of described interim core layer 70, the manufacture method of the coreless capsulation substrates of described second embodiment is that essence is same as described first embodiment, so the present invention gives each step that describes described second embodiment in detail no longer in addition.
As mentioned above, when increasing layer, use described core layer 11 compared to the existing base plate for packaging 10 of Fig. 1, cause being unfavorable for reducing shortcomings such as integral thickness or raising circuit level, Fig. 2 A to 2H and the present invention of 3 utilize described interim core layer 20 that enough support strengths are provided during increasing layer, and can after increasing layer, remove described interim core layer 20, thereby the circuit level that helps reducing the integral thickness of described coreless capsulation substrates 200 and improve described coreless capsulation substrates 200.Moreover, owing to can manufacture two groups of coreless capsulation substrates 200 simultaneously in the both sides of described interim core layer 20, therefore not only can improve speed of production relatively and reduce manufacturing cost, also can increase layer by two side symmetries, preventing the inhomogeneous warpage defective that is caused of thermal stress really, and then guarantee to increase a layer yield.In addition, as shown in Figure 3, therefore when the surface of described interim core layer 70 had first metal foil layer 72 that can remove, described first metal foil layer 72 can directly be migrated as the surface circuit layer of follow-up coreless capsulation substrates, can simplify to increase a layer program, raising and increase layer efficient and the reduction cost of getting the raw materials ready.
The present invention is described by above-mentioned related embodiment, yet the foregoing description is only for implementing example of the present invention.Must be pointed out that disclosed embodiment does not limit the scope of the invention.On the contrary, being contained in the spirit of claims and the modification and impartial setting of scope is included in the scope of the present invention.
Claims (15)
1. the manufacture method of a coreless capsulation substrates, it is characterized in that: described manufacture method comprises:
One interim core layer is provided;
Two sides in described interim core layer are piled up one first metal foil layer, one first dielectric layer and second metal foil layer respectively in regular turn, wherein said first metal foil layer has a flat surfaces and a rough surface, described flat surfaces is towards described interim core layer, and described rough surface is towards described first dielectric layer; Each described second metal foil layer is carried out patterning, to form a second circuit layer respectively;
Pile up at least one layer reinforced structure outside each described second circuit layer, described layer reinforced structure comprises one and increases layer dielectric layer and and increase a layer metal foil layer; And
Remove described interim core layer, to obtain two coreless capsulation substrates, each described coreless capsulation substrates comprises described first metal foil layer, first dielectric layer, second circuit layer and at least one layer reinforced structure at least.
2. the manufacture method of coreless capsulation substrates as claimed in claim 1, it is characterized in that: in the step of described interim core layer was provided, described interim core layer was the core layer that contains B stage thermosetting resin.
3. the manufacture method of coreless capsulation substrates as claimed in claim 1, it is characterized in that: in the step that described interim core layer and described first metal foil layer of pressing are provided, each side of described interim core layer has a temporary adhesive surface, to be incorporated into the flat surfaces of described first metal foil layer.
4. the manufacture method of coreless capsulation substrates as claimed in claim 3, it is characterized in that: after the step of piling up described first metal foil layer, first dielectric layer and second metal foil layer, carry out heat treated, with the viscosity on the temporary adhesive surface of the described interim core layer of permanent removal.
5. the manufacture method of coreless capsulation substrates as claimed in claim 1, it is characterized in that: in the step that described interim core layer and described first metal foil layer of pressing are provided, each side of described interim core layer has a metal supporting layer, described metal supporting layer has a rough surface and a flat surfaces, the rough surface of described metal supporting layer is incorporated into the surface of described interim core layer, and the flat surfaces of described metal supporting layer is incorporated into the flat surfaces of described first metal foil layer.
6. the manufacture method of coreless capsulation substrates as claimed in claim 5, it is characterized in that: the thickness of the metal supporting layer of described interim core layer is greater than the thickness of described first metal foil layer.
7. the manufacture method of coreless capsulation substrates as claimed in claim 1, it is characterized in that: after piling up the step of described layer reinforced structure and before removing the step of described interim core layer, in addition to described layer reinforced structure increase layer dielectric layer and increase that a layer metal foil layer holed, filling perforation and patterning, increase a layer circuit layer to form several vias and.
8. the manufacture method of coreless capsulation substrates as claimed in claim 1, it is characterized in that: after obtaining the step of described coreless capsulation substrates, in addition to first metal foil layer and first dielectric layer of described coreless capsulation substrates hole, filling perforation and patterning, to form one first circuit layer and several vias.
9. the manufacture method of coreless capsulation substrates as claimed in claim 8, it is characterized in that: after the step that forms described first circuit layer, on described first circuit layer, form a welding resisting layer, and described welding resisting layer carried out patterning, to form several openings, described first circuit layer of an exposed part is to provide several weld pads.
10. the manufacture method of coreless capsulation substrates as claimed in claim 1, it is characterized in that: after obtaining the step of described coreless capsulation substrates, in addition to described layer reinforced structure increase layer dielectric layer and increase that a layer metal foil layer holed, filling perforation and patterning, increase a layer circuit layer to form several vias and.
11. the manufacture method of coreless capsulation substrates as claimed in claim 10, it is characterized in that: after forming the described step that increases layer circuit layer, form a welding resisting layer on layer circuit layer described increasing, and described welding resisting layer carried out patterning, to form several openings, the described layer circuit layer that increase of an exposed part is to provide several weld pads.
12. the manufacture method as claim 9 or 11 described coreless capsulation substrates is characterized in that: after the step that forms described welding resisting layer and weld pad, form one on the surface of described weld pad and help layer.
13. the manufacture method of coreless capsulation substrates as claimed in claim 12 is characterized in that: the described layer that helps is selected from electroless nickel layer, electrogilding layer, electroless nickel platingization gold layer, immersion silver, immersion tin or organic protective film.
14. the manufacture method of coreless capsulation substrates as claimed in claim 1 is characterized in that: described first metal foil layer, second metal foil layer and the thickness that increases layer metal foil layer are respectively between 10 to 35 microns.
15. the manufacture method of coreless capsulation substrates as claimed in claim 1 is characterized in that: described first dielectric layer and the thickness that increases layer dielectric layer are respectively between 30 to 55 microns.
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| CN104425431A (en) * | 2013-09-03 | 2015-03-18 | 日月光半导体制造股份有限公司 | Substrate structure, encapsulation structure and manufacture method thereof |
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| CN104540339A (en) * | 2014-12-31 | 2015-04-22 | 广州兴森快捷电路科技有限公司 | Core-less board manufacturing component, core-less board and manufacturing method for core-less board |
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| US6447929B1 (en) * | 2000-08-29 | 2002-09-10 | Gould Electronics Inc. | Thin copper on usable carrier and method of forming same |
| US7026059B2 (en) * | 2000-09-22 | 2006-04-11 | Circuit Foil Japan Co., Ltd. | Copper foil for high-density ultrafine printed wiring boad |
| JP4541763B2 (en) * | 2004-01-19 | 2010-09-08 | 新光電気工業株式会社 | Circuit board manufacturing method |
| JP4866268B2 (en) * | 2007-02-28 | 2012-02-01 | 新光電気工業株式会社 | Wiring board manufacturing method and electronic component device manufacturing method |
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| CN102361024A (en) * | 2011-01-13 | 2012-02-22 | 日月光半导体制造股份有限公司 | Semiconductor package with single sided substrate design and manufacturing methods thereof |
| CN102361024B (en) * | 2011-01-13 | 2014-09-17 | 日月光半导体制造股份有限公司 | Semiconductor package with single sided substrate design and manufacturing methods thereof |
| CN104425431A (en) * | 2013-09-03 | 2015-03-18 | 日月光半导体制造股份有限公司 | Substrate structure, encapsulation structure and manufacture method thereof |
| CN104540326A (en) * | 2014-12-31 | 2015-04-22 | 广州兴森快捷电路科技有限公司 | Core-less board manufacturing component and manufacturing method for core-less board |
| CN104540339A (en) * | 2014-12-31 | 2015-04-22 | 广州兴森快捷电路科技有限公司 | Core-less board manufacturing component, core-less board and manufacturing method for core-less board |
| CN104540339B (en) * | 2014-12-31 | 2017-11-17 | 广州兴森快捷电路科技有限公司 | Without core plate manufacture component, without core plate and centreless board manufacturing method |
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