CN101894768A - Manufacturing method of chip provided with bump - Google Patents
Manufacturing method of chip provided with bump Download PDFInfo
- Publication number
- CN101894768A CN101894768A CN2009102035606A CN200910203560A CN101894768A CN 101894768 A CN101894768 A CN 101894768A CN 2009102035606 A CN2009102035606 A CN 2009102035606A CN 200910203560 A CN200910203560 A CN 200910203560A CN 101894768 A CN101894768 A CN 101894768A
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- CN
- China
- Prior art keywords
- wafer
- manufacture method
- chip
- projection
- glued membrane
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
Abstract
The invention discloses a manufacturing method of chip provided with bump. Firstly, a wafer is provided, the wafer is provided with a first surface and a second surface which are arranged oppositely. Secondary, certain thickness of the wafer is removed from the second surface. Then the wafer is placed into a carrier. Besides, the wafer after removing the certain thickness is subject to dicing, so as to form a plurality of chips. And then a plurality of bumps are formed on the first surface of the wafer after dicing. And finally, the wafer formed with bumps is removed from the carrier, so as to separate the chips.
Description
[technical field]
The present invention relates to a kind of manufacture method, relate more specifically to a kind of manufacture method of avoiding the chip of projection damage with chip of projection.
[background technology]
In recent years, along with electronic product is marched toward under compact, multi-functional, the high-speed trend development, the demand of the semiconductor package part of high density and high I/O is cumulative, so the also thinning day by day of chip thickness in the packaging part, effectively to dwindle the overall package size.In the interconnection technique of semiconductor chip, common connected mode comprises that flip-chip bond (flip-chip bonding), routing engage (wire bonding) and winding and engage (tape automated bonding) etc. automatically, in order to chip and substrate electric connection.Wherein the flip-chip bond technology is to utilize projection (bumps) as the media that electrically connects between chip and substrate, compared to the mode that routing engages and winding engages automatically, the flip-chip bond technology has short electrical connection path, and has preferred electric connection quality, more can save the required area of joint chip on the substrate, make and adopt projection, become one of important research and development direction of present industry gradually as the chip ways of connecting.
In at present common manufacture method, for manufacturing efficient and the reduction manufacturing cost that improves chip, the manufacture method of often utilizing crystal circle grade is after forming gate array on the wafer, directly form projection, then carry out steps such as wafer thinning, wafer cutting and chip separation again in the active surface of wafer.Wherein in the step of wafer thinning, industry is to use emery wheel (grinding wheel) widely to carry out brilliant back-grinding at present.Yet in the process of brilliant back-grinding, because emery wheel must apply certain mechanical stress in brilliant back, the projection that often causes being positioned at the active surface of wafer sustains damage, thereby has had influence on the joint quality of flip-chip chip join on substrate.In addition, the projection that is positioned at active surface can make and make suffered mechanical stress skewness when wafer carries out thinning grinding thickness inhomogeneous, thereby become vortex-like depression (dimple) in brilliant antiform.Be the evenness that has reduced crystal column surface, the thickness that has limited wafer thinning like this, under serious situation even the phenomenon that can cause wafer to break.
[embodiment]
For allowing above-mentioned purpose of the present invention, feature and advantage become apparent, preferred embodiment of the present invention cited below particularly, and conjunction with figs. are described in detail below:
According to the manufacture method of the chip with projection of preferred embodiment of the present invention, be after wafer grinds (grinding) and cutting steps such as (dicing), then again projection is formed on the crystal column surface that is placed in the carrier.Below be to propose first, second embodiment as detailed description of the present invention, so these a little embodiment are only in order to as the example explanation, scope that can't limit desire protection of the present invention.Moreover embodiment graphic also omits unnecessary element, shows technical characterstic of the present invention with clear.
First embodiment
Please be simultaneously with reference to Fig. 1 and Fig. 2 A～2H, Fig. 1 illustrates the flow chart according to the manufacture method of the chip of first embodiment of the invention; Fig. 2 A～2H illustrates the schematic diagram according to the manufacture method of first embodiment of the invention respectively.At first, shown in step S1 and Fig. 2 A, provide a wafer 100.Wafer 100 has a first surface 100a and a second surface 100b who is oppositely arranged, and first surface 100a and second surface 100b preferably are respectively a substantial plane.Further, the first surface 100a of wafer 100 defines a plurality of Cutting Roads (dicing channel) C and a plurality of circuit region (circuit region) A, and these a little Cutting Road C are preferably around each circuit region A.
Secondly, carry out step S2, remove wafer 100 1 thickness w1, carry out the thinning (thinning) or the planarization (planarizing) of wafer 100, shown in Fig. 2 B and 2C by second surface 100b.For instance, be to use existing brilliant back-grinding (back-grinding) technology to carry out the thinning of chip 100 among the step S2, for example (Chemical Mechanical Polishing is ground in mechanical polishing (mechanical grinding), chemico-mechanical polishing, CMP), wet etching (wet etching) or the etching of normal pressure air-flow plasma dry chemical (Atmospheric Downstream Plasma Dry Chemical Etching, mode such as ADP-DCE).These a little chip thinning technology are known by being familiar with this technical field person, are no longer given unnecessary details herein.In addition, can utilize one second glued membrane F2 to be attached at the first surface 100a of wafer 100 among the step S2, use the first surface 100a that protection has circuit region A when carrying out brilliant back-grinding, avoid circuit region A scratch and be subjected to chip, particle pollution.Described second glued membrane can be a brilliant back-grinding glued membrane (back-grinding tape).
Then shown in step S3, wafer 100 is arranged in the carrier (frame) (carrier is not illustrated among the figure), described carrier can more comprise one first glued membrane F1, and the second surface 100b of described wafer 100 is attached on the first glued membrane F1.In the present embodiment, when carrier for example is cutting crystal wafer 100 in order to the time supporting wafer 100 the resin annular frame.More carry out removing the step of the second glued membrane F2 among the step S3, shown in Fig. 2 D from first surface 100a.The first glued membrane F1 is in order to the wafer 100 that is adhesively fixed when the cutting crystal wafer 100, and preferably is heat-resisting material, and it is heat-resistingly to reach about 100 ℃ at least.In a preferred embodiment, the first glued membrane F1 can heat-resistingly reach about 200 ℃.
Come, carry out step S4, cutting (dicing) removes the wafer 100 behind the thickness w1, to form a plurality of chips (die) 110, shown in Fig. 2 E and 2F.For example be to utilize blade (sawblade) that Cutting Road C is cut in the present embodiment, and wafer 100 saws are worn (saw through), wafer 100 is divided into a plurality of chips 110.Yet in different embodiment, wafer 100 also can utilize laser to cut apart (laser scribing), or utilizes the mode of dry-etching or Wet-type etching to cut.In the present embodiment, each chip 110 all for example comprises a circuit region A.In addition, after the completing steps S4, the wafer 100 that cutting forms a plurality of chips 110 still is arranged in the carrier, and is adhered on the first glued membrane F1, shown in Fig. 2 F.
Next, the manufacturing method of chip of present embodiment is to enter step S5, forms a plurality of projections (bump) 130 on the first surface 100a of the wafer 100 after the cutting; Also being about to projection 130 is to be formed on each chip 110, shown in Fig. 2 G.In the present embodiment, a plurality of projections 130 of all corresponding configuration of the circuit region A of each chip 110, and these a little projections 130 for example are golden projection (gold stud bump).In the practical application, these a little projections 130 be can utilize the board that engages based on traditional routing and manufacture method plant the ball step, with the terminal gold goal (gold sephere) that forms of gold thread (gold wire) by the application of force, heat or mode that ultrasonic waves engages is connected on the circuit region A, then gold thread is ruptured near the gold goal place, the short point golden projection of (short spike) projection is slightly arranged to form the top.In another embodiment, projection 130 also can be the solder projection (solder bump) of film-forming method or printing reflow formation.In addition, form planarization (flattening) step that and then projection 130 can for example carry out projection afterwards,, make projection have uniform height by having planar pressing altogether in projection 130.Yet also can keep the external form of projection, directly carry out chip 110 and separate and rear manufacture method step.
In the present embodiment because wafer 100 grinds, during thinning step such as etching, the surface of wafer 100 does not have other elements (for example projection 130) is set, therefore brilliant back-grinding glued membrane can directly entirely be attached at the first surface 100a of wafer 100.In the practical application,,, be to avoid taking place the phenomenon that projection 130 is impaired even break because the first surface 100a of wafer 100 is not provided with projection 130 when for example forcing in second surface 100b when carrying out brilliant back-grinding by emery wheel (grinding wheel).In addition, be subjected to the problem that projection 130 external forms influence institute's generation nest shape depression (dimple) in the time of more can avoiding grinding wafer 100, keep the evenness on wafer 100 surfaces.Moreover when on the wafer 100 projection 130 not being set, because first surface 100a and second surface 100b are respectively substantial plane, the mechanical stress when grinding wafer 100 is to be dispersed in wafer 100 surfaces; Wafer 100 when grinding projection 130 and be arranged at the surface more helps the thinning of wafer 100.During actual the grinding, be the thickness that wafer 100 can be ground to about 1mm.
Second embodiment
According to the manufacture method of the chip of second embodiment of the invention and the manufacture method of above-mentioned first embodiment, difference mainly is to remove the precedence of the step of wafer thickness and cutting crystal wafer, and all the other something in common are repeated description no longer.In addition, the graphic middle components identical of two embodiment is to continue to use identical label.In the present embodiment, the step that removes wafer one thickness is to carry out after the cutting crystal wafer step, that is the manufacture method of present embodiment also can be applicable to grind preceding cutting, and (Dicing Before Griding is in manufacture method DBG).
Please be simultaneously with reference to Fig. 3 A～3G, it illustrates the schematic diagram according to the manufacture method of second embodiment of the invention respectively.The manufacture method of present embodiment at first provides wafer 100, and wafer 100 has first surface 100a and the second surface 100b that is oppositely arranged, and first surface 100a has a plurality of Cutting Road C, as shown in Figure 3A.
Then, these a little Cutting Road C are cut, to form a plurality of groove T in first surface 100a, shown in Fig. 3 B and 3C.The depth d of groove T is less than the integral thickness of wafer 100, and the depth d of groove T is in fact greater than the height of the chip of finally wishing to get 110.
Then, the second glued membrane F2 is attached at the first surface 100a of wafer 100, and removes wafer one thickness w2, shown in Fig. 3 D by second surface 100b.Removing behind the described thickness w2 is to expose this a little groove T, uses that wafer 100 is divided into a plurality of chips 110, shown in Fig. 3 E.
Next, the first glued membrane F1 that heat-resisting material is provided is in second surface 100b, and in order to adhesive wafer 100, and the wafer after will cutting 100 is arranged in the carrier, and the second glued membrane F2 is removed from first surface 100a, shown in Fig. 3 F.
Come again, shown in Fig. 3 G, form on the first surface 100a of the wafer 100 of a plurality of projections 130 after removing thickness w2.Shifting out wafer 100 after forming projection 130 from carrier then, and the first glued membrane F1 is removed to separate this a little chips 110 from second surface 100b, shown in Fig. 3 H, so far is to finish the chip 110 with projection 130.
Above-mentioned manufacture method according to second embodiment of the invention, when for example carrying out brilliant back-grinding or carrying out etching coming thinning wafer 100, because the first surface 100a of wafer 100 is not provided with projection 130, it is the thinning that helps wafer 100, and avoid projection 130 impaired, break, avoid producing nest shape depression simultaneously, keep the evenness on wafer 100 surfaces.
Claims (10)
1. manufacture method with chip of projection, it is characterized in that: described manufacture method comprises the following step:
(a) provide a wafer, described wafer has a first surface and a second surface that is oppositely arranged;
(b) remove described wafer one thickness by described second surface;
(c) be provided with on described wafer to a carrier;
(d) cutting removes the described wafer behind the described thickness, to form a plurality of chips;
(e) form a plurality of projections on the described first surface of the described wafer after the cutting; And
(f) the described wafer after described carrier shifts out the described projection of formation is to separate described chip.
2. manufacture method as claimed in claim 1 is characterized in that: the described first surface definition of described wafer has a plurality of Cutting Roads, and described step (d) comprising:
Cut along described Cutting Road, so that described wafer is divided into described chip.
3. manufacture method as claimed in claim 1 is characterized in that: in described step (b), be to utilize the mode of mechanical lapping, chemico-mechanical polishing grinding, dry-etching or Wet-type etching to remove the described thickness of described wafer.
4. manufacture method as claimed in claim 1 is characterized in that: described carrier is to be a framework.
5. manufacture method as claimed in claim 4 is characterized in that: described framework comprises one first glued membrane, and described second surface is to be attached on described first glued membrane.
6. manufacture method as claimed in claim 1 is characterized in that: described step (b) comprising:
Attach one second glued membrane in described first surface.
7. manufacture method with chip of projection, it is characterized in that: described manufacture method comprises the following step:
(a) provide a wafer, described wafer has a first surface and a second surface that is oppositely arranged, and described first surface definition has a plurality of Cutting Roads;
(b) cut along described Cutting Road, to form a plurality of grooves in described first surface;
(c) remove described wafer one thickness by described second surface,, use that described wafer is divided into a plurality of chips to expose described groove;
(d) be provided with on described wafer to a carrier;
(e) form on the described first surface of the described wafer of a plurality of projections after removing described thickness; And
(f) the described wafer after described carrier shifts out the described projection of formation is to separate described chip.
8. manufacture method as claimed in claim 7 is characterized in that: described carrier is to be a framework.
9. manufacture method as claimed in claim 8 is characterized in that: described framework comprises one first glued membrane, and described second surface is to be attached on described first glued membrane.
10. manufacture method as claimed in claim 7 is characterized in that: described step (c) comprising:
Attach one second glued membrane in described first surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009102035606A CN101894768A (en) | 2009-05-20 | 2009-05-20 | Manufacturing method of chip provided with bump |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009102035606A CN101894768A (en) | 2009-05-20 | 2009-05-20 | Manufacturing method of chip provided with bump |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101894768A true CN101894768A (en) | 2010-11-24 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009102035606A Pending CN101894768A (en) | 2009-05-20 | 2009-05-20 | Manufacturing method of chip provided with bump |
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| Country | Link |
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| CN (1) | CN101894768A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103085176A (en) * | 2011-11-03 | 2013-05-08 | 奇景光电股份有限公司 | Wafer cutting method |
| CN105428209A (en) * | 2014-09-12 | 2016-03-23 | 英飞凌科技股份有限公司 | Semiconductor Device Arrangement And A Method For Forming A Semiconductor Device Arrangement |
-
2009
- 2009-05-20 CN CN2009102035606A patent/CN101894768A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103085176A (en) * | 2011-11-03 | 2013-05-08 | 奇景光电股份有限公司 | Wafer cutting method |
| CN103085176B (en) * | 2011-11-03 | 2015-03-25 | 奇景光电股份有限公司 | Wafer cutting method |
| CN105428209A (en) * | 2014-09-12 | 2016-03-23 | 英飞凌科技股份有限公司 | Semiconductor Device Arrangement And A Method For Forming A Semiconductor Device Arrangement |
| CN105428209B (en) * | 2014-09-12 | 2019-05-10 | 英飞凌科技股份有限公司 | Semiconductor device arrangements and the method for being used to form semiconductor device arrangements |
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Application publication date: 20101124 |