CN101866942A - 环状电极及其制造方法 - Google Patents
环状电极及其制造方法 Download PDFInfo
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- CN101866942A CN101866942A CN201010165410.3A CN201010165410A CN101866942A CN 101866942 A CN101866942 A CN 101866942A CN 201010165410 A CN201010165410 A CN 201010165410A CN 101866942 A CN101866942 A CN 101866942A
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- integrated circuit
- conductive filling
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8822—Sulfides, e.g. CuS
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- G—PHYSICS
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- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/021—Formation of switching materials, e.g. deposition of layers
- H10N70/026—Formation of switching materials, e.g. deposition of layers by physical vapor deposition, e.g. sputtering
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/041—Modification of switching materials after formation, e.g. doping
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Shaping switching materials
- H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
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Abstract
本发明揭露一种电极结构及一种制造一集成电路电极的方法,包括形成一包含管状构件的底电极,填充一例如是n型掺杂硅的导电材料,且具有一环状上表面。一碟型绝缘构件由氧化导电填充材料形成在管状构件之上。一可程序电阻材料例如是相变化材料,被沉积与该管状构件的上表面连接。一顶电极与该可程序电阻材料连接。
Description
技术领域
本发明是有关于使用环状电极的根基于可程序化电阻材料,例如相变化存储材料的高密度存储装置,及此种装置的制造方法。
背景技术
硫属化物材料是被广泛地运用于读写光盘片中。而这些材料包括有至少两种固态相,包括如一大部分为非晶态的固态相,以及一大体上为结晶态的固态相。激光脉冲是用于读写光盘片中,以在二种相中切换,并读取此种材料于相变化之后的光学性质。
硫属化物材料也可以由施加电流而导致相变化。此特性也造成使用可程序电阻材料以形成非挥发存储电路。
在相变化存储器中,资料可由相变化材料于施加电流时在非晶状态与结晶状态之间的切换而储存。电流会加热此材料而导致在不同状态间切换。自非晶状态改变为结晶状态的相变化通常是一较低电流的操作。而自结晶状态改变为结非晶状态的相变化,在此称为重置,一般是为一高电流操作。在理想状态下,致使相变化材料从结晶态转变至非晶态的重置电流强度应越低越好。欲降低重置所需的重置电流强度,可由减低在存储器中的主动相变化材料元件的尺寸。相变化存储装置所遭遇的一个问题是因为重置操作所需的电流大小是与必须改变相态的相变化材料的体积相关。因此,使用标准集成电路工艺所制造的存储单元其必须受限于工艺设备的最小特征尺寸。因此,必须开发能够提供次光刻尺寸的技术给存储单元,其或许会欠缺大型、高密度存储装置所需的均匀度与可靠性。
此控制相变化存储单元主动区域尺寸领域发展的一种方法是致力于发展非常小的电极以将电流流经相变化材料的主体。此非常小的电极结构可以诱发相变化于相变化材料的一个小区域发生,如像是香菇头的接点区域。可参阅于2002年8月6日公告的美国专利第6,429,064号“ReducedContact Areas of Sidewall Conductors”、发明人为Wicker;于2002年10月8日公告的美国专利第6,462,353号“Method for Fabricating aSmall Area of Contact Between Electrodes”、发明人为Gilgen;于2002年12月31日公告的美国专利第6,501,111号“Three-Dimensional(3D)Programmable Device”、发明人为Lowrey;于2003年7月1日公告的美国专利第6,563,156号“Memory Elements and Methods for MakingSame”、发明人为Harshfield。
一种可以提供小表面区域接点的底电极结构的型态是环状电极。可参阅于2005年4月19日公告的美国专利第6,881,603号“Phase ChangeMaterial Memory Device”、发明人为Lai;于2005年9月13日公告的美国专利第6,943,365号“Electrically Programmable Memory withReduced Area of Contact and Method for Making Same”、发明人为Lowrey等人;于2007年9月20日公开的美国专利公开第2007/0215852号“Manufacturing Method for Pipe-Shaped Electrode Phase ChangeMemory”、发明人为Lung;于2008年公开的美国专利公开第2008/0203375号“Memory Cell with Memory Element Contacting Ring-Shaped UpperEnd of Bottom Electrode”、发明人为Lung。使用环状电极的一个好处是来自此环状表面的几何形状。特别是,环状表面的直径变异及此环状构件侧壁的厚度在此环状表面对此存储单元的操作特性具有相对小的影响,允许较其它型态具有在一较大阵列之间所能提供的更均匀的存储单元特性。
一个环状电极所产生的问题是因为电极于垂直电流方向上的小截面区域造成的电阻增加。电阻增加会需要更高的电压通过此存储单元才能达成所需的电流,也会因此增加此装置的功耗。此外,在形成一环状电极的工艺中,会形成薄膜侧壁。制造如此的侧壁结构于电极长度方向上具有均匀的厚度是非常困难的,特别是在环状电极所使用的侧壁结构厚度小于30纳米以下时。因此,在此薄膜侧壁中会产生较薄部分其会导致于此环状中的不均匀电流,且甚至是会在此结构中产生不连续处而影响了工艺良率。
因此需要提供一种方法与结构以构成存储单元,此结构具有可程序电阻材料的较小主动区域而可以使用可靠及可再现的工艺技术。
发明内容
本发明包括装置及方法以形成如一存储单元的集成电路的一电极结构,包括一较小的环状接触区域,而仍能维持低电阻和高制造良率。
本发明的一目的为提供一种集成电路装置,包括一管状构件的电极材料而具有环状上表面。此管状构件具有一轴、一第一端及一第二端。电极材料的侧壁构成管状构件,其具有与管状构件轴向正交的一厚度。管状构件的第一端与下方的接触元件连接。最好是,管状构件的第一端与电极材料很接近,其可以是与作为侧壁的材料相同或不同。管状构件的第二端具有一环状表面做为电极的接触表面。一第一层的导电填充材料于该管状构件的该内表面之内,且第一层的导电填充材料包含一导电材料。一第二层的绝缘填充材料于该管状构件的该内表面的该第一层填充材料之上。该第二层的绝缘填充材料可以相对地薄所以管状构件延伸于第一层导电填充材料之外的长度可以是短的。导电填充材料与绝缘填充材料的组合结果是,电极结构的电阻可以被大幅地降低。此外,电极结构在工艺中的可靠性也可以被改善。此导电填充材料可以是掺杂多晶硅,其它硅材料,或是其它材料可以易于被氧化而形成绝缘的氧化物。此绝缘填充材料可以是形成第一导电填充材料的导电填充材料的氧化物。因此,在第一导电填充材料包含硅的例子中,第二绝缘填充材料是包含氧化硅。此完成结构具有一管状构件其因为第一层导电填充材料的导电性而具有相对较低的电阻,同时提供了一个容易制造的管状接点表面。
一存储装置包括一可程序电阻材料与底电极的环状上表面连接。一顶电极形成于可程序电阻材料之上。
本发明亦提供一种制造上述电极的方法。此工艺包含形成具有一管状构件的一电极材料,其具有上述第一层和第二层的薄膜及材料。代表性的工艺包括以介层孔为基础的工艺,其中管状构件是藉由顺形地沉积电极材料于一穿过一绝缘层的图案化介层孔中。第一导电填充材料形成作为介层孔的衬垫而第二绝缘填充材料填入具有衬垫的介层孔中。替代地,一柱状物为基础的工艺也被描述。此工艺包含形成一柱状物,其包含第一填充材料,最好是有一层电极材料于其下。此管状构件藉由顺形地沉积电极材料于此柱状物之上。于沉积一填充层环绕此具有衬垫的柱状物,及研磨此结构以裸露管状构件的环状上表面之后,于管状构件内的第一绝缘填充材料被形成。
在此处所描述的一个工艺中,第二绝缘填充材料是由将导电填充材料的上表面进行氧化或氮化被形成。在一替代实施例中,第二绝缘填充材料是将第一导电填充材料凹陷蚀刻而形成,然后用绝缘填充材料填入凹陷中再研磨表面以将电极的环状表面裸露出来。
为了形成一存储装置,一可程序化电阻材料形成且与底电极的环状上表面连接。一顶电极形成于可程序电阻材料之上而完成此集成电路。
本发明的其它目的和优点,会在下列实施方式的章节中搭配附图被描述。
附图说明
本发明是由申请专利范围所界定。这些和其它目的,特征,和实施例,会在下列实施方式的章节中搭配附图被描述,其中:
图1为根据本发明一实施例具有管状电极与可程序电阻材料耦接的存储单元的剖面示意图。
图2为在图1中环状上表面的电极的上视图。
图3为根据本发明替代实施例具有管状电极与一偏移的可程序电阻材料耦接的存储单元的剖面示意图。
图4显示利用图1中所示的存储元件的存储阵列的示意图。
图5是可应用本发明包含管状电极相变化存储器阵列及其它电路的集成电路的简化方块图
图6至图12为根据本发明第一较佳实施例的管状电极存储单元以介层孔为基础的工艺步骤示意图。
图13至图18为根据本发明第二较佳实施例的管状电极存储单元以柱状物为基础的工艺步骤示意图。
图19至图21显示利用凹陷蚀刻/填充技术来制作第二绝缘填充材料层的工艺步骤示意图。
具体实施方式
为进一步说明各实施例,本发明乃提供有附图。此些附图乃为本发明揭露内容的一部分,其主要是用以说明实施例,并可配合说明书的相关描述来解释实施例的运作原理。配合参考这些内容,本领域具有通常知识者应能理解其它可能的实施方式以及本发明的优点。图中的元件并未按比例绘制,而类似的元件符号通常用来表示类似的元件。
图1为具有一环状上表面的管状电极的相变化存储单元10的剖面示意图。此存储单元10包含一底电极11与一存取结构的终端(图标中为箭头15)连接。此底电极包含一管状构件12其具有一第一端与终端15相邻,及一与第一端相对的第二端。此管状构件12包含一电极材料,例如是氮化钛或是其它电极材料。在此例示的实施例中,此管状构件12内填充有导电材料16,例如是N型掺杂多晶硅,其可以被如以下所述的方式氧化或是氮化。一绝缘填充材料形成一覆盖构件13,包含举例而言该导电材料16的氧化物或是氮化物,包覆此管状构件12上表面的导电材料16。在此例示中,此覆盖构件13包含氧化硅,而导电材料16是包含硅。替代地,此覆盖构件13包含氮化硅,而导电材料16是包含硅。一可程序电阻存储材料14被形成与管状构件12的环状上表面连接。一顶电极18形成且与可程序电阻存储材料14电性连接。
此管状构件12包含侧壁具有一与管状构件轴向正交的厚度,具有一内表面12a及一外表面12b,其是类似圆柱状的。因此,此内表面12a及外表面12b可以被理解为基本上是圆柱表面,通常被定义成表面踪迹为一直线平行地移向一固定线且与一固定曲线相交,其中对一圆柱环绕位于管状构件中心的一固定线,或是轴,且固定曲线是一中心于此固定线的圆形。此圆柱环绕的内表面12a及外表面12b可以被定义为各自的圆环具有一半径差距为此管状构件墙面的厚度,且因此定义出此管状构件的内表面12a及外表面12b直径。在管状构件的实施例中,类似圆柱状的形状,具有一外缘是圆形、椭圆形、长方形或是某种程度的不规则形,依赖形成此管状构件的工艺技术而定。此处所描述的所谓“环状”上表面,因此不必是圆形的,可以是自管状构件剖面的任何形状例如是长方形的,其是由一个称为沟渠状的结构所导致。此管状构件12第一端的厚度T1可以与侧壁的厚度T2不同。替代地,此管状构件可以在第一端具有一开口。
图2为在图1中管状电极11第二端所观察的环状表面19的上视图。此底电极11包含一管状构件12、填充有导电材料16以及氧化物覆盖构件13。此上表面19区域是由管状构件12侧壁的厚度T2所决定,其由管状构件12内外半径(Ri和Ro)的差值所决定。因为管状构件12外半径(Ro)的执会随着使用工艺的变异而在阵列中改变,此上表面19区域的差值仅会在内外半径(Ri和Ro)的差值很小的情况下才会改变。
在此处所描述的实施例中,管状构件包含一电极材料的薄膜于一介层孔的侧边或是柱状物的侧边。因此,此管状构件的侧墙可以十分薄,举例而言,小于30纳米以达到可程序电阻存储装置的可接受表现。此厚度是由顺形沉积此薄膜于介层孔侧边或是柱状物侧边上方的工艺所决定。许多导体可以作为管状构件12的电极材料,例如铝或是铝合金,TiN、TaN、TiAIN或TaAIN。在存储材料层14包含GST(会于以下描述)的实施例中,最好是使用氮化钛或氮化钽,因为其和GST之间具有良好的结合性,且其是半导体工艺中经常使用的材料,并提供在或GST转换的高温下,通常是600-700℃范围,一个良好的扩散阻障层。替代地,此电极材料也可以其它可由Ti、W、Mo、Al、Ta、Cu、Pt、Ir、La、Ni、N、O与Ru等元素族与合金中选择搭配。
在一实施例中,此管状构件材料的选择最好是其不会像导电填充材料16在形成绝缘覆盖构件13的工艺例如是热氧化中,会被氧化或是那么快地氧化,其会于以下的工艺段落中详细描述。替代地,此管状构件材料的选择最好是其不会像导电填充材料16在形成绝缘覆盖构件13的工艺例如是曝露于氨水中,会被氮化或是那么快地氮化。
此处所描述的实施例中存储单元可以使用标准的光刻及薄膜沉积技术来制造,不需要额外的次光刻图案化步骤,就可以达成在程序化时需要改变相态区域的非常小尺寸。此可程序电阻存储材料包含举例而言相变化材料,例如Ge2Sb2Te5或是其它以下所描述的材料。此存储单元10会发生相变化的主动区域是很小的;因此,相变化所需的重置电流大小也是很小的。
图3为图1的替代实施例,其中存储材料14是被图案化,且向底电极环状表面的一侧偏移,减少了介于底电极11与存储材料之间的主动区域接触面积。图3与图1中所示的结构相同,除了存储材料偏移之外。在其它的替代实施例中,一填充材料可以形成于此结构之上,之后再形成沟渠于环状电极的上表面之上。存储材料然后沉积于此沟渠内以形成一存储元件与此电极连接。
在操作上,电流会流经包含此存取装置一端点15、管状构件12侧边及环状表面的一路径,在环状表面会与可程序电阻存储材料14连接。此电流路径还包含顶电极构件18,及任何电路与电极构件18耦接至其上方的存取结构例如是金属线。此主动区域,通常是位于可程序电阻存储材料靠近管状构件的环状表面处,在其中相变化会因电流通过导致的热而发生,可以是非常小,也降低了所需的重置电流大小。更进一步,因为环状表面的几何形状,在管状构件直径的变异以及,管状构件的侧壁厚度变化具有对存储单元特性相对小的影响,允许此结构中相较于其它结构在一较大阵列间的存储单元特性分布是较为均匀的。
如上述在可程序电阻存储材料14的实施例中包含相变化材料,其包含硫属化物(chalcogenide)或其它材料以作为存储材料。硫属化物包括下列四元素的任一种:氧(O)、硫(S)、硒(Se)、以及碲(Te),形成元素周期表上第VI族的部分。硫属化物包括将一硫属元素与一更为正电性的元素或自由基结合而得。硫属化合物合金包括将硫属化合物与其它物质如过渡金属等结合。一硫属化合物合金通常包括一个以上选自元素周期表第六栏的元素,例如锗(Ge)以及锡(Sn)。通常,硫属化合物合金包括下列元素中一个以上的复合物:锑(Sb)、镓(Ga)、铟(In)、以及银(Ag)。许多以相变化为基础的存储材料已经被描述于技术文件中,包括下列合金:镓/锑、铟/锑、铟/硒、锑/碲、锗/碲、锗/锑/碲、铟/锑/碲、镓/硒/碲、锡/锑/碲、铟/锑/锗、银/铟/锑/碲、锗/锡/锑/碲、锗/锑/硒/碲、以及碲/锗/锑/硫。在锗/锑/碲合金家族中,可以尝试大范围的合金成分。此成分可以下列特征式表示:TeaGebSb100-(a+b),其中a与b是代表在所有构成元素中的原子百分比。一位研究员描述了最有用的合金是为,在沉积材料中所包含的平均碲浓度是远低于70%,典型地是低于60%,并在一般型态合金中的碲含量范围从最低23%至最高58%,且最佳是介于48%至58%的碲含量。锗的浓度是约高于5%,且其在材料中的平均范围是从最低8%至最高30%,一般是低于50%。最佳地,锗的浓度范围是介于8%至40%。在此成分中所剩下的主要成分则为锑。上述百分比是为原子百分比,其为所有组成元素加总为100%。(Ovshinky‘112专利,栏10-11)由另一研究者所评估的特殊合金包括Ge2Sb2Te5、GeSb2Te4、以及GeSb4Te7。(Noboru Yamada,“Potential of Ge-Sb-Te Phase-change Optical Disks forHigh-Data-Rate Recording”,SPIE v.3109,pp.28-37(1997))更一般地,过渡金属如铬(Cr)、铁(Fe)、镍(Ni)、铌(Nb)、钯(Pd)、铂(Pt)、以及上述的混合物或合金,可与锗/锑/碲结合以形成一相变化合金其包括有可程序化的电阻性质。可使用的存储材料的特殊范例,是如Ovshinsky‘112专利中栏11-13所述,其范例在此是列入参考。
在某些实施例中,可在硫属化物及其它相变化材料中掺杂物质以改善使用掺杂硫属化物作为存储元件的导电性、转换温度、熔化温度及其它等性质。代表性的掺杂物质为:氮、硅、氧、二氧化硅、氮化硅、铜、银、金、铝、氧化铝、钽、氧化钽、氮化钽、钛、与氧化钛。可参见美国专利第6,800,504号与美国专利申请US 2005/0029502号。
相变化合金可于一第一结构态与第二结构态之间切换,其中第一结构态是指此材料大体上为非晶固相,而第二结构态是指此材料大体上为结晶固相。这些合金是至少为双稳定的(bistable)。此词汇“非晶”是用以指称一相对较无次序的结构,其较之一单晶更无次序性,而带有可侦测的特征如比结晶态更高的电阻值。此词汇“结晶”是用以指称一相对较有次序的结构,其较之非晶态更有次序,因此包括有可侦测的特征例如比非晶态更低的电阻值。典型地,相变化材料可电切换至完全结晶态与完全非晶态之间所有可侦测的不同状态。其它受到非晶态与结晶态的改变而影响的材料特性中包括,原子次序、自由电子密度、以及活化能。此材料可切换成为不同的固态、或可切换成为由两种以上固态所形成的混合物,提供从非晶态至结晶态之间的灰阶部分。此材料中的电性质亦可能随之改变。
相变化材料可利用电脉冲由一相态改变至另一相态。就过去的观察,得知时间较短、振幅较大的脉冲,较倾向将相变化材料转为通常的非晶态;而时间长、振幅较低的脉冲,则易将相变化材料转为通常的结晶态。时间短且振幅高的脉冲,能量较高,足以破坏结晶态的键结,同时缩短时间可防止原子重新排列为结晶态。无须大量实验,即可获得适当的脉冲参数,以应用于特定的相变化材料与装置结构。于此揭露的,相变化材料是指GST,但亦可采用其它种类的相变化材料。适用于PCRAM中的材料是为Ge2Sb2Te5。
其它可以使用于本发明其它实施例的可程序化电阻存储材料包括利用不同晶体变化来决定电阻,或是利用电脉冲来改变电阻状态。举例来说,可使用电阻随机存取存储器(RRAM)的金属氧化物材料,如钨氧化物(WOx)、氧化镍、五氧化二铌、二氧化铜、五氧化二钽、三氧化二铝、氧化钴、三氧化二铁、二氧化铪、二氧化钛、钛酸锶、锆酸锶、钛酸锶钡。其它实施例则可包括用于磁阻随机存取存储器(MRAM)的材料,而磁阻随机存取存储器可以是旋转力矩转移随机存取存储器(STT MRAM)。举例来说,这些材料可以是以下群组至少一种:钴铁硼、铁、钴、镍、钆、镝、钴铁、镍铁、锰砷、锰铋、锰锑、二氧化铬、氧化锰三氧化二铁、氧化铁五氧化二铁、氧化镍三氧化二铁、氧化镁二铁、氧化铕及铁磁性氧化物钇铁石榴石(Y3Fe5O12)。此可参考美国专利公开号第2007/0176251号,其发明名称为“Magnetic Memory Device and Method of Fabricating the Same”,其中的内容乃并入本文作为参考。其它的例子还包括用于可程序化金属存储单元(PMC)的固态电解质材料,或用于纳米离子存储单元的材料,如银掺杂的锗硫化物解质或铜掺杂的锗硫化物解质。此部分请参考N.E.Gilbert等人发表的文章“A macro model of programmable metallizationcell devices”,Solid-State Electronics,49(2005),1813-1819,且其内容乃并入本文作为参考。
用以形成硫属化物材料的例示方法是利用PVD溅镀或磁控溅镀方式,其反应气体为氩气、氮气及/或氦气,压力为1mTorr至100mTorr。此沉积步骤一般是于室温下进行。一长宽比为1-5的准直器可用以改良其填充表现。为了改善其填充表现,亦可使用数十至数百伏特的直流偏压。另一方面,亦可同时合并使用直流偏压以及准直器。
一个使用化学气相沉积来形成硫属化物的例示方法揭露于美国专利公开号第2006/0172067号,其发明名称为“Chemical Vapor Depositionof Chalcogenide Materials”,其中的内容乃并入本文作为参考。
有时需要在真空中或氮气环境中进行一沉积后退火处理,以改良硫属化物材料的结晶态。此退火处理的温度典型地是介于100℃至400℃,而退火时间则少于30分钟。
图4显示一存储阵列的示意图,其可以利用此处所描述的方式来使用。如图4中所示,一共同源极线28、一字符线23及另一字符线24是沿着Y方向大致平行地排列。位线41和42是沿着X方向大致平行地排列。因此,一个Y解码器及字符线驱动器的区块45与字符线23和24耦接。一个X解码器及一组感应放大器的区块46与位线41和42耦接。共同源极线28与存取晶体管50、51、52及53的源极终端耦接。存取晶体管50的栅极与字符线23耦接。存取晶体管51的栅极与字符线24耦接。存取晶体管52的栅极与字符线23耦接。存取晶体管53的栅极与字符线24耦接。存取晶体管50的漏极与管状电极存储单元35的底电极构件32耦接,存储单元35具有一顶电极构件34。顶电极构件34与位线41耦接。类似地,存取晶体管51的漏极与管状电极存储单元36的底电极构件33耦接,存储单元36具有一顶电极构件37。顶电极构件37与位线41耦接。存取晶体管52和53的漏极则是与对应的管状电极存储单元及位线42耦接。如图中所示,共同源极线28是由两列存储单元所分享,其中一列是沿着Y方向安排如图所示。在其它的实施例中,存取晶体管可以由二极管或是其它可以控制电流通过阵列中所选取的装置以读取或写入资料的结构所取代。当然,也可以使用其它型态的存取装置或阵列结构。
图5是可应用本发明的集成电路的简化方块图。集成电路75内的存储器阵列60是使用于一基板上具有管状电极的相变化存储单元。一列解码器61是耦接至多条字符线62,其间并形成电性连接,且该列解码器61是沿着存储器阵列60的列方向排列。一行解码器63是耦接并电性连接至多条沿着存储器阵列60的行排列的多条位线64,以读取或程序化阵列60内的相变化存储单元的数据。地址是通过总线65提供至列解码器61及行解码器63。方块66中的感应放大器与资料输入结构,是通过数据总线67耦接至行解码器63。资料是由集成电路75上的输入/输出端口或其它内部或外部的资料来源,通过资料输入线71传送至方块66的资料输入结构。在此例示实施例中,集成电路亦可包括其它电路74,如一般用途的处理器、特定用途的应用电路或是可提供此薄膜熔丝相变化存储单元阵列所支持的***单芯片功能的多个模块的组合。资料是由方块66中的感应放大器,通过资料输出线72,传送至集成电路75上的输入/输出端口或其它集成电路75内或外的资料目的地。
于本实施例中,一控制器是利用偏压调整状态机构69控制偏压调整供应电压68,如读取、程序化、擦除、擦除验证及程序化验证的电压。此外,控制器亦可利用技术领域中已知的特殊目的逻辑电路来实作。于其它实施方式中,控制器可包括一般用途的处理器以执行计算机程序来控制元件的操作,而该处理器可以实作于相同的集成电路上。于另外的实施方式中,控制器可利用特殊目的逻辑电路与一般用途的处理器的组合来实作。
图6至图12为根据本发明图1所示的管状电极存储单元以介层孔为基础的一较佳实施例的工艺步骤示意图。图6显示一具有上层的基板99,包含一层间介电层118其具有由裸露栓塞120、121的上表面来形成接点122、123以连接底下的存取结构(未于图中显示)与存储单元。此基板可以包含与多种不同的存取结构耦接,或是取代栓塞120、121,如包括圆柱场效晶体管或双极晶体管或二极管,及平面场效晶体管、二极管或双极接面晶体管等。
在代表性的实施例中,层间介电层118包含氧化硅、氮化硅或是掺杂氧化硅材料。栓塞120、121包含钨栓塞。其它型态的导体也可以作为栓塞结构120、121,包含举例而言铝或是铝合金,TiN、TaN、TiAIN或TaAIN。也可以使用其它导体如Ti、W、Mo、Al、Ta、Cu、Pt、Ir、La、Ni、Ru与O等元素族与合金中选择搭配。
图6所示的工艺阶段中,如氧化硅的一填充材料125形成于此基板99的表面之上。填充材料125的厚度是由最终的装置尺寸所决定。对一具有最小特征尺寸为50到100纳米范围的工艺,填充材料125的厚度可以为相同的50到100纳米范围或更厚。此外,也可以使用与后续工艺兼容的其它填充材料。
图7显示下一工艺阶段于图案化及蚀刻介层孔126、127于接点122、123之上后的剖面图。一光刻工艺,或是次光刻工艺可以用来定义介层孔126、127与其下的接点122、123对准。
图8显示下一工艺阶段于使用顺形工艺沉积一电极材料128后的剖面图,此电极材料128可以是如的前所解释过的氮化钛。介层孔126、127侧壁的电极材料128的厚度是由最终的装置尺寸所决定。在一介层孔直径为5到100纳米数量级的实施例中,介层孔126、127侧壁的电极材料的厚度(对应图1中的厚度)T2可以是1到20纳米数量级。
图9显示下一工艺阶段于沉积例如是多晶硅的一硅材料129填入介层孔126、127剩余部分之后的剖面图。在一代表性的实施例中,此硅材料129可以掺杂n型材料例如是磷以如以下所述增进其热氧化的效率。当然,也可以使用其它型态的硅,举例而言包含非晶硅。
图10显示下一工艺阶段,于进行化学机械研磨或是其它平坦化工艺后的剖面图,自此结构的上表面移除了电极材料128和硅材料129,而保留电极材料128作为介层孔的衬垫而硅材料129填入具有衬垫的介层孔中。
图11显示下一工艺阶段,此结构被曝露于氧化环境,其中硅材料129的氧化速率较电极材料128为快。其结果是,氧化覆盖层130、131会形成于介层孔内的硅材料129之上。在使用硅材料129的实施例中,可以使用标准热氧化工艺。替代地氧化工艺包括铝作为导电填充材料而氧化铝作为绝缘填充材料。此外,在其它的替代实施例中,可以使用氮化工艺,例如将材料暴露于氨气中。
之后,假如需要的话,此完成结构可以进行化学机械研磨或是其它平坦化工艺,以自电极材料128的上表面132、133移除任何残留的氧化物或氮化物。
如图12所示,此具有管状接点表面电极的存储单元工艺步骤包含沉积例如是相变化材料的可程序电阻存储材料135,及一顶电极材料136于此可程序电阻材料之上。任何所需的图案化步骤是根据所使用的特定存储单元结构的需求来进行。最后,进行后段工艺以完成此集成电路,包括层间介电填充工艺、金属化工艺、覆盖工艺等等。
图13至图18为根据本发明图1所示的管状电极存储单元以柱状物为基础的一较佳实施例的工艺步骤示意图。图13显示一完成前段工艺的基板99,包含栓塞120、121形成于对应的介层孔内且延伸通过层间介电层118而至上表面。在此阶段中,电极材料150形成于基板99之上,在接着来形成一层硅或是可以被氧化的导电材料151。
选择性的,电极材料150可以进行化学机械研磨或是其它平坦化工艺以提供一较为平坦的电极材料于集成电路的阵列区域中。完成后电极材料150的厚度举例而言可以是在20到100纳米范围之间。此第一电极材料150可以是Ti、Al、W、TiN、Cu或是其它与此工艺兼容的金属,选取具有与栓塞上表面和第二电极良好附着力、与良好稳定性的材料。
之后,一导电硅材料151使用化学气相沉积或是其它业界所熟知的工艺形成。此导电硅材料151的厚度举例而言可以是在50到200纳米范围之间。
图14显示下一工艺阶段,根据此例示工艺,一光刻胶层被沉积及显影以形成光刻胶掩膜,其具有多边形状可为圆形、椭圆形或是正方形,且在光刻工艺的容许范围内与栓塞120、121对准。此光刻胶掩膜被裁减以形成更小的掩膜。举例而言,此光刻胶掩膜可以使用氧气等离子体蚀刻以形成次光刻掩膜,其可以保留此掩膜的多边形状而具有更小的直径。
此更小的掩膜被用来作为定义柱状物152、153的蚀刻掩膜,其包含各自的环状构件,其中包含电极材料层150,及各自的柱状硅构件,其中包含材料层151。在存储单元的实施例中,柱状结构152、153的直径约介于20到50纳米范围之间。此碟状构件的电极材料层150于栓塞120、121之上,以建立与栓塞120、121良好的电性与物理连接。
图15显示下一工艺阶段,于顺形沉积一第二电极层154于此柱状结构152、153及基板表面之上后的剖面图。在例示的工艺中,第二电极层154的材料是与第一电极层150相同。在其它的实施例中,第二电极层154的材料具有较第一电极层150为高的选择性,且具有与可程序电阻材料良好的附着特性。举例而言,第二电极材料可以是TaN、TiN、AlN,或是如铱或锂的氧化物或其材料组合。第二电极层可以使用业界所熟知的技术沉积,例如是化学气相沉积、溅镀或是对此选取材料适用的其它顺形沉积技术。
如图16所示,下一工艺阶段包含非均向性蚀刻第二电极层154以形成柱状结构152、153的侧壁结构,而自基板99表面移除电极材料。
之后,如图17所示,一填充层(于回蚀刻之后的剩余部分标示为165)被沉积再利用化学机械研磨或其它工艺回蚀刻,以形成一阶级低于柱状结构152、153的下且移除柱状结构152、153上方的电极材料以建立此管状构件的高度。于回蚀刻之后,此管状构件的环状上表面156、157被裸露于此完成结构的表面上。在一代表性的实施例中,此管状电极构件的高度约介于80到150纳米范围之间,例如是100纳米。此管状电极构件的电极材料154侧壁厚度约介于10到30纳米范围之间,例如是20纳米。此碟状构件的电极材料150的厚度,举例而言则因此可以是管状电极构件侧壁厚度的至少两倍以上。
图18显示于沉积或是溅镀一顺形层158的GST或是其它可程序电阻材料于填充层165表面上后的结构示意图。GST可以使用准直器在约250℃溅镀而被沉积形成。替代地,GST可以使用金属有机化学气相沉积(MOCVD)工艺被形成。在一代表性的实施例中,此顺形层158包含一薄膜的厚度约介于30到100纳米范围之间。接着,一层电极材料159其可以是与电极材料150相同,被沉积于顺形层158之上,其厚度约介于30到100纳米范围之间。
图19至图21显示利用凹陷蚀刻/填充技术来制作绝缘覆盖构件13的工艺步骤示意图。此阶段是开始于图10或图17的阶段之后,当合适的时候会继续使用图10的元件标号,如同的前所描述的,一化学机械研磨或是其它平坦化步骤,保留电极材料128垫在穿越层125的介层孔内,而导电填充材料129则填充此具有衬垫的介层孔。因此,图19显示于一凹陷蚀刻的结果,其选择性地移除此导电填充材料,且留下一凹陷229。之后,如图20所示,一绝缘填充材料230被沉积于此结构之上,填入凹陷229内。最后,如图21所示,进行一化学机械研磨程序或是其它类似的平坦化程序,所以绝缘填充材料的上表面331被冲洗而具有由电极材料128形成的管状或是沟渠状构件的上表面332。此存储装置的结构可以如上所述地被完成。根据图19至图21的工艺,此绝缘填充材料是由工艺兼容的因素来选取,且不一定要是导电填充材料的氧化物或是氮化物。
在上述的实施例中,管状构件具有侧边在此存储单元的周边是连续的。替代地,也可以形成方形的管状构件,其可以被认定为是沟渠状构件。此外,也可以使用让管状或是沟渠状构件的侧边在此存储单元的周边是不连续的沉积技术,更进一步减少主动区域的体积。
虽然本发明是已参照实施例来加以描述,然本发明创作并未受限于其详细描述内容。替换方式及修改样式是已于先前描述中所建议,且其它替换方式及修改样式将为熟习此项技术的人士所思及。特别是,所有具有实质上相同于本发明的构件结合而达成与本发明实质上相同结果,皆不脱离本发明的精神范畴。因此,所有此等替换方式及修改样式是意欲落在本发明于随附权利要求范围及其均等物所界定的范畴之中。
Claims (10)
1.一种集成电路装置,包括:
一电极,具有一管状构件的一电极材料,其具有一第一端、一第二端与一环状表面于该第二端,其中该管状构件具有一内表面及一外表面;
一第一层的导电填充材料于该管状构件的该内表面之内;以及
一第二层的绝缘填充材料于该第一层导电填充材料之上且延伸至该管状构件的该第二端。
2.如权利要求1所述的集成电路装置,其中该绝缘填充材料的特性是该导电填充材料的一种氧化物或氮化物。
3.如权利要求2所述的集成电路装置,其中该导电填充材料是N型硅。
4.如权利要求1所述的集成电路装置,其中该管状构件在该内表面与外表面之间的厚度小于30纳米。
5.如权利要求1所述的集成电路装置,还包含:
一碟状构件的电极材料邻近该管状构件的该第一端;
一可程序化电阻材料层与该管状构件的该环状表面连接;以及
一第二电极与该可程序化电阻材料层连接。
6.一种制造一集成电路装置中的一电极的方法,包括:
形成一电极包含一管状构件,其具有一第一端、一第二端与一环状表面于该第二端,其中该管状构件具有一内表面及一外表面;
形成一第一层的导电填充材料于该管状构件的该内表面之内;以及
形成一第二层的绝缘填充材料于该管状构件的该内表面内的该第一层导电填充材料之上且延伸至该管状构件的该第二端。
7.如权利要求6所述的制造一集成电路装置中的一电极的方法,其中形成该第二层的绝缘填充材料包括将该导电填充材料进行氧化或氮化之一。
8.如权利要求6所述的制造一集成电路装置中的一电极的方法,其中该导电填充材料具有较该管状构件的该环状表面为高的氧化或氮化速率;该导电填充材料包含硅,而该形成该第二层包括将该硅进行氧化或氮化之一。
9.如权利要求6所述的制造一集成电路装置中的一电极的方法,还包含:
形成一可程序化电阻材料层与该管状构件的该环状表面连接;以及
形成一第二电极与该可程序化电阻材料层连接。
10.如权利要求6所述的制造一集成电路装置中的一电极的方法,其中:
该形成一第一层的导电填充材料的步骤包含形成一结构具有该第一层的导电填充材料的一顶表面与该管状构件的一顶表面齐平,且蚀刻该导电填充材料以在该管状构件内形成一凹陷;以及
该形成一第二层的绝缘填充材料的步骤包含将该绝缘填充材料填入该凹陷中且平坦化该结构以裸露该环状表面。
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US20100264396A1 (en) | 2010-10-21 |
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