CN101848162A - Device and method for transmitting Ethernet data - Google Patents
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Abstract
The invention discloses a device and a method for transmitting Ethernet data. Under the condition that network data transmission is not busy, a datagram is transmitted through a channel with the minimum power consumption by comparing the power consumption needed when the current data is transmitted in different IO interface modes. The device and the method have the advantages that: the transmission power consumption is reduced by making full use of power consumption analysis of the data, and the efficiency of the data transmission is ensured.
Description
Technical field
The application relates to a kind of Ethernet data dispensing device and data transmission method that reduces the transmission power consumption, relates in particular to the interfacing of Ethernet transmission field.
Background technology
Current social, energy-saving and emission-reduction have become human common target.The energy supply in the whole world is limited at present, the present situation that is critical appears in various natural resources storage one after another, for example, required fuel oil and the natural gas quantity of generating electricity constantly reduces, and be known as the various new forms of energy of clear energy sources, development rate can't be filled energy breach again immediately, how to slow down the influence that the energy shortage problem causes, and has become all kinds of technology, product or has used actively effort target.In addition, reduce power consumption, just mean CO2 emissions still less, this has become the emphasis that people pay close attention under the current economic environment of advocating " green, environmental protection ".As Ethernet daily or that business activity is indispensable, also can become the primary emphasis that improves under the trend at this node.
At the correlation technique and the discussion of Ethernet, how concentrate on mostly increased Network Transmission usefulness in the past, how to design faster network chip more at a high speed, made product cost cheaper simultaneously.And the transmission and the disposal ability of raising network chip, the most direct method designs chip faster exactly, improves the dominant frequency of chip, increases the quantity of IO pin etc.But these all will bring the loss on the power consumption, and flower tends to cause the power consumption design margin of the whole network equipment unable to make ends meet in the lifting of the disposal ability of strengthening per 1 network interface.And network switch is because the power consumption electricity consumption increases, naturally also can allow organism temperature promote, cost main naturally, passive cooling mechanism will improve when organism temperature increases, for example driving forced air-cooled radiator fan also can electricity consumption, and use network, data center's machine room of interchanger, the network equipment in a large number, also can be in order to keep machine room optimal operation temperature, and allow air conditioner load increase the weight of, causing more, the multipotency source consumes.
On the other hand, from the angle of application layer, the continuous fusion of network and service has more increased the weight of the power consumption of network processes equipment and has born.Present IT and 3C use the dependence of network are constantly deepened, for example present web2.0 and the various video of carrying out, voice applications is (as IPTV, Online Music, VOD video request program etc.), the user has all had exponential growth with respect in the past application to the access quantity of network data and frequency, directly affects the deal with data amount and the consumed power of the network hardware.Use partly in commerce, each major company is all in application such as the cloud computing of carrying out (Cloud Computing), virtual, cluster computing (Cluster Computing), online shopping, Enterprise's Electronic Commercial, also quickened data center for high speed, the urgent demand of low-power consumption network.
But review present network processes hardware, much still still pursuing performance, Ethernet is from initial 10Mb, 100Mb, develop into present 1Gb, 10Gb or even 100Gb, bandwidth rises with index, and it is double that the disposal ability of chip is not stopped, simultaneously, its power consumption consumption is also going up synchronously with considerable ratio, and this has proposed great challenge to the application scenario (as Embedded Application, data center) of paying attention to performance/power consumption ratio.
Fig. 1 has shown the basic structure of a network processing card, and network processing card is by Ethernet cable RJ-45 interface, transformer, and physical layer (PHY) chip, ethernet controller constitutes.The signal of telecommunication by the I/O of RJ-45 interface passes through transformer coupled to the PHY chip.Typical Ethernet phy chip such as the BCM5461 of broadcom company and the chips such as 88E1111 of marvell company, Ethernet PHY chip links to each other with ethernet controller by gmii interface (RGMII interface, SGMII interface).
GMII is the meaning of GIGABIT Medium Independent Interface, is meant to consider that medium are copper axle, optical fiber, cable etc., because the chip that the related work that these medium are handled all has PHY or is called MAC is finished.GMII is the Ethernet industry standard of IEEE-802.3 definition, is used for Fast Ethernet MAC-block and is connected with various types of PHY.It comprises a data interface, and the management interface between MAC and the PHY.
GMII supports 1,000 million operation, its support still more flexibly, but there is a shortcoming to be because the holding wire that its port is used is too many, so the making of modern switch all can be used other some standards of simplifying out from GMII, such as RGMII, SGMII etc.
Management interface MDIO is a dual signal interface: one is clock signal MDC, and another is data-signal MDIO.By management interface, the upper strata can monitor and control PHY.
RGMII is the gmii interface of simplifying, and it has lacked one times holding wire than the MII interface in the transmitting-receiving of data.SGMII is than RMII line number signal still less, and S represents the meaning of serial.Because it only transmits with a holding wire and sends data, a signal wire transmits is accepted data, and its clock frequency is very high.
In network chip is used, the IO power consumed has accounted for the sizable part of total power consumption, according to measuring and calculating, a common network chip, it is on the IOswitching that consumes externally that nearly 30% power consumption is arranged, but simultaneously, network chip is faced the requirement of more and more higher IO speed again, this just and power consumption formed a pair of contradiction, in the face of such problem, the method for power consumption is transmitted in the solution that the present invention proposes a kind of innovation.
Summary of the invention
Technical problem to be solved by this invention provides a kind of power consumption that reduces transfer of data between Ethernet phy interface chip and the mac chip.
The technical scheme that the present invention adopts in order to solve the problems of the technologies described above provides a kind of Ethernet data dispensing device, comprising: an asynchronous FIFO, be used to store the data message that the slave controller core is sent, and the change over clock territory;
One power consumption calculation and control module are used for reading current message from described asynchronous FIFO, calculate the power consumption data of current message, select the data transmission channel of current message;
One 8bit data bit width Ethernet media access controller module is coupled between described power consumption calculation and control module and the gmii interface;
One 4bit data bit width Ethernet media access controller module is coupled between described power consumption calculation and control module and the RGMII interface;
One 1bit data bit width Ethernet media access controller module is coupled between described power consumption calculation and control module and the SGMII interface;
One phase-locked loop module is in order to produce gmii interface, RGMII interface and the required data clock of SGMII interface;
One MDIO controller module, in order to the phy chip is carried out data read and control,
Described asynchronous fifo comprises a high-water mark, and whether data volume reaches certain thresholding in the fifo in order to indicate;
Described power consumption calculation module comprises a control module, one 8bit power consumption calculation module, one 4bit power consumption calculation module, one 1bit power consumption calculation module and data buffer, control module selects data message to export described 8bit data bit width Ethernet media access controller module or one of 4bit data bit width Ethernet media access controller module or 1bit data bit width Ethernet media access controller module to according to the result of calculation of described 3 power consumption calculation modules.
The present invention also provides a kind of method that is used for transmission data between Ethernet phy interface chip and the mac chip in order to solve the problems of the technologies described above, and this method is carried out following steps:
A. read each byte of network packet successively from fifo, by per 1 bit statistics number of 0,1 upset wherein, a whole frame and multiply by the value that a weight coefficient obtains and transmit required power consumption data as the SGMII interface adds up; Add up the wherein number of 0,1 upset by one group of per 4 bit, the whole frame that adds up transmits required power consumption data as the RGMII interface; By one group of per 8 bit statistics number of 0,1 upset wherein, the whole frame that adds up transmits required power consumption data as gmii interface, and selects above-mentioned 3 interfaces to transmit minimum value in the required power consumption data;
B. judge whether the data in the current transmitting terminal fifo have reached the high water level threshold value;
If the data in the C. current transmitting terminal fifo have reached the high water level threshold value, show that then current network is in busy condition, keep current data transfer port;
If the data in the D. current transmitting terminal fifo do not reach the high water level threshold value, show that then current network is in not busy condition, select data to carry out transfer of data according to described minimum value, and provide the selection control command to the phy chip by the MDIO bus by gmii interface, RGMII interface or SGMII interface;
E. select corresponding ports to carry out the transmission of packet.
Description of drawings
Fig. 1 is the realization block diagram of network processes interface card.
Fig. 2 is that the data receiver of ethernet controller of the present invention inside is to the interface circuit structure chart.
Fig. 3 is the internal circuit configuration figure of power consumption calculation of the present invention and control module.
Fig. 4 is the internal circuit logic diagram of 8bit power consumption calculation module of the present invention.
Fig. 5 is the internal circuit logic diagram of 4bit power consumption calculation module of the present invention.
Fig. 6 is the internal circuit logic diagram of 1bit power consumption calculation module of the present invention.
Embodiment
Fig. 2 has shown that the data receiver of ethernet controller inside is to the interface circuit structure chart.The sending direction data path comprises transmitting terminal fifo (TX FIFO), power consumption calculation and control module, PLL module, MDIO controller module, SGMII MAC module, RGMII MAC module and GMII MAC module.
The TX fifo module is to be the asynchronous First Input First Output buffering area of unit with the bag, and the Ethernet message of exporting from the ethernet controller kernel at first inputs to the TX fifo module, waits for the scheduling output of control module.The TX fifo module is provided with a watermark, and data in the current fifo what show.In one embodiment, the degree of depth of fifo is 16KB, can store the longest Ethernet message of about 10 1500B, watermark can be arranged on the fifo depth location of half, 8KB for example, when the message total amount in the fifo surpassed 8KB, high water mark was changed to 1, when the message total amount in the fifo less than 8KB the time, high water mark is set to 0.Notice that 8KB is a signal value here, in concrete chip is realized, the high water level judgment value can be arranged to fixed value, perhaps be set to a register, dispose by master cpu or other modes.The message input bus width of TX FIFO is 8bit, and each clock cycle can be imported the data of a byte.TX FIFO effect has 2, the message data of first buffer memory output, it two is the conversions that are used for doing clock zone, the internal clocking numeric field data of ethernet controller is delivered on the Ethernet interface clock zone, possible configuration for example internal clocking is 100Mhz, and the interface clock territory is fixed as 125Mhz.The output port of TX FIFO also is 8bit, can be under the read signal effect of controller, and with the clock rate of 125M message data of phase output weekly.
Power consumption calculation and control module are the cores of present embodiment.Fig. 3 has shown the internal structure of power consumption calculation and module, and the full state of sky that message reads logical foundation TX FIFO removes to obtain data message.TXFIFO adds up by complete message, and under the initial condition, TX FIFO is empty, behind a complete data message input TX FIFO, and TX FIFO indication control module fifo current state non-NULL.Message reads the logic determines current state for giving out a contract for a project behind the state, sends read signal, keeps the tail tag note that enables up to a message obtained.
Message reads the parallel message data of logic output 8bit and gives 8bit power consumption calculation module, 4bit power consumption calculation module and 1bit power consumption calculation module.These 3 power consumption calculation modules calculate the current complete sending power consumption statistics of message under 3 kinds of sending modes respectively.
Fig. 4 describes the internal structure of 8bit power consumption calculation module.8bit power consumption calculation module comprises current status register and laststate register, current status register is preserved the message data of current period, the message data of one-period on the laststate register holds, if current period is the start cycle of a message, what then preserve in the laststate register is last last byte number certificate by the message data of GMII port transmission.In each effective message data cycle, XOR 1 is calculated bit position corresponding in the message data of the 8bit that stores in the 8bit data of storing in the laststate register and the current status register, and whether identical (difference means the data upset has taken place, just can produce power consumption in the transmission), obtain current power consumption number for the number addition that wherein is not 0 bit, and the pairing power consumption number of each cycle that in accumulator, adds up.So a whole frame message data is carried out continuous calculating, after last message data passed through current status register, the power consumption data of the packet that accumulator output is complete was to control module.In the starting position of each packet, accumulator is cleared.
Fig. 5 describes the internal structure of 4bit power consumption calculation module.4bit power consumption calculation module comprises current status register and laststate register, current status register is preserved the message data of current period, the low 4bit of the message data of one-period on the laststate register holds, if current period is the start cycle of a message, that then preserve in the laststate register is a last low 4bit by last byte number certificate of the message data of RGMII port transmission.In each effective message data cycle, XOR 1 is calculated bit position corresponding in high 4 message data of storing in the 4bit data of storing in the laststate register and the current status register, and whether identical (difference means the data upset has taken place, just can produce power consumption in the transmission), XOR 2 is calculated bit position corresponding in low 4 the message data of storing in the high 4bit data of storing in the current status registers and the current status register, and whether identical (difference means the data upset has taken place, just can produce power consumption in the transmission), 2 groups of XOR are exported different bit number of each cycle respectively, for wherein not being after the number addition of 0 bit and adding up in accumulator.So a whole frame message data is carried out continuous calculating, after last message data passed through current status register, the power consumption data of the packet that accumulator output is complete was to control module.In the starting position of each packet, accumulator is cleared.
Fig. 6 describes the internal structure of 1bit power consumption calculation module.1bit power consumption calculation module comprises current status register and laststate register, current status register is preserved the message data of current period, the low 1bit of the message data of one-period on the laststate register holds, if current period is the start cycle of a message, that then preserve in the laststate register is a last low 1bit by last byte number certificate of the message data of SGMII port transmission.In each effective message data cycle, XOR 1 is calculated bit position corresponding in the 7th the message data of storing in the 1bit data of storing in the laststate register and the current status register, and whether identical (difference means the data upset has taken place, just can produce power consumption in the transmission), XOR 2 is calculated bit position corresponding in the message data of the 6bit that stores in the 7bit data of storing in the current status registers and the current status register, and whether identical (difference means the data upset has taken place, just can produce power consumption in the transmission), XOR 3 is calculated bit position corresponding in the message data of the 5bit that stores in the 6bit data of storing in the current status registers and the current status register, and whether identical (difference means the data upset has taken place, just can produce power consumption in the transmission), XOR 4 is calculated bit position corresponding in the message data of the 4bit that stores in the 5bit data of storing in the current status registers and the current status register, and whether identical (difference means the data upset has taken place, just can produce power consumption in the transmission), XOR 5 is calculated bit position corresponding in the message data of the 3bit that stores in the 4bit data of storing in the current status registers and the current status register, and whether identical (difference means the data upset has taken place, just can produce power consumption in the transmission), XOR 6 is calculated bit position corresponding in the message data of the 2bit that stores in the 3bit data of storing in the current status registers and the current status register, and whether identical (difference means the data upset has taken place, just can produce power consumption in the transmission), XOR 7 is calculated bit position corresponding in the message data of the 1bit that stores in the 2bit data of storing in the current status registers and the current status register, and whether identical (difference means the data upset has taken place, just can produce power consumption in the transmission), XOR 8 is calculated bit position corresponding in the message data of the 0bit that stores in the 1bit data of storing in the current status registers and the current status register, and whether identical (difference means the data upset has taken place, just can produce power consumption in the transmission), 8 groups of XOR are exported different bit number of each cycle respectively, for wherein not being after the number addition of 0 bit and adding up in accumulator.So a whole frame message data is carried out continuous calculating, after last message data passed through current status register, the power consumption data of the packet that accumulator output is complete was to control module.In the starting position of each packet, accumulator is cleared.Because SGMII is the LVDS difference fiduciary level that adopts, inconsistent with the single-ended level standard of the 2.5V of GMII and RGMII, therefore, also need once to revise operation, with the output result of 1bit power consumption calculation module multiply by a weight coefficient with convert with the same power consumption standard of GMII and RGMII port on, to obtain the power consumption data of SGMII interface.
When message complete pass through 3 power consumption calculation modules after, control module reads the last power consumption data that obtains of 3 power consumption calculation modules respectively, and compares, and selects above-mentioned 3 interfaces to transmit minimum value in the required power consumption data.Control module is carried out channel selecting according to the described minimum value and the current fifo degree of depth, and the algorithm of channel selecting is as follows:
When the fifo high water mark was not 1, if described minimum value comes from 8bit power consumption calculation module, then the current network message sent by gmii interface; If described minimum value comes from 4bit power consumption calculation module, then the current network message sends by the RGMII interface; If described minimum value comes from 1bit power consumption calculation module, then the current network message sends by the SGMII interface.
Be that current message sends from the selected passage of a last message, ignores the power consumption data of current message under 1 the situation when the fifo high water mark.
Control logic is after the selection of making current sendaisle, send the control command of MDIO controller, the SGMII/RGMII/GMII port mask register of control PHY side interface, making the PHY chip switch to corresponding ports to the outer data channel of sheet (notes, some PHY chip need carry out warm reset after setting up channel parameters just can make configuration take-effective, in order to use power consumption saving method of the present invention, need make amendment to the logic of this type of phy chip), behind the control register that has disposed PHY, control logic sends the extremely corresponding sendaisle of message in the buffer memory.
In order further to save power consumption, realize the gigabit Ethernet MAC module of a 8bit bit wide input respectively, the gigabit Ethernet MAC module of the gigabit Ethernet MAC module of a 4bit bit wide input and a 1bit bit wide input, be serially connected in power consumption calculation and control module and gmii interface respectively, between RGMII interface and the SGMII interface.The function of three MAC modules is identical, and difference only is the bit wide and the clock frequency of I/O.The clock frequency of the gigabit Ethernet MAC module of 1bit bit wide input is 8 times of gigabit Ethernet MAC module of 8bit bit wide input.The clock frequency of the gigabit Ethernet MAC module of 4bit bit wide input is 2 times of gigabit Ethernet MAC module of 8bit bit wide input.The clock of each ethernet mac controller drives by the output of phase-locked loop correspondence.Because the present invention has considered power consumption data when selecting data path, therefore, data can be saved a large amount of power consumptions too when handling through MAC.
The gigabit Ethernet media access controller function of the standard of defined is identical in the function that described MAC module realizes and the IEEE802.3 standard, is not described in detail at this.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when doing a little modification and perfect, because protection scope of the present invention is worked as with being as the criterion that claim was defined.
Claims (9)
1. Ethernet data dispensing device comprises:
One asynchronous FIFO is used to store the data message that the slave controller core is sent, and the change over clock territory;
One power consumption calculation and control module are used for reading current message from described asynchronous FIFO, calculate the power consumption data of current message, select the data transmission channel of current message;
One 8bit data bit width Ethernet media access controller (MAC) module is coupled between described power consumption calculation and control module and the gmii interface;
One 4bit data bit width Ethernet media access controller (MAC) module is coupled between described power consumption calculation and control module and the RGMII interface;
One 1bit data bit width Ethernet media access controller (MAC) module is coupled between described power consumption calculation and control module and the SGMII interface;
One phase-locked loop module is in order to produce gmii interface, RGMII interface and the required data clock of SGMII interface;
One MDIO controller module, in order to the phy chip is carried out data read and control,
It is characterized in that:
Described asynchronous fifo comprises a high-water mark, and whether data volume reaches certain thresholding in the fifo in order to indicate;
Described power consumption calculation module comprises a control module, one 8bit power consumption calculation module, one 4bit power consumption calculation module, one 1bit power consumption calculation module and data buffer, control module selects data message to export described 8bit data bit width Ethernet media access controller module or one of 4bit data bit width Ethernet media access controller module or 1bit data bit width Ethernet media access controller module to according to the result of calculation of described 3 power consumption calculation modules.
2. Ethernet data dispensing device according to claim 1 is characterized in that, controller module is judged and ignored current message power consumption calculation data according to described high-water mark, keeps the current data path to select.
3. Ethernet data dispensing device according to claim 1, it is characterized in that, when judging that need carry out data path selects, described control module control MDIO controller module writes control command to the register of PHY chip, and the PHY chip is switched the outer data channel of sheet.
4. Ethernet data dispensing device according to claim 1, it is characterized in that, described 8bit power consumption calculation module calculate the current period message data and last one-period message data the XOR value, and 1 number in this XOR value added up, and get the result of calculation of the accumulated value of a whole frame message data as this 8bit power consumption calculation module.
5. Ethernet data dispensing device according to claim 1, it is characterized in that, the XOR value that described 4bit power consumption calculation module calculating high 4bit message data of current period and last one-period are hanged down the 4bit message data, and the XOR value of high 4bit message data of current period and the low 4bit message data of current period, and 1 number wherein added up, and get the result of calculation of the accumulated value of a whole frame message data as this 4bit power consumption calculation module.
6. Ethernet data dispensing device according to claim 1, it is characterized in that, described 1bit power consumption calculation module calculate current period 7bit message data and last one-period the 0bit message data the XOR value, and the XOR value of each N bit message data of current period and each N-1bit message data of current period, and 1 number wherein added up, and the accumulated value of getting a whole frame message data multiply by the result of calculation of a weight coefficient as this 1bit power consumption calculation module.
7. Ethernet data dispensing device according to claim 1 is characterized in that, the data input and output bit wide of described 8bit data bit width Ethernet media access controller module is 8bit; The data input and output bit wide of described 4bit data bit width Ethernet media access controller module is 4bit; The data input and output bit wide of described 1bit data bit width Ethernet media access controller module is 1bit.
8. Ethernet data dispensing device according to claim 1 is characterized in that, the clock frequency of described 1bit data bit width Ethernet media access controller module is 8 times of described 8bit data bit width Ethernet media access controller module; The clock frequency of described 4bit data bit width Ethernet media access controller module is 2 times of described 8bit data bit width Ethernet media access controller module.
9. method that is used between Ethernet phy interface chip and the mac chip transmission data, this method is carried out following steps:
A. read each byte of network packet successively from fifo, by per 1 bit statistics number of 0,1 upset wherein, a whole frame and multiply by the value that a weight coefficient obtains and transmit required power consumption data as the SGMII interface adds up; Add up the wherein number of 0,1 upset by one group of per 4 bit, the whole frame that adds up transmits required power consumption data as the RGMII interface; By one group of per 8 bit statistics number of 0,1 upset wherein, the whole frame that adds up transmits required power consumption data as gmii interface, and selects above-mentioned 3 interfaces to transmit minimum value in the required power consumption data;
B. judge whether the data in the current transmitting terminal fifo have reached the high water level threshold value;
If the data in the C. current transmitting terminal fifo have reached the high water level threshold value, show that then current network is in busy condition, keep current data transfer port;
If the data in the D. current transmitting terminal fifo do not reach the high water level threshold value, show that then current network is in not busy condition, select data to carry out transfer of data according to described minimum value, and provide the selection control command to the phy chip by the MDIO bus by gmii interface, RGMII interface or SGMII interface;
E. select corresponding ports to carry out the transmission of packet.
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