CN101832831A - Piezoresistive sensor chip and manufacture method thereof - Google Patents
Piezoresistive sensor chip and manufacture method thereof Download PDFInfo
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- CN101832831A CN101832831A CN201010152895A CN201010152895A CN101832831A CN 101832831 A CN101832831 A CN 101832831A CN 201010152895 A CN201010152895 A CN 201010152895A CN 201010152895 A CN201010152895 A CN 201010152895A CN 101832831 A CN101832831 A CN 101832831A
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Abstract
The invention relates to a piezoresistive sensor chip which has convenient production, low cost and high yield and precision. The piezoresistive sensor chip comprises a pressure film layer, a substrate, a piezoresistor and a metal lead, wherein the piezoresistor and the metal lead are arranged on the upper surface of the pressure film layer; and the substrate is arranged on the lower surface of the pressure film layer. The piezoresistive sensor chip is characterized in that the substrate is specifically a silicon substrate; the pressure film layer comprises a bottom polycrystalline silicon film and an upper oxidation layer; and the lower surface of the bottom polycrystalline silicon film is arranged on the upper surface of the silicon substrate.
Description
Technical field
The present invention relates to art of pressure sensors, be specially a kind of piezoresistance sensor chip, the present invention also provides the method for making of making this piezoresistance sensor chip.
Background technology
MEMS(micromechanics electronics) pressure transducer is the earliest an one of product in the microelectromechanical systems, is divided into pressure resistance type, condenser type and piezoelectric type or the like according to principle of work.Piezoresistive pressure sensor is because of it has that highly sensitive, response speed is fast, good reliability, be easy to advantage such as integrated and obtained widespread use in fields such as space flight, medicine equipment and automotive electronics.
Existing body silicon pressure sensor chip, its substrate of glass need by bonding technology realize and the pressure sensitive film on upper strata between encapsulation, cause the production difficulty of this structure big, production cost is high, and easily produce waste product, yield rate is low; And because the thermal expansivity of silicon and glass does not match, all the pressure transducer more than surface micromachined is a lot of greatly to cause the pressure transducer sensitivity temperature coefficient of body micromachined and the temperature coefficient of zero output, and it uses, and real error is big, degree of accuracy is not high.
In addition, existing body silicon pressure sensor chip must carry out the anisotropic wet deep etch to the silicon chip back in manufacturing process, could satisfy the demand of lower range test behind the attenuate, waste areas a large amount of on the silicon chip like this, caused the waste of material, made the production cost height.
Summary of the invention
At the problems referred to above, the invention provides a kind of piezoresistance sensor chip, it is convenient for production, cost is low, and yield rate height, degree of accuracy height.
Its technical scheme is such:
It comprises pressure rete, substrate, force sensing resistance, metal lead wire, described force sensing resistance, metal lead wire are installed on the upper surface of described pressure rete, described substrate is loaded on the lower surface of described pressure rete, it is characterized in that: described substrate is specially substrate silicon, described pressure rete comprises the polysilicon film of bottom, the oxide layer on upper strata, and the polysilicon film lower surface of described bottom is loaded on the upper surface of described substrate silicon.
It is further characterized in that: vacuum chamber of its middle formation of upper surface sealing back of the lower surface of described polysilicon film and described substrate silicon;
The polysilicon film of described bottom has the corrosion hole of perforation, is full of in the described corrosion hole and the identical material of described upper strata oxide layer;
Described force sensing resistance is specially the force sensing resistance bar that the polycrystalline silicon membrane of coating described upper strata oxide layer forms through dry etching;
The pressure rete position of described vacuum chamber correspondence specifically is divided into film district, Liang Qu, and described beam district lateral arrangement is in the center on described vacuum chamber top, and described film district is symmetrically arranged in vertical both sides of described Liang Qu;
Described film district is lower than described Liang Qu, and the underlying polysilicon film in described film district exposes, described Liang Qu comprise polysilicon film, the upper strata of bottom oxide layer, coat the silicon nitride layer on the oxide layer of described upper strata;
Described force sensing resistance bar is symmetrically arranged in cross central line both sides, described beam district, and the upper strata of described force sensing resistance bar is coated with described silicon nitride layer, and described metal lead wire is communicated with described force sensing resistance bar by fairlead.
A kind of method for making of piezoresistance sensor chip is characterized in that:
In substrate silicon upper surface growth oxide layer, the oxide layer in photoetching and the big film of corrosion back of the body district is being carried on the back big film regioselectivity growth PSG (mixing the cryogenic oxidation silicon of phosphorus) as sacrifice layer, and is being anti-carved the oxide layer in the big film of non-back of the body district, at substrate silicon upper surface growing polycrystalline silicon film; Photoetching is also corroded the corrosion hole of polysilicon film, and releasing sacrificial layer is with the thick SiO of method deposit 2um of PECVD (plasma enhanced chemical vapor deposition)
2Stop up corrosion hole, and carry out densification; The deposit polysilicon membrane anti-carves resistance area in its front, and forms the polysilicon resistance bar behind the dry etching; Deposit Si
3N
4, photoetching Liang Qu, the oxide layer of losing the film district with the carving of beam district is to form beam-membrane structure; Lithography fair lead anti-carves the Al lead-in wire behind the steaming Al, finish metal lead wire after the alloying.
It is further characterized in that:
Its concrete steps are as follows:
A, substrate silicon is carried out standard cleaning, the back deionized water rinsing, and, then,, make the SiO of its single face formation 0.1um～1um with silicon slice placed thermal oxide in oxidation furnace of handling well with drier dehydration, oven dry
2Oxide layer;
Big film district is carried on the back in b, photoetching, the SiO in the big film of corrosion back of the body district
2Oxide layer continues use the TMAH(Tetramethylammonium hydroxide) corrosion carries on the back the silicon 1um～5um in big film district; After cleaning, use deionized water rinsing, enter the PSG (mixing the cryogenic oxidation silicon of phosphorus) that grows in PECVD (plasma enhanced chemical vapor deposition) stove after the oven dry, as sacrifice layer, wherein the thickness of Sheng Chang PSG is identical with the thickness of the silicon in the big film of the back of the body that is corroded district;
C, anti-carve the back of the body big film district, corrode the oxide layer in the big film of non-back of the body district.After cleaning, use deionized water rinsing, enter the LPCVD(low-pressure chemical vapor deposition after the oven dry) polysilicon film of growth bottom in the stove, thickness 1～5um;
D, lithographic definition corrosion hole, the method for employing dry etching is removed the polysilicon in the corrosion hole, again with dry method or wet process releasing sacrificial layer PSG (mixing the cryogenic oxidation silicon of phosphorus); After cleaning, use deionized water rinsing, enter the SiO that grows in PECVD (plasma enhanced chemical vapor deposition) stove after the oven dry
2Film 1～5um puts into oxidation furnace and carries out stopping up corrosion hole after the fine and close oxidation processes;
E, the silicon chip that will finish above-mentioned operation are put into the LPCVD(low-pressure chemical vapor deposition) stove preparing polysilicon film 0.1～1um, by boron diffusion or the injection of boron ion polysilicon membrane is mixed, for activator impurity spreads or injects the defective that causes with eliminating, and impurity is evenly distributed, with silicon slice placed annealing in process under 950 ℃～1200 ℃ nitrogen protections;
The shape of f, lithographic definition polysilicon force sensing resistance bar, the method that adopts dry etching stays the force sensing resistance bar of polysilicon in desired location, uses deionized water rinsing after cleaning; Entering the LPCVD(low-pressure chemical vapor deposition after the oven dry) Si grows in the stove
3N
4Film 0.1～1um;
G, photoetching Liang Qu remove silicon nitride layer, the oxide layer in film district successively, form beam-membrane structure;
H, lithography fair lead anti-carve the Al lead-in wire behind the steaming Al, finish metal lead wire after the alloying.
In the present invention, because described substrate is specially substrate silicon, itself and the thermal expansivity of pressure rete and the temperature coefficient of zero output are complementary, and guarantee the degree of accuracy height in the use; After using this method, it need not to carry out bonding technology, and it is convenient for production and production cost is low; In addition, this invention need not again the silicon chip back to be carried out the anisotropic wet deep etch and be need not attenuate, so the material of its needed silicon chip is little, and the utilization factor height of silicon chip, greatly reduce production cost.
Description of drawings
Fig. 1 is the structural representation of front view of the present invention;
Fig. 2 is the structural representation (force sensing resistance bar position is the silicon nitride on illustrated position, omission force sensing resistance bar upper strata) of the vertical view of Fig. 1;
Fig. 3 be manufacture craft process flow diagram of the present invention (wherein penultimate stride is Fig. 2 to B-B that should step to cut-open view, all the other steps for the A-A of respectively corresponding its step of Fig. 2 to cut-open view).
Embodiment
Its structure is seen Fig. 1, Fig. 2: it comprises pressure rete, substrate, force sensing resistance, metal lead wire 2, force sensing resistance, metal lead wire 2 are installed on the upper surface of pressure rete, substrate is loaded on the lower surface of pressure rete, substrate is specially substrate silicon 3, the pressure rete comprises the polysilicon film 4 of bottom, the oxide layer 5 on upper strata, and polysilicon film 4 lower surfaces of bottom are loaded on the upper surface of substrate silicon 3; Vacuum chamber 6 of its middle formation of upper surface sealing back of the lower surface of polysilicon film 4 and substrate silicon 3; The polysilicon film 4 of bottom has the corrosion hole 7 of perforation, is full of the material identical with the oxide layer 5 on upper strata in the corrosion hole 7; Force sensing resistance is specially the force sensing resistance bar 8 that the polycrystalline silicon membrane of coating the upper strata oxide layer forms through dry etching; The pressure rete position of vacuum chamber 6 correspondences specifically is divided into film district 9, beam district 10, and beam district 10 lateral arrangement are in the center on vacuum chamber 6 tops, and film district 9 is symmetrically arranged in vertical both sides in beam district 10; Film district 9 is lower than beam district 10, and the underlying polysilicon film 4 in film district 9 exposes, beam district 10 comprise polysilicon film 4, the upper strata of bottom oxide layer 5, coat the silicon nitride 11 on the upper strata oxide layer 5; Force sensing resistance bar 8 is symmetrically arranged in 10 cross central line both sides, beam district, and the upper strata of force sensing resistance bar 8 is coated with silicon nitride 11, and metal lead wire 2 is communicated with force sensing resistance bar 8 by fairlead 1.
Its manufacture craft flow process is seen Fig. 3:
Specific embodiment is as follows:
Embodiment one:
A, substrate silicon 3 is carried out standard cleaning, the back deionized water rinsing, and with the drier dehydration, dry.Then, the substrate silicon of handling well 3 is placed on thermal oxide in the oxidation furnace, single face forms the SiO of 0.1um
2Oxide layer 13.
Big film district is carried on the back in b, photoetching, the SiO in the big film of corrosion back of the body district
2Oxide layer 13, continuation TMAH(Tetramethylammonium hydroxide) the silicon 1um in the big film of corrosion back of the body district, after cleaning, use deionized water rinsing, enter the PSG (mixing the cryogenic oxidation silicon of phosphorus) of growth 1um in PECVD (plasma enhanced chemical vapor deposition) stove after the oven dry, as sacrifice layer 14.
C, anti-carve the back of the body big film district, corrode the oxide layer 13 in the big film of non-back of the body district, through cleaning after, use deionized water rinsing, enter the LPCVD(low-pressure chemical vapor deposition after the oven dry) polysilicon film 4 of the bottom of growing in the stove, thickness 1um.
D, on the polysilicon film 4 of bottom lithographic definition corrosion hole 7, the method of employing dry etching is removed the polysilicon in the corrosion hole 7, again with dry method or wet process releasing sacrificial layer 14, after cleaning, use deionized water rinsing, enter the SiO that grows in PECVD (plasma enhanced chemical vapor deposition) stove after the oven dry
2Film 1um as upper strata oxide layer 5, puts into oxidation furnace and carries out stopping up corrosion hole 7 after the fine and close oxidation processes.
E, the silicon chip that will finish above-mentioned operation are put into the LPCVD(low-pressure chemical vapor deposition) stove preparing polysilicon film 0.1um; by boron diffusion or the injection of boron ion polysilicon membrane is mixed; for activator impurity spreads or injects the defective that causes with eliminating; and impurity is evenly distributed; with silicon slice placed annealing in process under 950 ℃ of nitrogen protections, generate and treat corrosion layer 12.
F, on bag corrosion layer 12 shape of lithographic definition polysilicon force sensing resistance bar 8, the method of employing dry etching stays the force sensing resistance bar 8 of polysilicon in desired location, after cleaning, use deionized water rinsing, enter the LPCVD(low-pressure chemical vapor deposition after the oven dry) grown silicon nitride layer 11 in the stove, thickness 0.1um.
G, photoetching beam district 10 remove silicon nitride layer 11, the upper strata oxide layer 5 in film district 9 successively, form beam-membrane structure.
H, lithography fair lead 12 anti-carve the Al lead-in wire behind the steaming Al, finish metal lead wire 2 after the alloying.
Embodiment two:
A, substrate silicon 3 is carried out standard cleaning, the back deionized water rinsing, and with the drier dehydration, dry.Then, the substrate silicon of handling well 3 is placed on thermal oxide in the oxidation furnace, single face forms the SiO of 0.5um
2Oxide layer 13.
Big film district is carried on the back in b, photoetching, the SiO in the big film of corrosion back of the body district
2Oxide layer 13, continuation TMAH(Tetramethylammonium hydroxide) the silicon 3um in the big film of corrosion back of the body district, after cleaning, use deionized water rinsing, enter the PSG (mixing the cryogenic oxidation silicon of phosphorus) of growth 3um in PECVD (plasma enhanced chemical vapor deposition) stove after the oven dry, as sacrifice layer 14.
C, anti-carve the back of the body big film district, corrode the oxide layer 13 in the big film of non-back of the body district, through cleaning after, use deionized water rinsing, enter the LPCVD(low-pressure chemical vapor deposition after the oven dry) polysilicon film 4 of the bottom of growing in the stove, thickness 1um.
D, on the polysilicon film 4 of bottom lithographic definition corrosion hole 7, the method of employing dry etching is removed the polysilicon in the corrosion hole 7, again with dry method or wet process releasing sacrificial layer 14, after cleaning, use deionized water rinsing, enter the SiO that grows in PECVD (plasma enhanced chemical vapor deposition) stove after the oven dry
2Film 3um as upper strata oxide layer 5, puts into oxidation furnace and carries out stopping up corrosion hole 7 after the fine and close oxidation processes.
E, the silicon chip that will finish above-mentioned operation are put into the LPCVD(low-pressure chemical vapor deposition) stove preparing polysilicon film 0.5um; by boron diffusion or the injection of boron ion polysilicon membrane is mixed; for activator impurity spreads or injects the defective that causes with eliminating; and impurity is evenly distributed; with silicon slice placed annealing in process under 1100 ℃ of nitrogen protections, generate and treat corrosion layer 12.
F, on bag corrosion layer 12 shape of lithographic definition polysilicon force sensing resistance bar 8, the method of employing dry etching stays the force sensing resistance bar 8 of polysilicon in desired location, after cleaning, use deionized water rinsing, enter the LPCVD(low-pressure chemical vapor deposition after the oven dry) grown silicon nitride layer 11 in the stove, thickness 0.5um.
G, photoetching beam district 10 remove silicon nitride layer 11, the upper strata oxide layer 5 in film district 9 successively, form beam-membrane structure.
H, lithography fair lead 12 anti-carve the Al lead-in wire behind the steaming Al, finish metal lead wire 2 after the alloying.
Embodiment three:
A, substrate silicon 3 is carried out standard cleaning, the back deionized water rinsing, and with the drier dehydration, dry.Then, the substrate silicon of handling well 3 is placed on thermal oxide in the oxidation furnace, single face forms the SiO of 1um
2Oxide layer 13.
Big film district is carried on the back in b, photoetching, the SiO in the big film of corrosion back of the body district
2Oxide layer 13, continuation TMAH(Tetramethylammonium hydroxide) the silicon 5um in the big film of corrosion back of the body district, after cleaning, use deionized water rinsing, enter the PSG (mixing the cryogenic oxidation silicon of phosphorus) of growth 5um in PECVD (plasma enhanced chemical vapor deposition) stove after the oven dry, as sacrifice layer 14.
C, anti-carve the back of the body big film district, corrode the oxide layer 13 in the big film of non-back of the body district, through cleaning after, use deionized water rinsing, enter the LPCVD(low-pressure chemical vapor deposition after the oven dry) polysilicon film 4 of the bottom of growing in the stove, thickness 5um.
D, on the polysilicon film 4 of bottom lithographic definition corrosion hole 7, the method of employing dry etching is removed the polysilicon in the corrosion hole 7, again with dry method or wet process releasing sacrificial layer 14, after cleaning, use deionized water rinsing, enter the SiO that grows in PECVD (plasma enhanced chemical vapor deposition) stove after the oven dry
2Film 5um as upper strata oxide layer 5, puts into oxidation furnace and carries out stopping up corrosion hole 7 after the fine and close oxidation processes.
E, the silicon chip that will finish above-mentioned operation are put into the LPCVD(low-pressure chemical vapor deposition) stove preparing polysilicon film 1um; by boron diffusion or the injection of boron ion polysilicon membrane is mixed; for activator impurity spreads or injects the defective that causes with eliminating; and impurity is evenly distributed; with silicon slice placed annealing in process under 1200 ℃ of nitrogen protections, generate and treat corrosion layer 12.
F, on bag corrosion layer 12 shape of lithographic definition polysilicon force sensing resistance bar 8, the method of employing dry etching stays the force sensing resistance bar 8 of polysilicon in desired location, after cleaning, use deionized water rinsing, enter the LPCVD(low-pressure chemical vapor deposition after the oven dry) grown silicon nitride layer 11 in the stove, thickness 1um.
G, photoetching beam district 10 remove silicon nitride layer 11, the upper strata oxide layer 5 in film district 9 successively, form beam-membrane structure.
H, lithography fair lead 12 anti-carve the Al lead-in wire behind the steaming Al, finish metal lead wire 2 after the alloying.
Claims (9)
1. piezoresistance sensor chip, it comprises pressure rete, substrate, force sensing resistance, metal lead wire, described force sensing resistance, metal lead wire are installed on the upper surface of described pressure rete, described substrate is loaded on the lower surface of described pressure rete, it is characterized in that: described substrate is specially substrate silicon, described pressure rete comprises the polysilicon film of bottom, the oxide layer on upper strata, and the polysilicon film lower surface of described bottom is loaded on the upper surface of described substrate silicon.
2. a kind of piezoresistance sensor chip according to claim 1 is characterized in that: vacuum chamber of its middle formation of upper surface sealing back of the lower surface of described polysilicon film and described substrate silicon.
3. a kind of piezoresistance sensor chip according to claim 1 is characterized in that: the polysilicon film of described bottom has the corrosion hole of perforation, is full of in the described corrosion hole and the identical material of described upper strata oxide layer.
4. a kind of piezoresistance sensor chip according to claim 1 is characterized in that: described force sensing resistance is specially the force sensing resistance bar that the polycrystalline silicon membrane of coating described upper strata oxide layer forms through dry etching.
5. a kind of piezoresistance sensor chip according to claim 2, it is characterized in that: the pressure rete position of described vacuum chamber correspondence specifically is divided into film district, Liang Qu, described beam district lateral arrangement is in the center on described vacuum chamber top, and described film district is symmetrically arranged in vertical both sides of described Liang Qu.
6. a kind of piezoresistance sensor chip according to claim 5, it is characterized in that: described film district is lower than described Liang Qu, the underlying polysilicon film in described film district exposes, described Liang Qu comprise polysilicon film, the upper strata of bottom oxide layer, coat the silicon nitride layer on the oxide layer of described upper strata.
7. according to claim 4 or 6 described a kind of piezoresistance sensor chips, it is characterized in that: described force sensing resistance bar is symmetrically arranged in cross central line both sides, described beam district, the upper strata of described force sensing resistance bar is coated with described silicon nitride layer, and described metal lead wire is communicated with described force sensing resistance bar by fairlead.
8. the method for making of a piezoresistance sensor chip, it is characterized in that: in substrate silicon upper surface growth oxide layer, the oxide layer in photoetching and the big film of corrosion back of the body district, grow PSG (mixing the cryogenic oxidation silicon of phosphorus) as sacrifice layer at the big film regioselectivity of the back of the body, and anti-carve the oxide layer in the big film of non-back of the body district, at substrate silicon upper surface growing polycrystalline silicon film; Photoetching is also corroded the corrosion hole of polysilicon film, and releasing sacrificial layer is with the thick SiO of method deposit 2um of PECVD (plasma enhanced chemical vapor deposition)
2Stop up corrosion hole, and carry out densification; The deposit polysilicon membrane anti-carves resistance area in its front, and forms the polysilicon resistance bar behind the dry etching; Deposit Si
3N
4, photoetching Liang Qu, the oxide layer of losing the film district with the carving of beam district is to form beam-membrane structure; Lithography fair lead anti-carves the Al lead-in wire behind the steaming Al, finish metal lead wire after the alloying.
9. the method for making of a kind of piezoresistance sensor chip according to claim 8 is characterized in that:
Its concrete steps are as follows:
A, substrate silicon is carried out standard cleaning, the back deionized water rinsing, and, then,, make the SiO of its single face formation 0.1～1um with silicon slice placed thermal oxide in oxidation furnace of handling well with drier dehydration, oven dry
2Oxide layer;
Big film district is carried on the back in b, photoetching, the SiO in the big film of corrosion back of the body district
2Oxide layer continues use the TMAH(Tetramethylammonium hydroxide) corrosion carries on the back the silicon 1～5um in big film district.After cleaning, use deionized water rinsing, enter the PSG (mixing the cryogenic oxidation silicon of phosphorus) that grows in PECVD (plasma enhanced chemical vapor deposition) stove after the oven dry, as sacrifice layer, wherein the thickness of Sheng Chang PSG is identical with the thickness of the silicon in the big film of the back of the body that is corroded district;
C, anti-carve the back of the body big film district, corrode the oxide layer in the big film of non-back of the body district.After cleaning, use deionized water rinsing, enter the LPCVD(low-pressure chemical vapor deposition after the oven dry) polysilicon film of growth bottom in the stove, thickness 1～5um;
D, lithographic definition corrosion hole, the method for employing dry etching is removed the polysilicon in the corrosion hole, again with dry method or wet process releasing sacrificial layer PSG (mixing the cryogenic oxidation silicon of phosphorus).After cleaning, use deionized water rinsing, enter the SiO that grows in PECVD (plasma enhanced chemical vapor deposition) stove after the oven dry
2Film 1～5um puts into oxidation furnace and carries out stopping up corrosion hole after the fine and close oxidation processes;
E, the silicon chip that will finish above-mentioned operation are put into the LPCVD(low-pressure chemical vapor deposition) stove preparing polysilicon film 0.1～1um, by boron diffusion or the injection of boron ion polysilicon membrane is mixed, for activator impurity spreads or injects the defective that causes with eliminating, and impurity is evenly distributed, with silicon slice placed annealing in process under 950 ℃～1200 ℃ nitrogen protections;
The shape of f, lithographic definition polysilicon force sensing resistance bar, the method for employing dry etching stays the force sensing resistance bar of polysilicon in desired location.After cleaning, use deionized water rinsing.Entering the LPCVD(low-pressure chemical vapor deposition after the oven dry) Si grows in the stove
3N
4Film 0.1～1um;
G, photoetching Liang Qu remove silicon nitride layer, the oxide layer in film district successively, form beam-membrane structure;
H, lithography fair lead anti-carve the Al lead-in wire behind the steaming Al, finish metal lead wire after the alloying.
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