CN101826025A - Device for upgrading firmware of field programmable logic device and method thereof - Google Patents
Device for upgrading firmware of field programmable logic device and method thereof Download PDFInfo
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Abstract
The invention discloses a device for upgrading the firmware of a field programmable logic device, which comprises a microcontroller and a host connected with the microcontroller, and is characterized in that the microcontroller is connected with the field programmable logic device in a passive serial mode, after the host sends a firmware upgrading instruction, the microcontroller reads in the firmware upgrading data and configures the firmware upgrading data for the field programmable logic devices in passive serial mode. When upgrading the CPLD firmware, the device is simple to operate, and not only can eliminate the hardware problems caused by artificially welding or inserting/pulling the chip CPLD, but also can avoid the inconvenience caused by using the ISP.
Description
Technical field
The invention belongs to field of computer technology, be specifically related to the method for a kind of simple on-site field programmable logic device (CPLD) device for upgrading firmware and upgrading thereof.
Background technology
Current society is the society of a digitizing and digital integrated circuit widespread use.Digital integrated circuit is originally in constantly updating.It by early stage electron tube, transistor, little medium scale integration (MSI), develop into VLSI (very large scale integrated circuit) (VLSIC is more than several ten thousand) and many special ICs with specific function.But along with the development of microelectric technique, design is not exclusively independently born by semiconductor manufacturer with the task of making integrated circuit.System designers more are ready own design specialized integrated circuit (ASIC) chip, and the design cycle of wishing ASIC is short as far as possible, preferably under lab just can design proper A SIC chip, and drop among the practical application immediately, thereby field programmable logic device (FPLD), the wherein most widely used CPLD (CPLD) that surely belongs to appearred.
But because the function of product not only will satisfy user's demand, also will accelerate the research and development speed of product, seize market as early as possible, this just need realize more logic function by the CPLD firmware upgrade under the situation that hardware does not change very much.At present the prior art method of carrying out the CPLD firmware upgrade mainly contains following 2 kinds: 1.ISP online upgrading, its advantage are can be by the JTAG10 CPLD that upgrades, simple and convenient.But its shortcoming also clearly, because circuit board must have the JTAG mouth, not only increased cost, and field upgrade must be with download line and download tool.2. use fever writes.In chip, the programming program time, must be placed on chip in the socket of fever writes.Its advantage is that cost is low, and is simple to operate.Shortcoming is frequently plug or welding chip CPLD again, causes the damage of hardware easily, artificial increase unreliability.
In order to provide a kind of operation both simply, not only to eliminate the hardware problem that artificial welding or plug chip CPLD cause, and can avoid the inconvenience of using ISP to bring again, prior art does not well solve, and makes troubles to the staff.The present invention comes therefrom.
Summary of the invention
The object of the invention is to provide a kind of device for upgrading firmware of field programmable logic device, solved and carried out CPLD firmware upgrade operation complexity in the prior art, need artificial welding or plug chip CPLD, often produced hardware problem and ISP upgrading and have problems such as inconvenience.
In order to solve these problems of the prior art, technical scheme provided by the invention is:
A kind of device for upgrading firmware of field programmable logic device, comprise microcontroller and the main frame that is connected with microcontroller, it is characterized in that described microcontroller is connected with field programmable logic device by the passive serial mode, after described main frame sends the firmware upgrade instruction, described microcontroller reads in the firmware upgrade data, and the firmware upgrade data are disposed field programmable logic device by the passive serial mode.
Preferably, described device also comprises internal storage, and described internal storage is connected with microcontroller, stores the firmware upgrade data of field programmable logic device.
Preferably, described internal storage is selected EROM for use, and after main frame sent the firmware data transfer instruction, microprocessor deposited internal storage in after accepting after the instruction firmware upgrade data are read in.
Preferably, the DCONFIG of described field programmable logic device, DCLK, DATA, INT_DONE, nSTATUS, CONF_DONE are connected to the I/O interface of microprocessor, wherein DCONFIG, DCLK, DATA pin are arranged to output state, by microprocessor field programmable logic device are operated; NSTATUS, CONF_DONE, INT_DONE pin are arranged to import attitude, are detected by the configuration status of microprocessor to field programmable logic device.
Preferably, the I/O interface of described microprocessor comprises CF, CON, INT, DL, CLK, DAT pin, the DCONFIG of described field programmable logic device, nSTATUS, INT_DONE, CONF_DONE, DCLK, DATA pin mate one by one and are connected with CF, CON, INT, DL, CLK, DAT pin, described microprocessor is arranged to delivery outlet by internal register with CF, DCLK, DATA pin, and CON, INT, DL pin are arranged to the input port.
When concrete the use, after described device powered on, micro controller was joined new CPLD scale-of-two and is read in internal storage, by the passive serial configuration, code was sent to CPLD, and moved; Outage if the desired logic function of CPLD correctly realizes after restarting circuit board, is then finished debug process, if program error, the mistake in the search program then is after the recompility, repeat above-mentioned steps, till the correct realization of the desired logic function of CPLD.
Another object of the present invention is to provide a kind of method of simple on-site upgrading field programmable logic device firmware, it is characterized in that said method comprising the steps of:
(1) connects field programmable logic device by the passive serial mode on the programmable logic device (PLD) device for upgrading firmware at the scene;
(2) main frame generates the scale-of-two configuration data of field programmable logic device firmware;
(3) main frame sends instruction, and micro controller sends to field programmable logic device by the passive serial mode with the scale-of-two configuration data after the scale-of-two configuration data is read in internal storage.
Preferably, described method step (3) comprises microprocessor upward saltus step from low to high of generation of DCONFIG of programmable logic device (PLD) at the scene, make field programmable logic device enter configuration status, wait for that field programmable logic device discharges nSTATUS, after nSTATuS uprises, deliver to configuration data on the DATA by turn by the DCLK rising edge; After field programmable logic device is received all configuration datas, discharge CONF_DONE, become high level, the last output of DCLK pulse comes the initialization field programmable logic device, be released up to INT_DONE and become high level, the initialization of expression field programmable logic device finishes, and enters User Status, the step that layoutprocedure finishes.
Preferably, also comprise the step of debugging after configuration finishes in the described method, if the step of described debugging comprises that restarting behind the device for upgrading firmware of field programmable logic device the desired logic function of field programmable logic device fails correct the realization, then remodify firmware code, be compiled into passive serial configuration again behind the scale-of-two configuration data.
Preferably, also comprise the step of carrying out device for upgrading firmware of field programmable logic device dismounting on the field programmable logic device after the successfully configuration in the described method.
This method is followed the JTAG agreement; Microprocessor at first produces the negative pulse of a width greater than 8 μ s on the DCONFIG signal wire, begin to detect the state of nSTATUS signal then.CPLD can force nSTATUS and CONF_DONE signal to drag down after detecting the negative edge of DCONFIG signal, and remains low level between the DCONFIG signal is raised again.After the DCONFIG signal is raised, nSTATUS will raise within 1 μ s thereupon, and microprocessor detects just to be thought after this changes that CPLD is ready and can begin configuration.Dispose the time interval that requires to have at least 1 μ s between the rising edge of first rising edge and nSTATUS.Because configuration data is synchronous with the configuration rising edge, between the rising edge of configurable clock generator comes, the configuration data of 1bit should be ready on data line, configuration data by low level formerly high-order after order send from data line.After whole configuration datas are sent, the CONF_DONE signal will be elevated, and show that configuration finishes.Microprocessor detects the CONF_DONE signal and raises, and just finishes layoutprocedure.If make mistakes in the layoutprocedure, CPLD will force the nSTATUS signal to drag down, and microprocessor detects this variation will restart configuration.
Principle of the present invention is by the configuration of micro controller and passive serial the CPLD required binary code of upgrading to be sent to CPLD, and then realizes required logic function, and preferred concrete upgrade step can be:
A, on circuit board, set up passive serial configuration;
B, under the MAX+PLUSII environment, generate new CPLD scale-of-two configuration data;
C, circuit board power on, and micro controller is read in internal storage with configuration data, then, on DCONFIG, produce a saltus step from low to high, make CPLD enter configuration status, wait for that CPLD discharges nSTATUS, after nSTATUS uprises, deliver to configuration data on the DATA by turn by the DCLK rising edge; After CPLD is received all configuration datas, can discharge CONF_DONE, become high level, the pulse of the last output of DCLK afterwards comes initialization CPLD device, is released up to INT_DONE to become high level, and the initialization of expression CPLD device finishes, enter User Status, layoutprocedure finishes;
If D, restart circuit board after the desired logic function of CPLD correctly realize, then carry out step e; Otherwise remodify code, compiling, repeat step B, C again;
E, finish debugging.
In these steps, step e can be removed the passive serial configuration after finishing debugging.In the steps A, the passive serial configuration is that definition is provided with according to chip handbook pin oneself.Among the described step B, CPLD scale-of-two configuration data is a code of realizing logic function.
By above-mentioned escalation process, the present invention obtains a kind of operation and both simply, had not only eliminated artificial welding or plugged the hardware problem that chip CPLD causes, and can avoid using the adjustment method of the inconvenience that ISP brings again, designed the method for a kind of simple on-site CPLD firmware upgrade, the configuration of use passive serial, the required binary code of upgrading is sent to CPLD, simple to operate, not only solved owing to frequently plug or weld again CPLD, cause the technical matters of hardware damage easily, and avoided the inconvenience of using ISP to bring.
With respect to scheme of the prior art, advantage of the present invention is:
By the configuration of micro controller and passive serial the CPLD required binary code of upgrading is sent to CPLD in the technical solution of the present invention, and then realize required logic function; Not only solved owing to frequently plugging or welding CPLD again, caused the technical matters of hardware damage easily, and avoided the inconvenience of using ISP to bring.
In sum, the invention provides the method for a kind of simple on-site CPLD firmware upgrade, this method operation both simply, had not only been eliminated artificial welding or had been plugged the hardware problem that chip CPLD causes, and can avoid the inconvenience of using ISP to bring again, the technical scheme that adopts is by micro controller and passive serial configuration the CPLD required binary code of upgrading to be sent to CPLD, and then realizes required logic function.This method concrete steps are: set up passive serial configuration on circuit board, after circuit board powered on, micro controller was joined new CPLD scale-of-two and is read in internal storage, by the passive serial configuration, code was sent to CPLD, and moved; Outage if the desired logic function of CPLD correctly realizes after restarting circuit board, is then finished debug process, if program error, the mistake in the search program then is after the recompility, repeat above-mentioned steps, till the correct realization of the desired logic function of CPLD.
Description of drawings
Below in conjunction with drawings and Examples the present invention is further described:
Fig. 1 is the structural representation of embodiment of the invention device.
Embodiment
Below in conjunction with specific embodiment such scheme is described further.Should be understood that these embodiment are used to the present invention is described and are not limited to limit the scope of the invention.The implementation condition that adopts among the embodiment can be done further adjustment according to the condition of concrete producer, and not marked implementation condition is generally the condition in the normal experiment.
Embodiment as shown in Figure 1, this device for upgrading firmware of field programmable logic device, comprise the microcontroller of BCM5836 chip, the internal storage and the PC that is connected with microcontroller of A3S56D30ETP chip, it is characterized in that described microcontroller is connected with field programmable logic device by the passive serial mode, after described main frame sends the firmware upgrade instruction, described microcontroller reads in the firmware upgrade data, and the firmware upgrade data are disposed field programmable logic device by the passive serial mode.Described internal storage is connected with microcontroller, stores the firmware upgrade data of field programmable logic device.Described internal storage is selected EROM for use, and after main frame sent the firmware data transfer instruction, microprocessor deposited internal storage in after accepting after the instruction firmware upgrade data are read in.Described field programmable logic device is the LCM640C of Lattice company.
The DCONFIG of field programmable logic device, DCLK, DATA, INT_DONE, nSTATUS, CONF_DONE are connected to the I/O interface of microprocessor, wherein DCONFIG, DCLK, DATA pin are arranged to output state, by microprocessor field programmable logic device are operated; NSTATUS, CONF_DONE, INT_DONE pin are arranged to import attitude, are detected by the configuration status of microprocessor to field programmable logic device.The I/O interface of described microprocessor comprises CF, CON, INT, DL, CLK, DAT pin, the DCONFIG of described field programmable logic device, nSTATUS, INT_DONE, CONF_DONE, DCLK, DATA pin mate one by one and are connected with CF, CON, INT, DL, CLK, DAT pin, described microprocessor is arranged to delivery outlet by internal register with CF, DCLK, DATA pin, and CON, INT, DL pin are arranged to the input port.
When CPLD is carried out firmware upgrade, can carry out according to following steps:
A, on circuit board, set up passive serial configuration;
B, under the MAX+PLUSII environment, generate new CPLD scale-of-two configuration data;
C, circuit board power on, and micro controller is read in internal storage with configuration data.Then, on DCONFIG, produce a saltus step from low to high, make CPLD enter configuration status, wait for that CPLD discharges nSTATUS, after nSTATuS uprises, delivers to configuration data on the DATA by the DCLK rising edge by turn; After CPLD is received all configuration datas, can discharge CONF_DONE, become high level, the pulse of the last output of DCLK afterwards comes initialization CPLD device, is released up to INT_DONE to become high level, and the initialization of expression CPLD device finishes, enter User Status, layoutprocedure finishes;
If D, restart circuit board after the desired logic function of CPLD correctly realize, then carry out step e; Otherwise remodify code, compiling, repeat step B, C again;
E, finish debugging.
After finishing debugging, the passive serial configuration can be removed.
Before the configuration of upgrading, the microprocessor responds serial ports interrupts and receives data, and microprocessor is at first judged the command type that these data are represented, if configuration order, microprocessor just enters configuration status.Under configuration status, on one side microprocessor receives configuration data, Yi Bian these data are write in the CPLD device; If write the interior magazine order, microprocessor just enters the interior magazine state of writing, this moment, microprocessor can receive configuration data on one side, on one side these data are write configuration with (noticing that this moment, these data were not configured in the CPLD device) in the interior magazine; If read the interior magazine order, microprocessor just enters to be read interior magazine and disposes the CPLD device state, on one side this moment, microprocessor can be read configuration data in the interior magazine, Yi Bian the configuration data of reading is write in the CPLD device.
Above-mentioned example only is explanation technical conceive of the present invention and characteristics, and its purpose is to allow the people who is familiar with this technology can understand content of the present invention and enforcement according to this, can not limit protection scope of the present invention with this.All equivalent transformations that spirit is done according to the present invention or modification all should be encompassed within protection scope of the present invention.
Claims (9)
1. device for upgrading firmware of field programmable logic device, comprise microcontroller and the main frame that is connected with microcontroller, it is characterized in that described microcontroller is connected with field programmable logic device by the passive serial mode, after described main frame sends the firmware upgrade instruction, described microcontroller reads in the firmware upgrade data, and the firmware upgrade data are disposed field programmable logic device by the passive serial mode.
2. device for upgrading firmware of field programmable logic device according to claim 1 is characterized in that described device also comprises internal storage, and described internal storage is connected with microcontroller, stores the firmware upgrade data of field programmable logic device.
3. device for upgrading firmware of field programmable logic device according to claim 2, it is characterized in that described internal storage selects EROM for use, after main frame sent the firmware data transfer instruction, microprocessor deposited internal storage in after accepting after the instruction firmware upgrade data are read in.
4. device for upgrading firmware of field programmable logic device according to claim 1, it is characterized in that DCONFIG, DCLK, DATA, INT_DONE, nSTATUS, the CONF_DONE of described field programmable logic device are connected to the I/O interface of microprocessor, wherein DCONFIG, DCLK, DATA pin are arranged to output state, by microprocessor field programmable logic device are operated; NSTATUS, CONF_DONE, INT_DONE pin are arranged to import attitude, are detected by the configuration status of microprocessor to field programmable logic device.
5. device for upgrading firmware of field programmable logic device according to claim 4, the I/O interface that it is characterized in that described microprocessor comprises CF, CON, INT, DL, CLK, DAT pin, the DCONFIG of described field programmable logic device, nSTATUS, INT_DONE, CONF_DONE, DCLK, DATA pin mate one by one and are connected with CF, CON, INT, DL, CLK, DAT pin, described microprocessor is arranged to delivery outlet by internal register with CF, DCLK, DATA pin, and CON, INT, DL pin are arranged to the input port.
6. the method for simple on-site upgrading field programmable logic device firmware is characterized in that said method comprising the steps of:
(1) connects field programmable logic device by the passive serial mode on the programmable logic device (PLD) device for upgrading firmware at the scene;
(2) main frame generates the scale-of-two configuration data of field programmable logic device firmware;
(3) main frame sends instruction, and micro controller sends to field programmable logic device by the passive serial mode with the scale-of-two configuration data after the scale-of-two configuration data is read in internal storage.
7. method according to claim 6, it is characterized in that described method step (3) comprises microprocessor upward saltus step from low to high of generation of DCONFIG of programmable logic device (PLD) at the scene, make field programmable logic device enter configuration status, wait for that field programmable logic device discharges nSTATUS, after nSTATuS uprises, deliver to configuration data on the DATA by turn by the DCLK rising edge; After field programmable logic device is received all configuration datas, discharge CONF_DONE, become high level, the last output of DCLK pulse comes the initialization field programmable logic device, be released up to INT_DONE and become high level, the initialization of expression field programmable logic device finishes, and enters User Status, the step that layoutprocedure finishes.
8. method according to claim 6, it is characterized in that also comprising in the described method step of debugging after configuration finishes, if the step of described debugging comprises that restarting behind the device for upgrading firmware of field programmable logic device the desired logic function of field programmable logic device fails correct the realization, then remodify firmware code, be compiled into passive serial configuration again behind the scale-of-two configuration data.
9. method according to claim 6 is characterized in that also comprising in the described method step of carrying out device for upgrading firmware of field programmable logic device dismounting on the field programmable logic device after the successfully configuration.
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| CN104331300A (en) * | 2014-09-23 | 2015-02-04 | 英业达科技有限公司 | Server capable of directly updating setting by using substrate management controller |
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| CN106445544A (en) * | 2016-10-08 | 2017-02-22 | 中国科学院微电子研究所 | Device and method for configuring or updating programmable logic device |
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| US9996334B2 (en) | 2016-09-21 | 2018-06-12 | International Business Machines Corporation | Deploying and utilizing a software library and corresponding field programmable device binary |
| US10355945B2 (en) | 2016-09-21 | 2019-07-16 | International Business Machines Corporation | Service level management of a workload defined environment |
| US10417012B2 (en) | 2016-09-21 | 2019-09-17 | International Business Machines Corporation | Reprogramming a field programmable device on-demand |
| US10572310B2 (en) | 2016-09-21 | 2020-02-25 | International Business Machines Corporation | Deploying and utilizing a software library and corresponding field programmable device binary |
| US10599479B2 (en) | 2016-09-21 | 2020-03-24 | International Business Machines Corporation | Resource sharing management of a field programmable device |
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| US9152544B2 (en) | 2011-07-21 | 2015-10-06 | Huawei Technologies Co., Ltd. | Method and system for upgrading a firmware of a chip and baseboard management controller by waiting until an idle state of a connected system to finish upgrade |
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Application publication date: 20100908 |