CN102520961B - Off-chip online programmable SOC (system on a chip) and control method for same - Google Patents
Off-chip online programmable SOC (system on a chip) and control method for same Download PDFInfo
- Publication number
- CN102520961B CN102520961B CN201110433068.5A CN201110433068A CN102520961B CN 102520961 B CN102520961 B CN 102520961B CN 201110433068 A CN201110433068 A CN 201110433068A CN 102520961 B CN102520961 B CN 102520961B
- Authority
- CN
- China
- Prior art keywords
- interface
- nflash
- soc
- chip
- norflash
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Programmable Controllers (AREA)
Abstract
The invention relates to the technical field of design of an SOC (system on a chip), in particular to an off-chip online programmable SOC (system on a chip) and a control method for the same. The system comprises an SOC, an off-chip Nflash/Norflash storage and an off-chip switch, the SOC comprises a minimum SOC, a serial port controller, an Nflash/Norflash controller and a reset control CCU (central control unit) module, and the minimum SOC comprises a CPU (central processing unit), an internal storage and an on-chip bus. The control method for the system includes: compiling software on a computer, switching the SOC into a programming mode by means of selection control of the off-chip switch, downloading compiled executable file data into the off-chip Nflash/Norflash storage, and then switching the SOC into a normal operating mode to realize system operation. The system and the control method for the system are not only beneficial to development of a software system, but also easy to debug, and the chip is not easy to damage during debugging.
Description
Technical field
The present invention relates to SOC design field, particularly the outer online programmable SOC system of a kind of sheet and control method thereof.
Background technology
SOC chip has been widely used in every field at present, and the carrier of the software storage of SOC chip has two kinds of modes, a kind of is Flash in SOC chip, be the Nflash/Norflash outside sheet, these two kinds of modes are different for the downloading mode of software data.
The software data downloaded stored mode of Flash in sheet as shown in Figure 1, after PC end generates software executable, downloads data to the serial ports of SOC chip by serial ports, then, by the flash controller of chip internal, write data in Flash.The advantage of this mode is that software can be directly downloaded to the routine data of generation in Flash, system debug is very convenient, shortcoming is because flash is in SOC chip, be subject to the restriction of chip technology and cost, Flash memory span can be very not large, for complicated software systems, just limit its application like this.
The software data downloaded stored mode of Nflash/Norflash outside sheet as shown in Figure 2, PC holds after Software Create, by professional Nflash/Norflash flashburn tools, software program data programming, in Nflash/Norflash, and then is welded on pcb board.The advantage of this mode is that the Nflash/Norflash outside sheet is enough large, can support for complicated software systems, shortcoming is for very trouble of software systems debugging, each update routine, need first Nflash/Norflash chip soldering to be got off, by professional fever writes by software programming in Nflash/Norflash, and then be welded on pcb board, bring the risk of damage because of welding virtually having increased chip like this.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, the outer online programmable SOC system of a kind of sheet and control method thereof are provided, this system and control method thereof are not only conducive to the exploitation of software systems, and are easy to debugging, and debug process chip is not fragile.
For achieving the above object, technical scheme of the present invention is: the outer online programmable SOC system of a kind of sheet, comprise SOC chip, the outer Nflash of sheet or Norflash storer and sheet external switch, described SOC chip is made up of SOC minimum system, serial ports controller, Nflash or the Norflash controller corresponding with described outer Nflash or Norflash storer and the control CCU module that resets, and described SOC minimum system comprises CPU, internal storage and bus on chip;
Described serial ports controller, being used for is bus on chip agreement by UART protocol conversion, described serial ports controller is provided with two UART interfaces and two bus interface, UART0 interface in two UART interfaces for being connected with serial ports of computers under programming mode, UART1 interface is the functional interface of SOC system under normal mode of operation, MBUS interface in two bus interface is that described serial ports controller is operated in the bus interface under Master pattern, for initiatively transfer data to Nflash or Norflash controller outside described under programming mode, another SBUS interface is that described serial ports controller is operated in the bus interface under Slave pattern, for the control interface of bus on chip to serial ports under normal mode of operation,
Described Nflash or Norflash controller, for by bus on chip protocol conversion being the control sequential of the outer Nflash of sheet or Norflash storer, described Nflash or Norflash controller only have a Slave bus interface, are to connect MBUS interface or SBUS interface by Slave bus interface described in model selection control;
Described reset control CCU module, for the reset signal of SOC system is controlled, complete under programming mode and normal mode of operation under management and the switching of all reset signals of SOC system;
Described external switch, controls for the mode of operation of SOC system is selected.
The present invention also provides the control method of the outer online programmable SOC system of sheet, comprises the following steps:
(1) sheet external switch being set makes SOC system be switched to programming mode;
(2) control the reset control of CCU module by reset, SBUS interface, UART1 interface, SOC minimum system and Nflash or Norflash controller are set to reset mode, then MBUS interface, UART0 interface and Nflash or Norflash controller are set to reset disarm state;
(3) by computing machine, start-up code and function code are compiled as to executable file data, by UART0 interface, described executable file data are write to the serial ports controller of SOC chip;
(4) serial ports controller, by MBUS interface through MUX, is passed to Nflash or Norflash controller by described executable file data;
(5) Nflash or Norflash controller transfer the described executable file data that receive to external memory control sequential, are written in the outer Nflash of sheet or Norflash storer;
(6) sheet external switch being set makes SOC system be switched to normal mode of operation;
(7) control the reset control of CCU module by reset, MBUS interface, UART0 interface and Nflash or Norflash controller are set to reset mode, then SBUS interface, UART1 interface, SOC minimum system and Nflash or Norflash controller are set to reset disarm state;
(8) CPU starts working, sense order in Nflash or Norflash storer from sheet, and configuration peripheral hardware, moves corresponding function program.
The invention has the beneficial effects as follows:
(1) Software Function Design of SOC system is no longer subject to internal storage to hold quantitative limitation, makes PHP more pay attention to efficiency and the performance of software, improves the Time To Market of product.
(2) avoid completely in the software debugging stage, use special storer flashburn tools carry out repeatedly programming and weld the chip risk of damage bringing Nflash/Norflash device, and software debugging is very flexible, has greatly reduced debug time.
Below in conjunction with drawings and the specific embodiments, the present invention is described in further detail.
Brief description of the drawings
Fig. 1 is the software data downloaded stored mode schematic diagram of the Flash in sheet in prior art.
Fig. 2 is the software data downloaded stored mode schematic diagram of the Nflash/Norflash outside sheet in prior art.
Fig. 3 is the system architecture schematic diagram of the embodiment of the present invention.
Fig. 4 is the present invention is switched to normal mode of operation reset control sequential chart from programming mode.
Fig. 5 is the present invention is switched to programming mode reset control sequential chart from normal mode of operation.
Embodiment
Of the present invention outer online programmable SOC system, as shown in Figure 3, comprise SOC chip, the outer Nflash of sheet or Norflash storer and sheet external switch, described SOC chip is made up of SOC minimum system, serial ports controller, Nflash or the Norflash controller corresponding with described outer Nflash or Norflash storer and the control CCU module that resets, and described SOC minimum system comprises CPU, internal storage and bus on chip; It should be noted that, the outer Nflash of sheet or Norflash storer refer to that chip external memory can adopt Nflash or Norflash wherein a kind of, if sheet adopts Nflash storer outward, corresponding employing is NFlash controller, if sheet adopts Norflash storer outward, corresponding employing is Norflash controller.
Described serial ports controller, being used for is bus on chip agreement by UART protocol conversion, described serial ports controller is provided with two UART interfaces and two bus interface, UART0 interface in two UART interfaces for being connected with serial ports of computers under programming mode, UART1 interface is the functional interface of SOC system under normal mode of operation, MBUS interface in two bus interface is that described serial ports controller is operated in the bus interface under Master pattern, for initiatively transfer data to Nflash or Norflash controller outside described under programming mode, another SBUS interface is that described serial ports controller is operated in the bus interface under Slave pattern, for the control interface of bus on chip to serial ports under normal mode of operation,
Described Nflash or Norflash controller, for by bus on chip protocol conversion being the control sequential of the outer Nflash of sheet or Norflash storer, described Nflash or Norflash controller only have a Slave bus interface, are to connect MBUS interface or SBUS interface by Slave bus interface described in model selection control;
Described reset control CCU module, for the reset signal of SOC system is controlled, complete under programming mode and normal mode of operation under management and the switching of all reset signals of SOC system;
Described external switch, controls for the mode of operation of SOC system is selected; In the time that sheet external switch signal is high level, expression system is in online programming state, and when sheet external switch signal is when being low level, expression system is in normal operating conditions.
Above-mentioned SOC minimum system also comprises peripheral hardware, and CPU, internal storage, bus on chip are the requisite assemblies of SOC system, and peripheral hardware is selected different functional modules according to the different demand of SOC system.
The control method of of the present invention outer online programmable SOC system, comprises the following steps:
(1) sheet external switch is set to high level, makes SOC system under programming mode;
(2) under programming mode, control the reset control of CCU module by reset, SBUS interface, UART1 interface, SOC minimum system and Nflash or Norflash controller are set to reset mode, then MBUS interface, UART0 interface and Nflash or Norflash controller are set to reset disarm state;
(3) by computing machine, start-up code and function code are compiled as to executable file data, by UART0 interface, described executable file data are write to the serial ports controller of SOC chip;
(4) serial ports controller, by MBUS interface through MUX, is passed to Nflash or Norflash controller by described executable file data;
(5) Nflash or Norflash controller transfer the described executable file data that receive to external memory control sequential, are written in the outer Nflash of sheet or Norflash storer;
(6) the described executable file data that write are read by Nflash or Norflash controller, then pass to again computing machine by UART0 interface, data in computing machine and before writing contrast, guarantee that the data of writing into do not have mistake, if made a mistake, re-write executable file data;
(7), confirming that executable file data are successfully written to outside sheet after Nflash or Norflash storer, sheet external switch is set to low level, makes SOC system be switched to normal mode of operation from programming mode;
(8) be switched under normal mode of operation and after moving a period of time in SOC system, control the reset control of CCU module by reset, MBUS interface, UART0 interface and Nflash or Norflash controller are set to reset mode, then SBUS interface, UART1 interface, SOC minimum system and Nflash or Norflash controller are set to reset disarm state;
(9) CPU starts working, sense order in Nflash or Norflash storer from sheet, and configuration peripheral hardware, moves corresponding function.
(10) if function does not meet the demands or needs amendment, revise on computers software and recompilate, by the selection control of sheet external switch, SOC system is switched to programming mode, the executable file data of newly compiling are downloaded in the outer Nflash of sheet or Norflash storer, and then be switched to normal mode of operation, carry out system debug and checking.
As shown in Figure 3, in the use procedure of product, a sheet external switch or wire jumper need to be set on pcb board as pattern switching controls.After SOC chip is connected with the serial ports of computing machine, Software for Design completes, after compiling, mode selector switch is set to height, be online programmable pattern, by serial ports, software data downloaded in external memory storage, after guaranteeing that downloading data is correct, pattern is switched to normal mode of operation, and SOC system starts anew to carry out function program.
In the present invention, the reset control of CCU module, has switched vital effect to whole system at programming mode and normal mode of operation.
Fig. 4 is the sequential chart that is switched to normal mode of operation from programming mode, reset and control the reset control of CCU module, first the reset signal of online programmable logical gate first drags down in reset mode, and then the reset signal of normal work-based logic is drawn high, in reset disarm state.Wherein, the reset signal of online programmable logical gate refers to the reset signal of MBUS interface, UART0 interface and Nflash or Norflash controller, and the reset signal of normal work-based logic part refers to the reset signal of SBUS interface, UART1 interface, SOC minimum system and Nflash or Norflash controller.
Fig. 5 is the sequential chart that is switched to programming mode from normal mode of operation, the reset control of reset CCU module, the reset signal of first normal work-based logic part first drags down in reset mode, and then the reset signal of online programmable logic is drawn high, in reset disarm state.
Normal mode of operation and programming mode all will be used Nflash/Norflash controller, this part logic need to reset when pattern is switched, as shown in Figure 4 and Figure 5, the normal reset control of work-based logic and the reset control of online programmable logic be all low during, be the reset time of Nflash/Norflash controller.
Be more than preferred embodiment of the present invention, all changes of doing according to technical solution of the present invention, when the function producing does not exceed the scope of technical solution of the present invention, all belong to protection scope of the present invention.
Claims (5)
1. the outer online programmable SOC system of sheet, it is characterized in that: comprise SOC chip, the outer NFlash of sheet or Norflash storer and sheet external switch, described SOC chip is made up of SOC minimum system, serial ports controller, NFlash or the Norflash controller corresponding with described outer NFlash or Norflash storer and the control CCU module that resets, and described SOC minimum system comprises CPU, internal storage and bus on chip;
Described serial ports controller, being used for is bus on chip agreement by UART protocol conversion, described serial ports controller is provided with two UART interfaces and two bus interface, UART0 interface in two UART interfaces for being connected with serial ports of computers under programming mode, UART1 interface is the functional interface of SOC system under normal mode of operation, MBUS interface in two bus interface is that described serial ports controller is operated in the bus interface under Master pattern, for initiatively transfer data to described NFlash or Norflash controller under programming mode, another SBUS interface is that described serial ports controller is operated in the bus interface under Slave pattern, for the control interface of bus on chip to serial ports under normal mode of operation,
Described NFlash or Norflash controller, for by bus on chip protocol conversion being the control sequential of the outer NFlash of sheet or Norflash storer, described NFlash or Norflash controller only have a Slave bus interface, are to connect MBUS interface or SBUS interface by Slave bus interface described in model selection control;
Described reset control CCU module, for the reset signal of SOC system is controlled, complete under programming mode and normal mode of operation under management and the switching of all reset signals of SOC system;
Described external switch, controls for the mode of operation of SOC system is selected.
2. according to claim 1 outer online programmable SOC system, is characterized in that: described SOC minimum system also comprises peripheral hardware.
3. the control method of according to claim 1 and 2 outer online programmable SOC system, is characterized in that: comprise the following steps:
(1) sheet external switch being set makes SOC system under programming mode; Under programming mode, control the reset control of CCU module by reset, the SBUS interface except MBUS interface, UART0 interface and NFlash or Norflash controller and UART1 interface are set to reset mode;
(2) by computing machine, start-up code and function code are compiled as to executable file data, by UART0 interface, described executable file data are write to the serial ports controller of SOC chip;
(3) serial ports controller, by MBUS interface through MUX, is passed to NFlash or Norflash controller by described executable file data;
(4) NFlash or Norflash controller transfer the described executable file data that receive to external memory control sequential, are written in the outer NFlash of sheet or Norflash storer;
(5) sheet external switch being set makes SOC chip be switched to normal mode of operation;
(6) after a period of time, reset and control CCU module by the reset signal releasing of SBUS interface and UART1 interface, MBUS interface and UART0 interface are set to reset mode simultaneously;
(7) CPU starts working, sense order in NFlash or Norflash storer from sheet, and configuration peripheral hardware, moves corresponding function program.
4. the control method of according to claim 3 outer online programmable SOC system, it is characterized in that: also further comprising the steps between step (4) and step (5): the described executable file data that write are read by NFlash or Norflash controller, then pass to again computing machine by UART0 interface, data in computing machine and before writing contrast, guarantee that the data of writing into do not have mistake, if made a mistake, re-write executable file data; Confirming that executable file data are successfully written to outside sheet after NFlash or Norflash storer, then sheet external switch is set makes SOC chip be switched to normal mode of operation.
5. the control method of according to claim 3 outer online programmable SOC system, it is characterized in that: also further comprising the steps afterwards in step (7): if function does not meet the demands or needs amendment, revise on computers software and recompilate, by the selection control of sheet external switch, SOC chip is switched to programming mode, the executable file data of newly compiling are downloaded in the outer NFlash of sheet or Norflash storer, and then be switched to normal mode of operation, carry out system debug and checking.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110433068.5A CN102520961B (en) | 2011-12-22 | 2011-12-22 | Off-chip online programmable SOC (system on a chip) and control method for same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110433068.5A CN102520961B (en) | 2011-12-22 | 2011-12-22 | Off-chip online programmable SOC (system on a chip) and control method for same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102520961A CN102520961A (en) | 2012-06-27 |
| CN102520961B true CN102520961B (en) | 2014-08-27 |
Family
ID=46291903
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110433068.5A Expired - Fee Related CN102520961B (en) | 2011-12-22 | 2011-12-22 | Off-chip online programmable SOC (system on a chip) and control method for same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102520961B (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103246623B (en) * | 2013-05-20 | 2016-08-31 | 杭州士兰控股有限公司 | SOC calculates device extension system |
| CN103412834B (en) * | 2013-07-23 | 2015-11-25 | 中国科学院计算技术研究所 | The multiplexing method of a kind of single SOC and single SOC multi-operation mode |
| CN105487906A (en) * | 2015-12-07 | 2016-04-13 | 浪潮集团有限公司 | Method and system for realizing MCU core code updating by using plug-in FLASH |
| CN106873916A (en) * | 2017-02-23 | 2017-06-20 | 郑州云海信息技术有限公司 | A kind of Debugging message access method and device based on the debugging of ultra-large chip |
| CN106682535A (en) * | 2017-03-16 | 2017-05-17 | 周清睿 | System on chip (SoC) |
| WO2020029254A1 (en) * | 2018-08-10 | 2020-02-13 | 深圳市汇顶科技股份有限公司 | Soc chip and bus access control method |
| CN111459744A (en) * | 2020-03-20 | 2020-07-28 | 江苏集萃智能集成电路设计技术研究所有限公司 | Firmware burning method and firmware debugging method of video processing chip |
| CN112291256B (en) * | 2020-11-06 | 2023-12-01 | 北京中航通用科技有限公司 | UART gateway data transmission method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1991784A (en) * | 2005-12-30 | 2007-07-04 | 北京中电华大电子设计有限责任公司 | On-line debugging method for SoC system using HDL to expand serial port |
| CN102282546A (en) * | 2008-11-10 | 2011-12-14 | 维尔基逻辑公司 | Resource controlling |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8650629B2 (en) * | 2009-12-16 | 2014-02-11 | Intel Corporation | Interface logic for a multi-core system-on-a-chip (SoC) |
-
2011
- 2011-12-22 CN CN201110433068.5A patent/CN102520961B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1991784A (en) * | 2005-12-30 | 2007-07-04 | 北京中电华大电子设计有限责任公司 | On-line debugging method for SoC system using HDL to expand serial port |
| CN102282546A (en) * | 2008-11-10 | 2011-12-14 | 维尔基逻辑公司 | Resource controlling |
Non-Patent Citations (3)
| Title |
|---|
| 刘磊等.基于SPM的多核SoC访存结构设计与优化.《计算机工程》.2009,第35卷(第18期),第234-236页. |
| 基于SPM的多核SoC访存结构设计与优化;刘磊等;《计算机工程》;20090920;第35卷(第18期);第234-236页 * |
| 王仁平等.基于MCU的SoC芯片版图设计与验证.《福州大学学报(自然科学版)》.2011,第39卷(第4期),第539-545页. * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102520961A (en) | 2012-06-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102520961B (en) | Off-chip online programmable SOC (system on a chip) and control method for same | |
| CN102609286B (en) | A kind of FPGA configurator remote update system based on processor control and method thereof | |
| CN105930186B (en) | The method for loading software of multi -CPU and software loading apparatus based on multi -CPU | |
| CN104679559B (en) | The method of single-chip microcontroller online programming | |
| CN107678988A (en) | A kind of multifunctional serial port device and implementation method | |
| CN105320531A (en) | Online FPGA software upgrading method based on MicroBlaze soft core | |
| CN105335548A (en) | MCU simulation method for ICE | |
| CN104077204A (en) | Reconfigurable 8-bit RSIC (reduced instruction set computer) SCM (Single Chip Microcomputer) simulator | |
| CN102854962B (en) | MPC8280 minimum system applying CPLD (complex programmable logic device) and state switching method for setting hard reset configuration words | |
| CN104834620A (en) | SPI (serial peripheral interface) bus circuit, realization method and electronic equipment | |
| CN109992555A (en) | A kind of management board shared for multipath server | |
| CN106773954A (en) | A kind of operating mode control method in microcontroller chip | |
| CN102377423A (en) | Field programmable gate array (FPGA) online configuration method | |
| CN111190855A (en) | FPGA multiple remote configuration system and method | |
| CN100545826C (en) | A kind of microcontroller | |
| CN102375749B (en) | Method for quickly downloading and updating firmware by using I2C (Inter-Integrated Circuit) bus | |
| CN103793263A (en) | DMA transaction-level modeling method based on Power PC processor | |
| CN203250312U (en) | Extensible common core processing daughter board with interferences | |
| CN102193860A (en) | Microcontroller online debugging circuit and method as well as microcontroller | |
| CN104077080A (en) | Memory access method, memory access control method, SPI flash memory device and controller thereof | |
| CN204706031U (en) | Serial peripheral equipment interface SPI bus circuit and electronic equipment | |
| CN102955872B (en) | There is the emulator of parameter propagation function | |
| CN111710357B (en) | MTP unit read-write control circuit of MCU | |
| CN202394528U (en) | Programming device for storage board | |
| CN104750591A (en) | Evidence-taking device and method for computer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140827 Termination date: 20161222 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |