CN101819450A - Method for synchronizing multipath DDS (Direct Digital Synthesis) signals - Google Patents
Method for synchronizing multipath DDS (Direct Digital Synthesis) signals Download PDFInfo
- Publication number
- CN101819450A CN101819450A CN 201010156393 CN201010156393A CN101819450A CN 101819450 A CN101819450 A CN 101819450A CN 201010156393 CN201010156393 CN 201010156393 CN 201010156393 A CN201010156393 A CN 201010156393A CN 101819450 A CN101819450 A CN 101819450A
- Authority
- CN
- China
- Prior art keywords
- dds
- phase
- latch
- cpu
- phase control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Measuring Phase Differences (AREA)
Abstract
The invention relates to a synchronization method capable of strictly synchronizing multipath DDS signals and not generating phase errors during phase switching. The method comprises the following steps of: synchronizing multipath DDS by using clock signals generated by the same oscillator; transmitting synchronizing signals generated by one contact button to each-path DDS to make the program of the DDS run from the same instruction position; and generating a binary phase control signal through a switch, and then deciding the meter lookup position of next circulation according to the phase control signal and the meter lookup position of the current program by using a CPU of the DDS to realize phase switching. Latches are connected to the backs of the contact buttons for synchronization. Each-path DDS is provided with a set of phase control switches. The latches are connected with the backs of all phase control switches, the outputs of the latches are connected to the phase control ends of respective CPUs in one-to-one correspondence, and the control ends of the latches are connected with the CPU. By utilizing the method, an accurate and stable same-phase or right-angle voltage ratio can be established by using low cost for precise impedance measurement.
Description
Technical field:
The present invention relates to the signal generator field, particularly a kind of method for synchronous that can make multipath DDS (Direct Digital Synthesis) signals keep the stable phase potential difference.
Background technology:
DDS is the english abbreviation of " Direct Digital frequency synthesis ".This is a kind of from the phase place notion, directly synthesizes the technology of required waveform with given reference frequency.Because the DDS technology has clear superiority at aspects such as bandwidth, frequency inverted time, resolution, is developed faster in recent years.
In the Precise Electromagnetic Measurement field, the usability ratio arms that should be coupled obtains the right angle ratio in conjunction with the RC phase shift network always traditionally, and then precision measurement is carried out in the right angle impedance.Though this method can obtain high-precision right angle ratio, complex structure, with high costs.The present invention proposes a kind of DDS signal synchronizing method that guarantees accurate stable phase potential difference, thereby realizes making up the right angle ratio to carry out the impedance precision measurement with DDS.Use this technology to carry out the accuracy of measurement that measurement of mutual inductance reached and be better than disclosed in the world at present best index.
The output waveform of DDS is determined that by the waveform table that is stored among the ROM this is the basis that its phase place has high accuracy and stability.But will constitute the right angle ratio that can be used for precision measurement with two-way or multipath DDS (Direct Digital Synthesis) signals, also must satisfy following several requirements: one, each road DDS signal keeps fully synchronously when operation; Two, in measuring process, each road DDS resetted after, the phase differential of each road signal with reset before answer strict conformance; Three, when the using compensation method is measured impedance, usually need to change the wherein phase place of one road signal, the operation that therefore requires DDS can accurately excute phase to change, and can accurately recover virgin state.
Using switch to carry out " resetting " or " phase place switching " according to usual method can not errorless realization above-mentioned second and the 3rd requirement of entirely accurate.This be because: the trigger pip that is produced by button or switch has a damped oscillation process, can cause repeatedly false triggering when the coda wave voltage of vibration surpasses the synchronous triggering level.And owing to distribution parameter difference among each road DDS, the signal waveform of end also can not be in full accord synchronously to arrive each road DDS.So promptly use each road signal of same switch triggering, the constantly different situation of actual triggering also can take place, cause phase place inaccurate.This phase error is unimportant concerning general application, but precision measurement then is the problem that needs emphasis to solve.
Adopt existing disappear for example RC filtering of the measure of trembling, monostable circuit or software to disappear to tremble and to improve the problems referred to above.But the effect of RC filtering can not satisfy the requirement of pin-point accuracy; Software disappears to tremble and can take the program space and cause DDS output frequency bandwidth to narrow down; Monostable circuit can address the above problem, but structure dislikes complicated slightly.
In fact disappear and tremble a kind of thinking that just addresses the above problem.If keep in full accord in the time of allowing trigger pip arrive each road to hold synchronously,, still can guarantee not produce phase error even there is a small amount of shake.The present invention from then on thinking sets out, and it is low, simple in structure but can the strict method for synchronous of realizing required three conditions of right angle ratio to propose a kind of cost.
Summary of the invention:
The invention provides a kind of method for synchronous of multipath DDS (Direct Digital Synthesis) signals, be used to make the multipath DDS (Direct Digital Synthesis) signals strict synchronism and reset and do not produce phase error when switching phase place.The important application occasion of this method is to make up accurately stable homophase or right angle voltage ratio to carry out accurate impedance measurement.
To achieve these goals, the present invention proposes following method: the clock signal that each road DDS uses same oscillator to produce is carried out synchronously; Produce synchronizing signal by same contact button, be sent to each road DDS its program is brought into operation from the same instructions position; Produce the binary phase control code by switch, the CPU of DDS is according to phase control code and the present procedure next round-robin of the determining positions position of tabling look-up of tabling look-up, thereby realizes that phase place switches.
In a preferred embodiment of described method for synchronous, be used for being connected with latch after the synchronous contact button, the output terminal of latch is drawn the synchronous end that multiple signals are delivered to all CPU, but has only the control end of the CPU of first via DDS to link to each other with the control end of described latch.
In the described method for synchronous, in each program loop of first via DDS signal, carry out the operation of opening latch control end, closing control end and read latch output terminal successively.Mending time delay command in the program of other channel DDS equates to keep cycle period.
In described method for synchronous, provide one group of phase control switch to each road DDS, connect latch behind all phase control switch, the output of latch is connected on the phase control end of CPU separately correspondingly, and the control end of described latch links to each other with CPU.
Description of drawings:
Fig. 1 is the structured flowchart according to three road DDS signal generators of a specific embodiment of the present invention.
Embodiment:
Below in conjunction with description of drawings the specific embodiment of the present invention.
Figure 1 shows that the structured flowchart that makes up voltage ratio with three road DDS signal generators.。
More than three road DDS all include an independently Single Chip Microcomputer (SCM) system, comprising CPU and storer.The signal that three road CPU all send with same oscillator is as clock, clock synchronously down, the instruction of each road CPU action has identical starting and ending constantly.What realize each road DDS clock is to realize the synchronous basis of output signal synchronously.
In order to guarantee the synchronous of each road DDS final output signal, be provided with a contact button and be used to produce synchronous triggering signal.Be connected with a latch after the contact button, the control end of latch links to each other with first via CPU, and the output of latch is then linked on three road CPU simultaneously.After button actions produced triggering level, this level at first arrived the input end of latch.In each program loop of first via DDS program, carry out the operation of opening latch control end, closing control end and read latch output terminal successively, triggering level was maintained at output terminal and sent to three road CPU simultaneously this moment.Because the waveform that contact button produces has the parasitic parameter of shake and each road DDS to be not quite similar, constantly different phenomenons can appear on the CPU triggering if directly the signal of contact button generation is linked, and use latch then to realize free from error synchronous triggering.In order to make each road DDS program loop have identical length, in the program of other three road DDS, need to mend the time delay command isometric with above-mentioned instruction.
Each road DDS has one group of phase control switch.Connect latch behind all phase control switch, the output correspondence of latch is linked on the phase control end of each road CPU.In each circulation of DDS program, CPU reads in current phase control code, and with itself and totalizer (being the current position of tabling look-up) sum as the address of inquiring about waveform table next time.Therefore, when the phase control switch state of all road DDS is identical, can produce synchronous output signal; In case change the wherein phase control switch state of one road DDS, promptly can realize the pairing phase differential of phase control code.
Claims (4)
1. the method for synchronous of a multipath DDS (Direct Digital Synthesis) signals is used to make the multipath DDS (Direct Digital Synthesis) signals strict synchronism and resets and do not produce phase error when switching phase place, it is characterized in that, said method comprising the steps of:
A) each road DDS uses the clock signal of same oscillator generation to carry out synchronously;
B) produce reset signal by same contact button, be sent to each road DDS its program is brought into operation from the same instructions position;
C) produce the binary phase control signal by switch, the CPU of DDS is according to phase control signal and the present procedure next round-robin of the determining positions position of tabling look-up of tabling look-up, thereby realizes that phase place switches.
2. the method for synchronous of multipath DDS (Direct Digital Synthesis) signals according to claim 1, it is characterized in that, connect latch after reset button, the output terminal of latch is drawn the synchronous end that multiple signals are delivered to all CPU, has only the control end of the CPU of first via DDS to link to each other with the control end of described latch.
3. the method for synchronous of multipath DDS (Direct Digital Synthesis) signals according to claim 1, it is characterized in that, in each program loop of first via DDS signal, carry out the operation of opening latch control end, closing control end and read latch output terminal successively, in the program of other channel DDS, mend time delay command and equate to keep cycle period.
4. the method for synchronous of multipath DDS (Direct Digital Synthesis) signals according to claim 1, it is characterized in that, provide one group of phase control switch to each road DDS, connect latch behind all phase control switch, the output of latch is connected on the phase control end of CPU separately correspondingly, and the control end of described latch links to each other with CPU.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101563937A CN101819450B (en) | 2010-04-27 | 2010-04-27 | Method for synchronizing multipath DDS (Direct Digital Synthesis) signals |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101563937A CN101819450B (en) | 2010-04-27 | 2010-04-27 | Method for synchronizing multipath DDS (Direct Digital Synthesis) signals |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101819450A true CN101819450A (en) | 2010-09-01 |
| CN101819450B CN101819450B (en) | 2011-11-02 |
Family
ID=42654579
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010101563937A Expired - Fee Related CN101819450B (en) | 2010-04-27 | 2010-04-27 | Method for synchronizing multipath DDS (Direct Digital Synthesis) signals |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101819450B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102571036A (en) * | 2011-12-07 | 2012-07-11 | 中国电子科技集团公司第十研究所 | Method for generating any accurate frequency by using DDS (Direct Digital Synthesizer) |
| CN104635002A (en) * | 2015-01-20 | 2015-05-20 | 国家电网公司 | Three-phase two-waveform adjustable phase angle signal generating equipment for electric power system |
| CN108663306A (en) * | 2018-07-27 | 2018-10-16 | 北京指真生物科技有限公司 | A kind of flow cytometry device and compensation method |
| CN114167136A (en) * | 2021-11-23 | 2022-03-11 | 成都泰盟软件有限公司 | Impedance method for sampling multiple frequencies by using single channel |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5231598A (en) * | 1991-09-30 | 1993-07-27 | National Semiconductor Corporation | Direct digital synthesis measurement signal skew tester |
| CN101339446A (en) * | 2008-07-18 | 2009-01-07 | 电子科技大学 | Double channel synchronous DDS device capable of modulating phase and amplitude |
| CN201266240Y (en) * | 2008-10-14 | 2009-07-01 | 武汉大学 | High band multichannel DDS signal generator |
-
2010
- 2010-04-27 CN CN2010101563937A patent/CN101819450B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5231598A (en) * | 1991-09-30 | 1993-07-27 | National Semiconductor Corporation | Direct digital synthesis measurement signal skew tester |
| CN101339446A (en) * | 2008-07-18 | 2009-01-07 | 电子科技大学 | Double channel synchronous DDS device capable of modulating phase and amplitude |
| CN201266240Y (en) * | 2008-10-14 | 2009-07-01 | 武汉大学 | High band multichannel DDS signal generator |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102571036A (en) * | 2011-12-07 | 2012-07-11 | 中国电子科技集团公司第十研究所 | Method for generating any accurate frequency by using DDS (Direct Digital Synthesizer) |
| CN104635002A (en) * | 2015-01-20 | 2015-05-20 | 国家电网公司 | Three-phase two-waveform adjustable phase angle signal generating equipment for electric power system |
| CN104635002B (en) * | 2015-01-20 | 2017-12-08 | 国家电网公司 | The waveform adjustable phase angle signal occurrence of equipment of Three-phase Power Systems two |
| CN108663306A (en) * | 2018-07-27 | 2018-10-16 | 北京指真生物科技有限公司 | A kind of flow cytometry device and compensation method |
| CN108663306B (en) * | 2018-07-27 | 2024-02-09 | 北京指真生物科技有限公司 | Flow cytometry analysis device and compensation method |
| CN114167136A (en) * | 2021-11-23 | 2022-03-11 | 成都泰盟软件有限公司 | Impedance method for sampling multiple frequencies by using single channel |
| CN114167136B (en) * | 2021-11-23 | 2024-05-24 | 成都泰盟软件有限公司 | Impedance method for sampling multiple frequencies by using single channel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101819450B (en) | 2011-11-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101819450B (en) | Method for synchronizing multipath DDS (Direct Digital Synthesis) signals | |
| CN101820500B (en) | Slave device, time synchronization method in slave device, master device, and electronic equipment system | |
| CN202041623U (en) | Tester for electromagnetic relays | |
| CN108233906B (en) | Starting-up deterministic delay system and method based on ADC | |
| CN103529689B (en) | Active and standby satellite clock time frequency signal seamless switching device and method | |
| CN101103277A (en) | Instrument with interface for synchronization in automatic test equipment | |
| TWI690161B (en) | Method for synchronizing data converters with a signal transmitted from converter to converter | |
| CN102707766B (en) | signal synchronization device | |
| CN104267638A (en) | Serializer/deserializer clock source based on clock managers and FPGA | |
| KR20050038209A (en) | Clock signal selecting device and method for guaranting its clock continuity | |
| CN104683057B (en) | A kind of method and system of the time synchronization of more instrument cubicles | |
| CN109525354A (en) | A kind of serial ports timing device and its configuration method based on toggle switch control | |
| CN116560457B (en) | Inter-clock domain synchronization circuit and method based on IIC communication | |
| CN113491082B (en) | Data processing device | |
| US8804887B2 (en) | Transmission and receiving apparatus and method having different sending and receiving clocks | |
| JP5573867B2 (en) | Clock phase synchronization apparatus and clock phase synchronization method | |
| US20220260635A1 (en) | Circuit for transferring data from one clock domain to another | |
| CN109245759A (en) | Level shifting circuit | |
| TW201303533A (en) | Method and system for measuring distance | |
| CN116131821A (en) | High-precision delay clock calibration circuit and chip | |
| CN208797919U (en) | A kind of circuit with multimode detection function | |
| Deev et al. | Subnanosecond synchronization method based on the synchronous Ethernet network | |
| CN105137753A (en) | Beidou multifunctional timing system | |
| CN112654082A (en) | Timing device, base station, positioning system, calibration method and positioning method | |
| CN116827335B (en) | Frequency divider and data processing circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20111102 Termination date: 20210427 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |