CN101778280B - Circuit and method based on AVS motion compensation interpolation - Google Patents
Circuit and method based on AVS motion compensation interpolation Download PDFInfo
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Abstract
The invention relates to a circuit and a method based on AVS motion compensation interpolation, which belong to the technical field of audio and video digital encoding and decoding; the circuit comprises integer-pixel memories I and II, bh and j pixel memories, a memory interface module, one-second and one-fourth pixel interpolation filters, a multiplexer and an adjusting amplitude limiter; the output ends of the circuit comprises integer-pixel memories I and II and the bh and j pixel memories are connected with the input end of the memory interface module; the output end of the memory interface module is respectively connected with the input ends of the one-second and one-fourth pixel interpolation filters; the output ends of the one-second and one-fourth pixel interpolation filters are respectively connected with the input end of the multiplexer; the output end of the one-second pixel interpolation filter is respectively connected with the input ends of the bh and j pixel memories; and the output end of the multiplexer is connected with the input end of the adjusting amplitude limiter, and interpolation results are output by the adjusting amplitude limiter. The invention carries out interpolation operation by the means of improving system parallelism, thereby effectively improving the system performance.
Description
Affiliated technical field
The present invention relates to audio frequency and video numeral encoding and decoding technique field, relate in particular to a kind of circuit and method based on AVS (digital audio/video encoding and decoding technique standard) motion compensation luminance interpolation computing.
Background technology
AVS (Audio Video Coding Standard) is an Audio Video coding Standard, is the national standard that China has independent intellectual property right, and its video section was national standard in February, 2006 by Information Industry Department's promulgation, in enforcement on March 1 in 2006.This standard is mainly towards high definition and High-Quality Digital Television broadcasting, digital storage media and other related application.Estimation and motion compensation are the main method of removing time redundancy in the AVS encoding-decoding process.Because the proper motion object has continuity,, therefore need to use the interpolative prediction of fraction pixel in the prediction residual minimum of only using between video sequence two frames after the integer pixel prediction can not effectively make motion compensation.The problem that adopts " fraction pixel " precision motion vector to bring is that motion vector may point to the position between the reference picture integer pixel, in order to obtain the pixel value of these positions, needs with reference to carrying out filtering interpolation with these position adjacent pixels.
Use the non-integer pixel motion estimation and compensation in the AVS standard, wherein monochrome information adopts 1/4 pixel precision interpolation, and chrominance information adopts 1/8 pixel precision interpolation.AVS has defined two kind of four tap filter---four tap F1 filters (1 of prediction two/the same this position, 5,5,-1) with the four tap F2 filter (1 of predicting four/the same this position, 7,7,1), the method for use filtering interpolation is calculated the brightness interpolating of 1/2 location of pixels and 1/4 location of pixels.Ask half-pix to obtain, ask 1/4 pixel to obtain by using four tap F2 filters to carry out filtering to adjacent 4 integer pixels or half-pix by using four tap F1 filters to carry out filtering to 4 adjacent integer pixels of colleague/row.When asking half-pix point, the point-diagonal angle half-pix point of a specific position is arranged, need reuse four tap F1 filters and 4 adjacent half-pix points are carried out filtering just can obtain.Detail can be with reference to the AVS standard document.Therefore, when carrying out the AVS motion compensation luminance interpolation, data all are to choose according to the position that pixel shows.AVS interpolation arithmetic circuit generally adopts the outer jumbo memory cell such as SDRAM of sheet to store the used reference frame of interpolation at present, the inner buffer that adopts based on FIFO or SRAM is input to the value that sheet interpolate value device calculates fraction pixel point by the pixel value of selecting respective point in SDRAM or the SRAM.People such as Chen Guanghua are at SignalProcessing, 2008.ICSP " An Efficient VLSI Architecture of Sub-pixel Interpolator forAVS Encoder " (Signal Processing that is delivered on the 2008.9th International Conference (international conference in a signal processing field), 2008.ICSP the 1255th page of 2008.9th International Conference on), what adopt is exactly this outside mass storage that uses, the inner structure that adopts input buffer.Jumbo external memory storage can reduce cost, but the related data of directly obtaining each interpolation point by access sdram can produce two aspect deficiencies:
1. sdram memory storage pixel is generally deposited in proper order by the mode of raster scan, and data are pressed the increase sequential storage of address in mass storage, no longer become Two dimensional Distribution according to the position that shows.When carrying out interpolation calculation, need frequent each position corresponding address of calculating when choosing adjacent position point pixel.And when calculating the interpolation of diverse location point, may use the point of some same position, cause the redundancy when fetching data.Therefore the access pressure of memory is huge, becomes to improve the interpolation arithmetic bottleneck of performance.
2. owing to the restriction of SDRAM access port, the degree of parallelism of interpolation arithmetic is not high, and heightening of AVS interpolation arithmetic circuit performance mainly is to rely on the progression that increases streamline to realize.Yet, when the progression of streamline acquires a certain degree, increase streamline the effect of improving of performance just become very limited.And along with the rising of system frequency, it is big that system power dissipation also can become thereupon.
As everyone knows, the degree of parallelism that improves system is one of effective means that significantly improves systematic function, if therefore can improve the degree of parallelism of interpolation arithmetic, can improve the performance of system effectively.
Summary of the invention
For defective and the deficiency that overcomes prior art, the invention provides a kind of circuit and method based on the computing of AVS motion compensation luminance interpolation, to reduce visit pressure to external memory storage, the degree of parallelism that can improve system simultaneously guarantees the real-time decoding of HD video to accelerate the processing speed of interpolation arithmetic.
Technical solution of the present invention is as follows:
A kind of circuit based on the computing of AVS motion compensation luminance interpolation, comprise integer pixel memory I, integer pixel memory I I, bh class pixel memories, j class pixel memories, memory interface module, 1/2 pixel interpolation filtering device, 1/4 pixel interpolation filtering device, MUX (MUX) and adjust amplitude limiter, it is characterized in that the output of integer pixel memory I, integer pixel memory I I, bh class pixel memories and j class pixel memories is connected to the input of memory interface module; The output of memory interface module is connected respectively to the input of 1/2 pixel interpolation filtering device and 1/4 pixel interpolation filtering device; The output of 1/2 pixel interpolation filtering device and 1/4 pixel interpolation filtering device is connected respectively to the input of MUX; The output of 1/2 pixel interpolation filtering device is connected respectively to the input of bh class pixel memories and j class pixel memories simultaneously; The output of MUX is connected to the input of adjusting amplitude limiter, and interpolation result is finally by adjusting amplitude limiter output.
Integer pixel memory I recited above and integer pixel memory I I storage are from the integer pixel piece of the interpolation of outside SDRAM, when the block of pixels in using one of them memory was carried out interpolation arithmetic, another memory received the block of pixels of next interpolation;
The bh class location of pixels median that produces in the above-mentioned bh class pixel memories storage interpolation arithmetic process;
The bh class location of pixels median that produces in the above-mentioned j class pixel memories storage interpolation arithmetic process;
The required data storage of each computing is selected in the selection of above-mentioned memory interface module control storage;
1/2 above-mentioned pixel interpolation filtering device is realized the function of four tap interpolation filter F1 (1,5,5 ,-1);
1/4 above-mentioned pixel interpolation filtering device is realized the function of four tap interpolation filter F2 (1,7,7,1);
Above-mentioned MUX (MUX) selects the output of 1/2 pixel interpolation filtering device or the output of 1/4 pixel interpolation filtering device to deliver to the adjustment amplitude limiter;
The median that above-mentioned adjustment amplitude limiter adjustment and restriction interpolation arithmetic obtain makes its size between 0-255.
Described integer pixel memory I, integer pixel memory I I, bh class pixel memories and j class pixel memories adopt based on the storage array of shift register comes the storage pixel piece according to the display position of pixel.
Described storage array based on shift register comprises storage array input controller, memory cell array and storage array o controller; The storage array input controller links to each other with memory cell array, the storing process of control store cell array; Memory cell array links to each other with the storage array o controller, the process that reads of output controller controls memory cell array.Can read in the data of the whole interpolation piece after the expansion from outside SDRAM based on the storage array of shift register, and be positioned in each inner memory cell according to DISPLAY ORDER.When dateout arrives the interpolation arithmetic module, can be according to the requirement of interpolation, according to row or row output.For the storage array based on shift register of 12 * 12 arrays, once can export 1-12 capable/row.Interpolation circuit provided by the present invention is once exported 4 row/row;
The memory cell array of described storage array based on shift register is made of memory cell, memory cell array storage inside data become Two dimensional Distribution according to the display position of pixel, memory cell by one group of MUX, one or and one group of d type flip flop constitute; The output of MUX is connected to the input of d type flip flop; Or the output of door is connected to the Enable Pin of d type flip flop.MUX selects signal to select line data input or columns to be connected to the input of d type flip flop according to input according to ranks.Exercise the Enable Pin that energy signal and row enable to carry out being connected to after " logic OR " operated d type flip flop.The number of d type flip flop is identical with the figure place of the pixel of storage, is 8 in this example;
Described 1/2 pixel interpolation filtering device comprises 4 parallel four tap F1 filters of placing (1,5,5 ,-1), and these four four tap filters are parallel to be connected, and can handle four tunnel input data simultaneously;
Described four tap F1 filters are formed by 4 processing units (being abbreviated as PE) cascade, constitute the one dimension systolic array architecture that input is broadcasted, the result moves, weight keeps; Each processing unit is made up of multiplier, adder and d type flip flop, and wherein the output of multiplier is connected to the input of adder, and the output of adder is connected to the output of d type flip flop.
Described 1/4 pixel interpolation filtering device comprises 4 parallel four tap F2 filters of placing (1,7,7,1), and these four four tap filters are parallel to be connected, and can handle four tunnel input data simultaneously;
Described adjustment amplitude limiter comprises 4 parallel adjustment amplitude limit unit of placing, and adjusts the parallel connection in amplitude limit unit, can adjust amplitude limiting processing to the pixel median after 4 tunnel interpolation simultaneously for these four.
A kind of foregoing circuit that utilizes carries out method based on the computing of AVS motion compensation luminance interpolation, and step is as follows:
(1) block of pixels of interpolation is delivered to integer pixel memory I/II;
(2) use 1/2 pixel interpolation filtering device to ask level, vertical half-pix point to the pixel value in integer pixel memory I/II;
(3) use 1/2 pixel interpolation filtering device to ask diagonal angle half-pix point to the pixel value in the bh class pixel memories; Step (2) is obtained horizontal or vertical half-pix point median, use filter F1, select 4 nearest half-pix values of colleague/row to carry out filtering, obtain median j ';
(4) use 1/4 pixel interpolation filtering device that integer pixel or half-pix are carried out filtering and ask 1/4 pixel; For a in the AVS standard, c, d, n, i, k, f, the q location point uses filter F2, and nearest 4 integer pixels and half-pix point are carried out filtering, obtains median a ', c ', d ', n ', i ', k ', f ', q '; For the e in the AVS standard, g, p, the r location point with diagonal angle integer pixel adjusted value and diagonal angle half-pix j ' addition, obtains median e ', g ', p ', r ';
(5) use the adjustment amplitude limiter that the median of desired interpolation point is carried out following processing:
Interpolation＝Clip1((Interpolation′+NUMB)＞＞numb)
Wherein Interpolation is the fraction pixel point that requires, Interpolation ' is the median of the interpolation point asked, MUMB is 4,32,64 or 512, occurrence is determined by the position of asking fraction pixel point, numb is a carry digit, value is 3,6,7 or 10, and occurrence is determined by the position of asking fraction pixel point; If ask level or vertical 1/2 pixel, carry out the calculating of step (1), (2) and (4); If ask diagonal angle 1/2 pixel, carry out the calculating of step (1), (2), (3) and (4); If ask 1/4 pixel, then carry out the calculating of step (1), (2), (3), (4) and (5), the final result after the above-mentioned processing is by adjusting amplitude limiter output.
The invention is characterized in: the luminance block of utilizing the corresponding hardware circuit to take out interpolation from outside SDRAM, when depositing the integer pixel memory I in, integer pixel memory I I is stored the device interface module and selects to carry out interpolation arithmetic; Equally, when integer pixel memory I I received outside SDRAM interpolation piece, the integer pixel memory I was carried out interpolation arithmetic.Memory interface module is selected the integer pixel memory I, integer pixel memory I I, and bh class pixel memories, the respective memory dateout is to 1/2 pixel interpolation filtering or 1/4 pixel interpolation filtering device in these four memories of j class pixel memories.The result of interpolation is temporary to bh class pixel memories, j class pixel memories according to the different choice of location of interpolation, perhaps exports to adjustment amplitude limit module and adjusts amplitude limiting processing.The pairing hardware circuit of the present invention adopts the storage array based on shift register, treats the parallel processing that the interpolating pixel piece carries out multirow/row, can handle 4 row or column data in the piece simultaneously, carries out 4 tunnel parallel processings.
Circuit of the present invention and method adopt outside SDRAM to add inner storage array based on shift register, and it is big to have memory capacity with respect to prior art, the advantage that cost is low, thus improved the performance of hardware circuit.Take out a bigger piece from outside SDRAM at every turn, alleviated visit pressure, reduced the complexity of address-generation unit address decoding simultaneously memory.The DI memory has reduced the stand-by period of interpolation arithmetic to transfer of data.Based on the storage array of shift register, interpolation arithmetic can carry out filtering interpolation to 4 row/row at every turn, has effectively improved the degree of parallelism of circuit, has heightened interpolation efficiency.For picture format is that 4:2:0, image size are 1920 * 1080, frame frequency is the HD video of 30fps, and the interpolation arithmetic of finishing a macro block only needs 40-90 clock cycle, and prior art then needs 200 above cycles.
Description of drawings
Fig. 1 is the structural representation of circuit of the present invention;
Wherein: 1, integer pixel memory I, 2, integer pixel memory I I, 3, bh class pixel memories, 4, j class pixel memories, 5, memory interface module, 6,1/4 pixel interpolation filtering device, 7,1/2 pixel interpolation filtering device, 8, MUX, 9, adjust amplitude limiter.
Fig. 2 is 1/4 pixel interpolation filtering device shown in Fig. 1,1/2 pixel interpolation filtering device and the structural representation of adjusting amplitude limiter;
Wherein: 10, F2 filter, 11, the F1 filter, 12, adjust the amplitude limit unit.
1/4 pixel interpolation filtering device 6 comprises four parallel four tap F2 filters of placing 10, these 10 parallel connections of four four tap F2 filters, can handle four tunnel input data simultaneously;
1/2 pixel interpolation filtering device 7 comprises four parallel four tap F1 filters of placing 11, these 11 parallel connections of four four tap F1 filters, can handle four tunnel input data simultaneously;
Adjust amplitude limiter 9 and comprise four parallel adjustment amplitude limit unit of placing 12, adjust 12 parallel connections of amplitude limit unit, can adjust amplitude limiting processing to the pixel median after four tunnel interpolation simultaneously for these four.
Fig. 3 is based on the memory array structure schematic diagram of shift register in the integer pixel memory I shown in Fig. 1, integer pixel memory I I, bh class pixel memories and the j class pixel memories;
Wherein: 13, storage array input controller, 14, memory cell array, 15, the storage array o controller, 16, memory cell, memory cell array 14 is made of memory cell 16.
Fig. 4 is the structural representation of the memory cell 16 in the memory cell array 14 shown in Fig. 3;
Wherein: 17, MUX, 18 or door, 19, d type flip flop.The output of MUX 17 is connected to the input of d type flip flop 19; Or the output of door 18 is connected to the Enable Pin of d type flip flop 19.
Fig. 5 is the one dimension systolic array architecture schematic diagram in the four tap F1 filters 11 shown in Fig. 2.
Wherein: 20, processing unit (PE).Four tap F1 filters 11 are formed by four processing units (PE), 20 cascades.
Fig. 6 is the structural representation of the processing unit shown in Fig. 5 (PE) 20.
Wherein: 21, multiplier, 22, adder, 23, d type flip flop.The input of multiplier 21 is connected to the input of adder 22; The output of adder 22 is connected to the input of d type flip flop 23.
Fig. 7 is the position distribution of brightness fraction pixel among the AVS.
Wherein: the square that contains alphabetical A, B, C, D, E, F, G, H, I, J, K, L is represented the position at integer pixel place; The circle that contains alphabetical aa, ff, hh, ee, b, bb, gg, h, j, m, cc, s, dd is represented the position at 1/2 pixel place; The circle that contains alphabetical a, c, d, e, f, g, i, k, n, p, q, r is represented the position at 1/4 pixel place;
Fig. 8 is the process blocks schematic diagram of the method for interpolation arithmetic of the present invention.Wherein (1)-(5) are its each step.
Embodiment
The invention will be further described below in conjunction with accompanying drawing and embodiment, but be not limited thereto.
Embodiment 1:
A kind of circuit based on the computing of AVS motion compensation luminance interpolation, as shown in Figure 1, comprise integer pixel memory I 1, integer pixel memory I I2, bh class pixel memories 3, j class pixel memories 4, memory interface module 5,1/2 pixel interpolation filtering device 6,1/4 pixel interpolation filtering device 7, MUX (MUX) 8 and adjust amplitude limiter 9, it is characterized in that the output of integer pixel memory I 1, integer pixel memory I I2, bh class pixel memories 3 and j class pixel memories 4 is connected to the input of memory interface module 5; The output of memory interface module 5 is connected respectively to the input of 1/2 pixel interpolation filtering device 6 and 1/4 pixel interpolation filtering device 7; The output of 1/2 pixel interpolation filtering device 6 and 1/4 pixel interpolation filtering device 7 is connected respectively to the input of MUX 8; The output of 1/2 pixel interpolation filtering device 6 is connected respectively to the input of bh class pixel memories 3 and j class pixel memories 4 simultaneously; The output of MUX 8 is connected to the input of adjusting amplitude limiter 9, and interpolation result is finally by adjusting amplitude limiter 9 outputs.
Integer pixel memory I I recited above and integer pixel memory I I2 storage are from the integer pixel piece of the interpolation of outside SDRAM, when the block of pixels in using one of them memory was carried out interpolation arithmetic, another memory received the block of pixels of next interpolation.
Described integer pixel memory I 1, integer pixel memory I I2, bh class pixel memories 3 and j class pixel memories 4 adopt based on the storage array of shift register comes the storage pixel piece according to the display position of pixel.
Described storage array based on shift register as shown in Figure 3, comprises storage array input controller 13, memory cell array 14 and storage array o controller 15; Storage array input controller 13 links to each other with memory cell array 14, the storing process of control store cell array 14; Memory cell array 14 links to each other with storage array o controller 15, the process that reads of output controller controls memory cell array 14.Can read in the data of the whole interpolation piece after the expansion from outside SDRAM based on the storage array of shift register, and be positioned in each inner memory cell according to DISPLAY ORDER.When dateout arrives the interpolation arithmetic module, can be according to the requirement of interpolation, according to row or row output.For the storage array based on shift register of 12 * 12 arrays, once can export 1-12 capable/row.Interpolation circuit provided by the present invention is once exported 4 row/row;
The memory cell array of described storage array based on shift register is made of memory cell, as shown in Figure 3-4, memory cell array 14 storage inside data become Two dimensional Distribution according to the display position of pixel, memory cell 16 by one group of MUX, one or and one group of d type flip flop constitute; The output of MUX is connected to the input of d type flip flop; Or the output of door is connected to the Enable Pin of d type flip flop.MUX selects signal to select line data input or columns to be connected to the input of d type flip flop according to input according to ranks.Exercise the Enable Pin that energy signal and row enable to carry out being connected to after " logic OR " operated d type flip flop.The number of d type flip flop is identical with the figure place of the pixel of storage, is 8 in this example;
As shown in Figure 2, described 1/2 pixel interpolation filtering device 7 comprises 4 parallel four tap F1 filters of placing 11 (1,5,5 ,-1), and these four four tap filters are parallel to be connected, and can handle four tunnel input data simultaneously;
As shown in Figure 5, described four tap F1 filters 11 are formed by 4 processing unit 20 cascades, constitute the one dimension systolic array architecture that input is broadcasted, the result moves, weight keeps; As shown in Figure 6, each processing unit 20 is made up of multiplier 21, adder 22 and d type flip flop 23, and wherein the output of multiplier 21 is connected to the input of adder 22, and the output of adder 22 is connected to the output of d type flip flop 23.
As shown in Figure 2, described 1/4 pixel interpolation filtering device 6 comprises 4 parallel four tap F2 filters of placing 10 (1,7,7,1), and these four four tap filters are parallel to be connected, and can handle four tunnel input data simultaneously;
As shown in Figure 2, described adjustment amplitude limiter 9 comprises 4 parallel adjustment amplitude limit unit of placing, and adjusts the parallel connection in amplitude limit unit, can adjust amplitude limiting processing to the pixel median after 4 tunnel interpolation simultaneously for these four.
Embodiment 2:
A kind of foregoing circuit that utilizes carries out based on the method for AVS motion compensation luminance interpolation computing as shown in Figure 8, and step is as follows:
(1) block of pixels of interpolation is delivered to integer pixel memory I/II;
(2) use 1/2 pixel interpolation filtering device to ask level, vertical half-pix point to the pixel value in integer pixel memory I/II;
(3) use 1/2 pixel interpolation filtering device to ask diagonal angle half-pix point to the pixel value in the bh class pixel memories; Step (2) is obtained horizontal or vertical half-pix point median, use filter F1, select 4 nearest half-pix values of colleague/row to carry out filtering, obtain median j ';
(4) use 1/4 pixel interpolation filtering device that integer pixel or half-pix are carried out filtering and ask 1/4 pixel; For a in the AVS standard, c, d, n, i, k, f, the q location point uses filter F2, and nearest 4 integer pixels and half-pix point are carried out filtering, obtains median a ', c ', d ', n ', i ', k ', f ', q '; For the e in the AVS standard, g, p, the r location point with diagonal angle integer pixel adjusted value and diagonal angle half-pix j ' addition, obtains median e ', g ', p ', r ';
(5) use the adjustment amplitude limiter that the median of desired interpolation point is carried out following processing:
Interpolation＝Clip1((Interpolation′+NUMB)＞＞numb)
Wherein Interpolation is the fraction pixel point that requires, Interpolation ' is the median of the interpolation point asked, MUMB is 4,32,64 or 512, occurrence is determined by the position of asking fraction pixel point, numb is a carry digit, value is 3,6,7 or 10, and occurrence is determined by the position of asking fraction pixel point; If ask level or vertical 1/2 pixel, carry out the calculating of step (1), (2) and (4); If ask diagonal angle 1/2 pixel, carry out the calculating of step (1), (2), (3) and (4); If ask 1/4 pixel, then carry out the calculating of step (1), (2), (3), (4) and (5), the final result after the above-mentioned processing is by adjusting amplitude limiter output.
Claims (9)
1. circuit based on the computing of AVS motion compensation luminance interpolation, comprise the integer pixel memory I, integer pixel memory I I, bh class pixel memories, j class pixel memories, memory interface module, 1/2 pixel interpolation filtering device, 1/4 pixel interpolation filtering device, MUX (MUX) and adjustment amplitude limiter is characterized in that the integer pixel memory I, integer pixel memory I I, the output that the output of bh class pixel memories and j class pixel memories is connected to the input memory interface module of memory interface module is connected respectively to the input of 1/2 pixel interpolation filtering device and 1/4 pixel interpolation filtering device; The output of 1/2 pixel interpolation filtering device and 1/4 pixel interpolation filtering device is connected respectively to the input of MUX; The output of 1/2 pixel interpolation filtering device is connected respectively to the input of bh class pixel memories and j class pixel memories simultaneously; The output of MUX is connected to the input of adjusting amplitude limiter, and interpolation result is finally by adjusting amplitude limiter output.
2. a kind of circuit based on the computing of AVS motion compensation luminance interpolation as claimed in claim 1, it is characterized in that described integer pixel memory I, integer pixel memory I I, bh class pixel memories and j class pixel memories adopt based on the storage array of shift register comes the storage pixel piece according to the display position of pixel.
3. a kind of circuit based on the computing of AVS motion compensation luminance interpolation as claimed in claim 2 is characterized in that described storage array based on shift register comprises storage array input controller, memory cell array and storage array o controller; The storage array input controller links to each other with memory cell array, the storing process of control store cell array; Memory cell array links to each other with the storage array o controller, the process that reads of output controller controls memory cell array.
4. a kind of circuit as claimed in claim 3 based on the computing of AVS motion compensation luminance interpolation, the memory cell array that it is characterized in that described storage array based on shift register is made of memory cell, and memory cell array storage inside data become Two dimensional Distribution according to the display position of pixel; Memory cell by one group of MUX, one or and one group of d type flip flop constitute; The output of MUX is connected to the input of d type flip flop; Or the output of door is connected to the Enable Pin of d type flip flop; MUX selects signal to select line data input or columns to be connected to the input of d type flip flop according to input according to ranks; Exercise the Enable Pin that energy signal and row enable signal carry out being connected to after " logic OR " operated d type flip flop.
5. a kind of circuit as claimed in claim 1 based on the computing of AVS motion compensation luminance interpolation, it is characterized in that described 1/2 pixel interpolation filtering device comprises 4 parallel four tap F1 filters of placing (1,5,5,-1), these four four tap F1 filters are parallel to be connected, and can handle four tunnel input data simultaneously.
6. a kind of circuit based on the computing of AVS motion compensation luminance interpolation as claimed in claim 5 is characterized in that described four tap F1 filters are formed by 4 processing unit cascades, constitutes the one dimension systolic array architecture that input is broadcasted, the result moves, weight keeps; Each processing unit is made up of multiplier, adder and d type flip flop, and wherein the output of multiplier is connected to the input of adder, and the output of adder is connected to the output of d type flip flop.
7. a kind of circuit as claimed in claim 1 based on the computing of AVS motion compensation luminance interpolation, it is characterized in that described 1/4 pixel interpolation filtering device comprises 4 parallel four tap F2 filters of placing (1,7,7,1), these four four tap F2 filters are parallel to be connected, and can handle four tunnel input data simultaneously.
8. a kind of circuit as claimed in claim 1 based on the computing of AVS motion compensation luminance interpolation, it is characterized in that described adjustment amplitude limiter comprises 4 parallel adjustment amplitude limit unit of placing, adjust the parallel connection in amplitude limit unit, can adjust amplitude limiting processing to the pixel median after 4 tunnel interpolation simultaneously for these four.
9. one kind is utilized the described circuit of claim 1 to carry out method based on the computing of AVS motion compensation luminance interpolation, and step is as follows:
(1) block of pixels of interpolation is delivered to integer pixel memory I or II;
(2) use 1 or 2 pixel interpolation filtering devices to ask level, vertical half-pix point to the pixel value in integer pixel memory I or the II;
(3) use 1 or 2 pixel interpolation filtering devices to ask diagonal angle half-pix point to the pixel value in the bh class pixel memories; Step (2) is obtained horizontal or vertical half-pix point median, use 1/2 pixel interpolation filtering device F1, select to carry out filtering, obtain median j ' with 4 nearest half-pix values of row or column;
(4) use 1/4 pixel interpolation filtering device that integer pixel or half-pix are carried out filtering and ask 1/4 pixel; For a in the AVS standard, c, d, n, i, k, f, the q location point uses 1/4 pixel interpolation filtering device F2, and nearest 4 integer pixels and half-pix point are carried out filtering, obtains median a ', c ', d ', n ', i ', k ', f ', q '; For the e in the AVS standard, g, p, the r location point with diagonal angle integer pixel adjusted value and median j ' addition, obtains median e ', g ', p ', r ';
(5) use the adjustment amplitude limiter that the median of desired interpolation point is carried out following processing:
Interpolation＝Clipl((Interpolation′+NUMB)>>numb)
Wherein Interpolation is the fraction pixel point that requires, Interpolation ' is the median of the interpolation point asked, MUMB is 4,32,64 or 512, occurrence is determined by the position of asking fraction pixel point, numb is a carry digit, value is 3,6,7 or 10, and occurrence is determined by the position of asking fraction pixel point; If ask level or vertical 1/2 pixel, the order computation of (1), (2) and (4) set by step; If ask diagonal angle 1/2 pixel, the order computation of (1), (2), (3) and (4) set by step; If ask 1/4 pixel, the order computation of (1), (2), (3), (4) and (5) then set by step, the final result after the above-mentioned processing is exported by adjusting amplitude limiter.
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| KR101855975B1 (en) * | 2011-06-24 | 2018-05-09 | 가부시키가이샤 엔.티.티.도코모 | Method and apparatus for motion compensation prediction |
| US10321151B2 (en) | 2014-04-01 | 2019-06-11 | Mediatek Inc. | Method of adaptive interpolation filtering in video coding |
| CN104734668B (en) * | 2015-03-31 | 2017-11-07 | 中国科学院微电子研究所 | A kind of interpolation filter |
| CN109615580B (en) * | 2018-11-28 | 2022-12-30 | 北京集创北方科技股份有限公司 | Digital processing circuit |
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2010
- 2010-01-14 CN CN 201010011441 patent/CN101778280B/en not_active Expired - Fee Related
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI652899B (en) | 2016-02-24 | 2019-03-01 | 聯發科技股份有限公司 | Reconfigurable interpolation filter and associated interpolation filtering method |
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