CN109615580B - Digital processing circuit - Google Patents
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- CN109615580B CN109615580B CN201811438482.3A CN201811438482A CN109615580B CN 109615580 B CN109615580 B CN 109615580B CN 201811438482 A CN201811438482 A CN 201811438482A CN 109615580 B CN109615580 B CN 109615580B
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- G06T3/4007—Scaling of whole images or parts thereof, e.g. expanding or contracting based on interpolation, e.g. bilinear interpolation
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Abstract
A digital processing circuit is disclosed, the circuit comprising: the storage unit is used for storing a plurality of sub-arrays, each sub-array is extracted from the basic point array, and each basic point in the basic point array has corresponding basic point coordinates and basic point values; a plurality of first selectors for selecting coordinates of at least one correlation point adjacent to the insertion point in each sub-array; the second selectors are used for selecting the coordinates of the boundary points of the target interval where the insertion points are located in the basic point array according to the coordinates of the relevant points; and a processing unit which determines the insertion point value based on the base point value corresponding to the coordinates of the plurality of boundary points. The circuit selects the relevant points through the first selector, selects the boundary points from the relevant points through the second selector, determines the target interval where the insertion points are located in a cascading mode through the two types of selectors, and obtains the insertion point values through the basic point array, so that the number of the selectors is reduced, the power consumption of the circuit is reduced, and the stability of the circuit is improved.
Description
Technical Field
The present invention relates to the field of integrated circuit technologies, and in particular, to a digital processing circuit.
Background
The one-dimensional or multi-dimensional interpolation is used for interpolating values among base points with different dimensions through a certain rule so as to obtain a value changing in an area according to the existing lookup table. The linear interpolation is based on the coordinates of the insertion point, the coordinates of the boundary point and the values of the boundary point, and the insertion point value is obtained through weight linear calculation.
In the existing interpolation method, the boundary point of the insertion point is usually directly selected, and then the value of the insertion point is obtained. As shown in fig. 1, a schematic diagram of a one-dimensional interpolation method in the prior art is provided, where a lookup table includes 17 base points P1-P17, and base point information embodied in the lookup table includes base point coordinates and base point values corresponding to the base point coordinates. When the coordinates of the insertion point 10 are defined by two boundary points P13 and P14, P13 is selected as the left boundary point, and P14 is selected as the right boundary point, and then linear weighting is performed based on the point values of the two boundary points to obtain an insertion point value 20. The interpolation method directly selects the boundary points of the interpolation points to obtain the interpolation point values 20, namely, respectively selects the left boundary points from the 16 left correlation points and selects the right boundary points from the 16 right correlation points. However, the hardware integrated circuit for implementing the method has a large number of devices and complicated circuit connection, so that the hardware circuit for implementing the method in the prior art has large power consumption, high cost and poor stability.
Disclosure of Invention
In view of the above problems, it is an object of the present invention to provide a digital processing circuit, thereby reducing power consumption and cost of a hardware circuit implementing an interpolation method, and reducing connection lines between devices to improve stability of the hardware circuit.
According to the present invention, there is provided a digital processing circuit comprising: the storage unit is used for storing a basic point array, and extracting a plurality of sub-arrays from the basic point array, wherein each basic point in the basic point array has corresponding basic point coordinates and basic point values; a plurality of first selectors for selecting coordinates of at least one relevant point adjacent to the insertion point in each of the sub-arrays; a plurality of second selectors used for selecting the coordinates of a plurality of boundary points of the target interval where the insertion point is located in the base point array according to the coordinates of each related point; and a processing unit which determines an insertion point value corresponding to an insertion point based on a base point value corresponding to the coordinates of the plurality of boundary points, wherein the number of base points in at least one of the sub-arrays is less than the number of base points in the base point array.
Optionally, the base points between a plurality of said sub-arrays do not overlap each other.
Optionally, when the base lattice column is an n-dimensional array, the target interval has 2 n N is a positive integer.
Optionally, the number of sub-arrays is equal to the number of boundary points for determining the target interval.
Optionally, the plurality of first selectors are configured to select at least one of the associated point coordinates in each of the sub-arrays.
Alternatively, when the basic dot matrix is a one-dimensional array, the first sub-array is formed of odd-numbered basic dots in the row direction or the column direction, and the second sub-array is formed of even-numbered basic dots in the row direction or the column direction.
Optionally, when the base dot array is a two-dimensional array, the row coordinates of the base dots in the first sub-array are odd numbers and the column coordinates are odd numbers, the row coordinates of the base dots in the second sub-array are even numbers and the column coordinates are odd numbers, the row coordinates of the base dots in the third sub-array are odd numbers and the column coordinates are even numbers, the row coordinates of the base dots in the fourth sub-array are even numbers and the column coordinates are even numbers, wherein the row coordinates of the base dots in each sub-array are the corresponding row numbers of the base dots in the base dot array, and the row coordinates of the base dots in each sub-array are the corresponding column numbers of the base dots in the base dot array.
Optionally, the processing unit obtains the interpolation point value by linear weight calculation based on a base point value corresponding to the coordinates of the plurality of boundary points.
Optionally, the first selector and/or the second selector is a one-out-of-two selector.
The digital processing circuit selects the coordinates of a plurality of related points adjacent to the insertion point in each subarray through the first selector, selects the coordinates of a plurality of boundary points of a target interval where the insertion point is located in the basic point array through the second selector according to the coordinates of the related points, limits the target interval of the insertion point in the basic point array in a mode of cascade connection of the two types of selectors, and determines the insertion point value based on the basic point value corresponding to the coordinates of the boundary points. The digital processing circuit saves the space of a memory for storing the basic point array, and the digital processing circuit provided by the invention can reduce the number of selectors by determining the target interval of the insertion point through the two types of selectors, thereby reducing the power consumption of the circuit and improving the stability of the circuit.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 shows a schematic diagram of a one-dimensional interpolation method according to the prior art;
FIG. 2 shows a schematic block diagram of a digital processing circuit according to an embodiment of the present invention;
FIG. 3 is a flow diagram illustrating an interpolation operation performed by a digital processing circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating interpolation operations performed by the digital processing circuit according to the first embodiment of the present invention;
fig. 5 shows a schematic diagram of a digital processing circuit for interpolation operation according to a second embodiment of the present invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.
The following detailed description of the present invention is provided in connection with the accompanying drawings and examples.
Fig. 2 shows a schematic block diagram of a digital processing circuit according to an embodiment of the invention. Fig. 3 is a flow diagram illustrating an interpolation operation performed by a digital processing circuit according to an embodiment of the present invention.
As shown in fig. 2 and 3, the digital processing circuit 300 of the present invention includes a storage unit 301, a plurality of first selectors 302, a plurality of second selectors 303, and a processing unit 304. The storage unit 301 is configured to store a plurality of sub-arrays, each sub-array being extracted from a base point array, each base point in the base point array having a corresponding base point coordinate and a base point value, the base point array and the sub-arrays being stored in a semiconductor Memory, such as any one of a Read-only Memory (ROM), a Random Access Memory (RAM), and a flash Memory chip. The inputs of a plurality of first selectors 302 are connected to the address ports of the base point in each sub-array in the memory unit 301 for selecting the coordinates of at least one relevant point adjacent to the insertion point in each sub-array. The input terminals of the second selectors 303 are connected to the output terminal of the first selector 302, for example, and are used for selecting the coordinates of the boundary points of the target interval where the insertion point is located in the base point array according to the coordinates of the relevant points. The processing unit 304 is connected to the output terminal of the second selector 303 for receiving the coordinates of the boundary points, reading the corresponding base point values based on the coordinates of the boundary points, and determining the insertion point value corresponding to the insertion point.
Array of base pointsFor an n-dimensional array, the target interval of the insertion point has 2 n N is a positive integer. Wherein, preferably, the number of base points in the sub-array is less than that of the base points in the base point array; preferably, the base points between a plurality of said sub-arrays do not overlap each other; preferably, the number of sub-arrays is equal to the number of boundary points for determining the target interval; preferably, a plurality of first selectors are used to select at least one relevant point coordinate in each sub-array; preferably, when the basic dot matrix is a one-dimensional array, the first sub-array is formed by odd number of basic dots in the row direction or the column direction, and the second sub-array is formed by even number of basic dots in the row direction or the column direction; preferably, when the base dot matrix array is a two-dimensional array, the row coordinate of the base dot in the first sub-array is odd and the column coordinate is odd, the row coordinate of the base dot in the second sub-array is even and the column coordinate is odd, the row coordinate of the base dot in the third sub-array is odd and the column coordinate is even, and the row coordinate of the base dot in the fourth sub-array is even and the column coordinate is even, wherein the row coordinate of the base dot in each sub-array is the corresponding row number of the base dot in the base dot array, and the row coordinate of the base dot in each sub-array is the corresponding column number of the base dot in the base dot array; preferably, the processing unit calculates an interpolation point value by linear weight based on a base point value corresponding to the coordinates of the plurality of boundary points; preferably, the first selector and/or the second selector may be, for example, a one-out-of-two selector. The digital processing circuit 300 of the present invention performs an interpolation operation including the steps of:
step S10: a plurality of sub-arrays are extracted from the base point array. The base dot array stored in the storage unit 301 may be classified and extracted to obtain a plurality of sub-arrays, the base dots between each sub-array may be overlapped or not overlapped, and when the base dots between each sub-array are not overlapped, it is preferable that each sub-array is, for example, classified by arranging and combining the base dot array at odd/even cross points in each dimension, and specifically, when the base dot array is a one-dimensional array, a first sub-array is composed of odd base dots in the row direction or the column direction, and a second sub-array is composed of even base dots in the row direction or the column direction; when the basic dot matrix array is a two-dimensional array, the row coordinate of the basic dot in the first sub-array is an odd number and the column coordinate is an odd number, the row coordinate of the basic dot in the second sub-array is an even number and the column coordinate is an odd number, the row coordinate of the basic dot in the third sub-array is an odd number and the column coordinate is an even number, the row coordinate of the basic dot in the fourth sub-array is an even number and the column coordinate is an even number, wherein the row coordinate of the basic dot in each sub-array is the corresponding row number of the basic dot in the basic dot array, and the row coordinate of the basic dot in each sub-array is the corresponding column number of the basic dot in the basic dot array. . The sub-array may only represent classification of the base points of the base point array or may represent division of the base point array into a plurality of sub-arrays, only for conveniently obtaining each boundary point of the insertion point. In the following embodiments, the sub-array may merely indicate that the base dots of the base dot array are classified, and the plurality of sub-arrays are still stored in the storage unit as one complete base dot array, instead of dividing the base dot array into a plurality of sub-arrays to be stored in different storage media, respectively.
Step S20: at least one associated point coordinate adjacent to the insertion point is selected in each sub-array. A first selector 302 is used to select a number of correlation points within each sub-array adjacent to the insertion point coordinates, the number of correlation points selected in each sub-array being no greater than 2 n . Preferably, when a plurality of sub-arrays are obtained by arranging and combining the base dot array at odd/even cross points in each dimension, the number of sub-arrays is 2 n At least one correlation point closest to the insertion point may be selected within each sub-array, for example, based on the insertion point coordinates.
Step S30: and determining a plurality of boundary point coordinates of the target interval where the insertion point is located in the basic point array according to each relevant point coordinate. The second selector 303 is configured to determine a plurality of boundary point coordinates of the target interval where the insertion point is located in the base point array according to each of the relevant point coordinates, where the boundary point of the insertion point is used to define the insertion point in the base point arrayWherein the number of boundary points is 2 n . When each sub-array can be obtained by correspondingly classifying according to the odd/even intersection point arrangement combination of each dimension, the number of the selected relevant points can be at least equal to the number of the boundary points.
Step S40: and determining an insertion point value corresponding to the insertion point based on the base point value corresponding to the coordinates of the boundary points. The processing unit 304 reads the base point value corresponding to each boundary point to determine the insertion point value corresponding to the insertion point based on the coordinates of the boundary points obtained by the second selectors 303, and preferably, the insertion point value may be obtained by linear weight calculation, for example.
In summary, the digital processing circuit of the present invention includes a plurality of first selectors for selecting a plurality of related points, and a plurality of second selectors for selecting a plurality of boundary points. The input to the first selector is the base point coordinates in each sub-array. The second selector is used to define the location of the insertion point on the basis of the first selector.
In addition, the invention selects the relevant points of the insertion points through the first selector, selects the boundary points of the insertion points from the relevant points through the second selector, realizes the limitation of the positions of the insertion points in the basic point array in a mode of cascading two types of selectors, further determines the insertion point values, reduces the use of the selectors and the connection of circuits, simultaneously reduces the power consumption of hardware circuits for realizing the multi-dimensional interpolation method, and improves the overall stability of the circuits.
The digital processing circuit proposed by the present invention will be described below by way of specific embodiments. In the following embodiments, the sub-arrays are obtained by correspondingly classifying the values at the odd/even intersection points of each dimension, and a correlation point closest to the insertion point is selected in each sub-array by the first selector, and the obtained correlation point defines the position of the insertion point in the base point array by the second selector. The following examples are described on the basis of the above-described limitations, however, it is clear from the description in the figures that the practice of the invention is not limited thereto.
Fig. 4 shows a schematic diagram of the interpolation operation performed by the digital processing circuit according to the first embodiment of the present invention.
As shown in fig. 4, a schematic diagram of a digital processing circuit implementing a one-dimensional linear interpolation operation is shown. Wherein the base point array 100 includes 17 base points P1-P17. The base point array 100 is divided into a first sub-array 110 and a second sub-array 120 according to one-dimensional odd/even intersections, the first sub-array 110 is formed by odd base points in the row direction, and the second sub-array 120 is formed by even base points in the row direction. By selecting a correlation point P13 adjacent to the insertion point 101 from the first sub-array 110 and selecting a correlation point P14 adjacent to the insertion point 101 from the second sub-array 120 by the first selector, only 8 first selectors are required to select a correlation point from 9 basis points in the first basis array 110, and only 7 first selectors are required to select a correlation point from 8 basis points in the second basis array 120. The left and right boundary points are selected from the relevant points P13, P14 by the second selectors, respectively, and thus two second selectors are required. It should be noted that the first selector and the second selector are only used for better understanding of the present invention, wherein the first selector and the second selector may be, for example, two or more selectors of the same type or different types.
In summary, in the first embodiment, 17 selectors are required, and when the boundary points of the insertion points are selected in one step according to the prior art, the base point array requires 30 ((17-1-1) x2= 30) alternative selectors, and when the number of interpolation nodes in the base point array (the number of base points in the one-dimensional base point array is minus 1) N is large enough, the digital processing circuit of the present invention can reduce N/2 selectors, where N is a natural number greater than 1.
Fig. 5 shows a schematic diagram of a digital processing circuit for interpolation operation according to a second embodiment of the present invention.
As shown in fig. 5, a schematic diagram of a digital processing circuit implementing a two-dimensional linear interpolation operation is shown. Wherein the base point array 200 includes 17x17 base points. The base point array 200 is divided into a first sub-array 210, a second sub-array 220, a third sub-array 230 and a fourth sub-array 240 according to the intersection points of the horizontal odd/even number and the vertical odd/even number, the row coordinates of the base points in the first sub-array 210 are odd numbers and the column coordinates are odd numbers, the row coordinates of the base points in the second sub-array 220 are even numbers and the column coordinates are odd numbers, the row coordinates of the base points in the third sub-array 230 are odd numbers and the column coordinates are even numbers, and the row coordinates of the base points in the fourth sub-array 240 are even numbers and the column coordinates are even numbers. A correlation point 211 adjacent to the insertion point 201 is selected from the first subarray 210, a correlation point 221 adjacent to the insertion point 201 is selected from the second subarray 220, a correlation point 231 adjacent to the insertion point 201 is selected from the third subarray 230, and a correlation point 241 adjacent to the insertion point 201 is selected from the fourth subarray 240 by the first selector. One correlation point is selected from 9 × 9 basis points in the first basis array 210, so that only 80 first selectors are required, one correlation point is selected from 8 × 9 basis points in the second basis array 220, so that only 71 first selectors are required, one correlation point is selected from 9 × 8 basis points in the third basis array 230, so that only 71 first selectors are required, and one correlation point is selected from 8 × 8 basis points in the fourth basis array 240, so that only 63 first selectors are required. The upper left boundary point, the lower left boundary point, the upper right boundary point and the lower right boundary point are respectively selected from the correlation point 211, the correlation point 221, the correlation point 231 and the correlation point 241 by the second selector, so that 3 × 4 second selectors are required. It should be noted that the first selector and the second selector are only used for better understanding of the present invention, wherein the first selector and the second selector may be, for example, two or more selectors of the same type or different types.
In summary, in the second embodiment, 297 selectors are required, and when the boundary point of the insertion point is selected in one step in the prior art, the base point array requires 1020 (((17-1) x (17-1) -1) x 4= 1020) alternative selectors, when the number of interpolation nodes in the base point array (the number of base points in the one-dimensional base point array is minus 1) N is large enough, the digital processing circuit of the present invention can reduce (NxN- (N/2) x (N/2)) selectors, where N is a natural number greater than 1.
When the dimension n is greater than 2, the invention providesThe digital processing circuit, when the number of interpolation nodes in the basic point array (the number of basic points in the one-dimensional basic point array is reduced by 1) is large enough, the interpolation device of the present invention can reduce (N) n –(N/2) n ) A selector, wherein N is a natural number greater than 1.
The digital processing circuit can solve the problem that the change value in the area is obtained through the existing basic point array, not only saves the space of a memory for storing the basic point array, but also can reduce the number of selectors by executing interpolation operation through the digital processing circuit, thereby reducing the power consumption of a hardware circuit and improving the stability of the hardware circuit.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.
Claims (9)
1. A digital processing circuit, comprising:
the storage unit is used for storing a basic point array, and extracting a plurality of sub-arrays from the basic point array, wherein each basic point in the basic point array has corresponding basic point coordinates and basic point values;
a plurality of first selectors for selecting coordinates of at least one relevant point adjacent to an insertion point in each of the sub-arrays;
a plurality of second selectors used for selecting the coordinates of a plurality of boundary points of the target interval where the insertion point is located in the base point array according to the coordinates of each related point; and
a processing unit determining an insertion point value corresponding to the insertion point based on a base point value corresponding to coordinates of the plurality of boundary points,
wherein the number of basis points in at least one of said sub-arrays is less than the number of basis points in said array of basis points.
2. The digital processing circuit of claim 1, wherein base points between a plurality of said sub-arrays do not overlap.
3. The digital processing circuit of claim 1, wherein the target interval of the insertion point has 2 when the base lattice column is an n-dimensional array n N is a positive integer.
4. The digital processing circuit of claim 3, wherein the number of subarrays is equal to the number of boundary points used to determine the target interval.
5. The digital processing circuit of claim 4, wherein the plurality of first selectors are configured to select at least one of the associated point coordinates in each of the sub-arrays.
6. The digital processing circuit of claim 5, wherein when said base lattice is a one-dimensional array,
the first sub-array is constituted by an odd number of base points in the row direction or the column direction,
the second sub-array is constituted by an even number of base dots in the row direction or the column direction.
7. The digital processing circuit of claim 5, wherein when the base lattice is a two-dimensional array,
the base points in the first sub-array have odd row coordinates and odd column coordinates,
the base points in the second sub-array have even row coordinates and odd column coordinates,
the base points in the third sub-array have odd row coordinates and even column coordinates,
the base points in the fourth sub-array have even row coordinates and even column coordinates,
the row coordinate of the base point in each sub-array is the corresponding row number of the base point in the base point array, and the row coordinate of the base point in each sub-array is the corresponding column number of the base point in the base point array.
8. The digital processing circuit according to claim 1, wherein the processing unit obtains the interpolation point value by linear weight calculation based on a base point value corresponding to coordinates of the plurality of boundary points.
9. The digital processing circuit of claim 1, wherein the first selector and/or the second selector is an alternative selector.
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| US6157937A (en) * | 1997-07-17 | 2000-12-05 | Nec Corporation | High speed interpolation circuit with small circuit scale |
| CN101500168A (en) * | 2009-02-18 | 2009-08-05 | 北京中星微电子有限公司 | 1/3 interpolation apparatus for image brightness |
| CN101778280A (en) * | 2010-01-14 | 2010-07-14 | 山东大学 | Circuit and method based on AVS motion compensation interpolation |
| JP2016163070A (en) * | 2015-02-26 | 2016-09-05 | キヤノン株式会社 | Data converter and control method and program thereof |
| CN106096263A (en) * | 2016-06-07 | 2016-11-09 | 深圳市国微电子有限公司 | A kind of multidimensional linear polation method and apparatus |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| GB2529644B (en) * | 2014-08-27 | 2016-07-13 | Imagination Tech Ltd | Efficient interpolation |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6157937A (en) * | 1997-07-17 | 2000-12-05 | Nec Corporation | High speed interpolation circuit with small circuit scale |
| CN101500168A (en) * | 2009-02-18 | 2009-08-05 | 北京中星微电子有限公司 | 1/3 interpolation apparatus for image brightness |
| CN101778280A (en) * | 2010-01-14 | 2010-07-14 | 山东大学 | Circuit and method based on AVS motion compensation interpolation |
| JP2016163070A (en) * | 2015-02-26 | 2016-09-05 | キヤノン株式会社 | Data converter and control method and program thereof |
| CN106096263A (en) * | 2016-06-07 | 2016-11-09 | 深圳市国微电子有限公司 | A kind of multidimensional linear polation method and apparatus |
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