CN101770737A - Image display system and display panel - Google Patents
Image display system and display panel Download PDFInfo
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- CN101770737A CN101770737A CN200910001704A CN200910001704A CN101770737A CN 101770737 A CN101770737 A CN 101770737A CN 200910001704 A CN200910001704 A CN 200910001704A CN 200910001704 A CN200910001704 A CN 200910001704A CN 101770737 A CN101770737 A CN 101770737A
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Abstract
The invention relates to an image display system and a display panel. The display panel comprises a gate line circuit, a control circuit and a gate line. The gate line circuit comprises a gate driver; an output end of the gate driver can generate a first driving signal which is a high level and low level alternating signal and has a first rising edge and a first falling edge. An input end of the control circuit is connected with the output end of the gate driver and is used for receiving the first driving signal, and an output end of the control circuit generates a second driving signal which has a second rising edge and a second falling edge. The gate line is connected to the output end of the control circuit, wherein the control circuit at least comprises a capacitor which is charged in a first direction on the first rising edge of the first driving signal and charged in a second direction on the first falling edge of the first driving signal. Through the image display system and the display panel, the problem that the brightness or image presented by the display panel is not uniform can be solved.
Description
Technical field
The present invention relates to the circuit on a kind of display system and the display panel, relate in particular to a kind of image display system and display panel and gate line circuit thereof.
Background technology
Please refer to Fig. 1, it is shown to be the known display panel synoptic diagram.Display panel comprises a plurality of pixel components 101～126 that array is arranged, and all comprises a storage element c101～c126 and a switch element m101～m126 in each pixel components 101～126.Wherein, switch element m101～m126 is a transistor, and storage element c101～c126 then is a capacitor.Moreover, include many gate lines (gate line) g1～g3 and many data lines (data line) d1～d6 on the display panel.Via grid-control system unit (gatecontrol unit) control switch unit m101～m126, the pixel data on data line d1～d6 can be stored in storage element c101～c126 smoothly.Certainly, along with the size of display panel becomes big, pixel components, gate line, with data line also can be many more.
In general, above-mentioned display panel can be applicable to an active array formula Organic Light Emitting Diode (active matrix organic light emitting diode, be called for short AMOLED) display or a LCD (liquid crystal display is called for short LCD).
Please refer to Fig. 2 A, it is shown to be known gate line circuit diagram.The gate line circuit comprises a gate drivers (gate driver) 230, one gate line 240 and n pixel components 211～21n.By Fig. 2 A as can be known, n switch element m211～n pixel components 211～21n of m21n may command.Moreover the output terminal of gate drivers 230 is connected to gate line 240, and gate line 240 is connected to the grid of n switch element m211～m21n (transistor).For the unlatching (on) that will control each switch element m211～m21n with close (off), gate drivers 230 can produce the drive signal (driving signal) that high level and low level replace on gate line 240.When drive signal was high level, n switch element m211～m21n opened; Otherwise when drive signal was low level, n switch element m211～m21n closed.Wherein, comprise a plurality of gate drivers in the grid-control system unit, and embodiments of the invention lay down a definition with a gate drivers all.
Please refer to Fig. 2 B, it is shown to be the equivalent electrical circuit of known gate line circuit.By Fig. 2 B as can be known, each switch element m211～m21n can equivalence be capacitor c1～cn all, and gate line can equivalence be a plurality of resistance r1～rn serial connection.Since the drive signal high level with low level replace very quick, therefore, precipitous (sharp) that the drive signal rising edge gradient on gate drivers 230 output terminals and the negative edge gradient can be very.Yet because drive signal must be passed to last (n) switch element cn, therefore, when drive signal was passed to last switch element cn, its rising edge gradient and the negative edge gradient can become not precipitous.
Please refer to Fig. 2 C, it is shown to be curve I and curve II.Wherein, curve I is the grid voltage synoptic diagram on first switch element c1 grid; And curve II is the grid voltage synoptic diagram on last switch element cn grid.Clearly, after drive signal was converted to the time of low level Δ t1 by high level, by curve I as can be known, the grid voltage of the first switch element c1 can be considered fully closed; And by curve II as can be known, the grid voltage of last switch element cn too Gao Ershang is not closed fully.That is to say that when time of Δ t1, first pixel components is closed fully, and last pixel components is not closed fully as yet.Therefore, can cause display panel inhomogeneous because of brightness or image that different feed-trough voltage effects (feed-throughvoltage effect) are presented.
In order to improve above-mentioned shortcoming, the designer of display panel can be in the online serial connection one big resistance R of grid.Please refer to Fig. 3 A, it is shown to be the equivalent electrical circuit of known gate line circuit.By Fig. 3 A as can be known, be connected in series a big resistance R, and drive signal must be passed to the first switch element c1 through after this big resistance R earlier between gate drivers 230 output terminals and the first switch element c1.Because what the online serial connection one big resistance R of grid can increase by the first switch element c1 discharges and recharges time constant (time constant), therefore, can slow down rising edge and the negative edge of drive signal on the first switch element c1 grid voltage.
Please refer to Fig. 3 B, it is shown to be curve III and curve IV.Wherein, curve III is the grid voltage synoptic diagram on first switch element c1 grid; And curve IV is the grid voltage synoptic diagram on last switch element cn grid.By curve III as can be known, after drive signal was converted to the time of low level Δ t2 by high level, the grid voltage on the first switch element c1 can be considered closed fully; By curve IV as can be known, last switch element cn is also near closing fully, that is the first switch element c1 almost can close to last switch element cn simultaneously fully.That is to say that when time of Δ t2, first pixel components and last pixel components are almost closed simultaneously.Therefore, can solve brightness or the uneven problem of image that display panel presents.
In like manner, please refer to Fig. 4, it is shown to be the equivalent electrical circuit of known another kind of gate line circuit.As shown in Figure 4, in a large capacitor C in parallel between gate drivers output terminal and the earth terminal, and drive signal must be earlier through being passed to the first switch element c1 behind this large capacitor C.Because grid discharges and recharges time constant (time constant) what line parallel one large capacitor C can increase by the first switch element c1, therefore, also can slow down rising edge and the negative edge of drive signal on the first switch element c1 grid.
Yet, can occupy the layout area in big zone on the display panel in design one large capacitor C on the display panel; Moreover, except increasing regional greatly layout area, meeting also can increase the consumed power of display panel in design one big resistance R on the display panel.
Summary of the invention
The objective of the invention is to propose the gate line circuit on a kind of display panel, utilize the control circuit drive signal that the gradient is precipitous of small size to be converted into the mild drive signal of the gradient.
The present invention proposes a kind of display panel, comprise: a gate line circuit, comprise: a gate drivers, the output terminal of this gate drivers can produce one first drive signal, this first drive signal is a high level and a low level alternating signals, and has one first rising edge and one first negative edge; One control circuit, the input end of this control circuit is connected to the output terminal of this gate drivers in order to receive this first drive signal, and produce one second drive signal in the output terminal of this control circuit, this second drive signal has one second rising edge and one second negative edge, the gradient of this second rising edge is mild than the gradient of this first rising edge, and the gradient of this second negative edge is mild than the gradient of this first negative edge; And a gate line is connected in the output terminal of this control circuit; Wherein, this control circuit comprises a capacitor at least, can be when this first rising edge of this first drive signal with a first direction this capacitor that charges; And can be when this first negative edge of this first drive signal with a second direction this capacitor that charges.
Moreover the present invention also proposes a kind of image display system, comprising: the display panel that the preceding paragraph falls; And a power supply unit is coupled to this display panel and provides power supply to this display panel.
The present invention can solve brightness or the uneven problem of image that display panel presents.
Description of drawings
Shown in Figure 1ly go out to be the known display panel synoptic diagram.
Fig. 2 A is shown to be known gate line circuit diagram.
Fig. 2 B is shown to be the equivalent electrical circuit of known gate line circuit.
Fig. 2 C is shown to be grid voltage synoptic diagram on first switch element and last the switch element grid.
Fig. 3 A is shown to be the equivalent electrical circuit of known gate line circuit.
Fig. 3 B is shown to be grid voltage synoptic diagram on first switch element and last the switch element grid.
The equivalent electrical circuit that goes out for known another kind of gate line circuit shown in Figure 4.
Fig. 5 A is shown to be first embodiment of control circuit of the present invention.
Fig. 5 B is shown to be the schematic equivalent circuit of the first embodiment control circuit.
Fig. 5 C is shown to be the equivalent electrical circuit of the gate line circuit of first embodiment of the invention.
Fig. 6 A is shown to be second embodiment of control circuit of the present invention.
Fig. 6 B is shown to be the schematic equivalent circuit of the second embodiment control circuit.
Fig. 6 C is shown to be the equivalent electrical circuit of the gate line circuit of second embodiment of the invention.
Shown in Figure 7ly go out to be display panel of the present invention.
Shown in Figure 8ly go out to be image display system of the present invention.
And the description of reference numerals in the above-mentioned accompanying drawing is as follows:
101～126 pixel components c101～c126 storage element
M101～m126 switch element 211～21n pixel components
M211～m21n switch element
230 gate drivers, 240 gate lines
300,400 control circuits, 310 first phase inverters
320 transmission gates, 322 resistance
330 second phase inverters, 340 capacitors
410 first phase inverters, 420 second phase inverters
430 the 3rd phase inverters, 440 resistance
450 capacitors
701～726 pixel components c701～c726 storage element
M701～m726 switch element 750 DCU data control unit
760 grid-control system unit, 761 first grid drivers
762 first control circuits, 763 second grid drivers
764 second control circuits 765 the 3rd gate drivers
766 the 3rd control circuits, 800 image display systems
810 power supply units, 820 display panels
Embodiment
The present invention proposes a gate line circuit, comprises that a control circuit is connected between gate drivers output terminal and first switch element.In order to the rising edge that slows down drive signal and the gradient of negative edge, and control circuit of the present invention all can utilize transistor to realize, so layout area can reduce effectively.
Please refer to Fig. 5 A, it is shown to be first embodiment of control circuit of the present invention.Control circuit 300 comprises one the one P transistor npn npn P1, one the one N transistor npn npn N1, one the 2nd P transistor npn npn P2, one the 2nd N transistor npn npn N2, one the 3rd P transistor npn npn P3, one the 3rd N transistor npn npn N3 and one the 4th transistor M4.Wherein, a P transistor npn npn P1 and a N transistor npn npn N1 are connected to form one first phase inverter (inverter) 310; The 2nd P transistor npn npn P2 and the 2nd N transistor npn npn N2 are connected to form a transmission gate (transmission gate) 320; The 3rd P transistor npn npn P3 and one the 3rd N transistor npn npn N3 are connected to form one second phase inverter 330; And the source electrode of the 4th transistor M4 and drain electrode are interconnected to form a capacitor 340, and the grid of the 4th transistor M4 can be considered first end of capacitor, and the drain electrode of the 4th transistor M4 can be considered second end of capacitor.Moreover the input end of control circuit 300 is the input end of first phase inverter 310, and the output terminal of control circuit 300 is the output terminal of second phase inverter 330.
The grid of the one a P transistor npn npn P1 and a N transistor npn npn N1 interconnects the input end that becomes first phase inverter 310; The source electrode of the one P transistor npn npn P1 is connected to a voltage source Vcc; The drain electrode of the one a P transistor npn npn P1 and a N transistor npn npn N1 interconnects and becomes the output terminal of first phase inverter 310; The source electrode of the one N transistor npn npn N1 is connected to earth terminal.
The grid of the 2nd P transistor npn npn P2 and the 2nd N transistor npn npn N2 is connected to earth terminal and voltage source respectively; The source electrode of the 2nd P transistor npn npn P2 and the 2nd N transistor npn npn N2 interconnects the input end that becomes transmission gate 320; The drain electrode of the 2nd P transistor npn npn P2 and the 2nd N transistor npn npn N2 interconnects the output terminal that becomes transmission gate 320.
The grid of the 3rd P transistor npn npn P3 and the 3rd N transistor npn npn N3 interconnects the input end that becomes second phase inverter 330; The source electrode of the 3rd P transistor npn npn P3 is connected to a voltage source Vcc; The drain electrode of the 3rd P transistor npn npn P3 and the 3rd N transistor npn npn N3 interconnects and becomes the output terminal of second phase inverter 330; The 3rd N transistor npn npn N3 source electrode is connected to earth terminal.
Please refer to Fig. 5 B, it is shown to be the schematic equivalent circuit of the first embodiment control circuit.Because the 2nd P transistor npn npn P2 and the 2nd N transistor npn npn N2 grid are connected to earth terminal and voltage source Vcc respectively in the transmission gate 320, therefore, transmission gate 320 can be considered opening and can equivalence be a resistance 322, and the input end of transmission gate 320 and output terminal are two ends of resistance 322.By Fig. 5 B as can be known, be connected in series a resistance 322 between first phase inverter, 310 output terminals and second phase inverter, 330 input ends, and a capacitor 340 in parallel between the input end of second phase inverter 330 and the output terminal.
Please refer to Fig. 5 C, it is shown to be the equivalent electrical circuit of the gate line circuit of first embodiment of the invention.When the drive signal of gate drivers 230 generations rises to high level apace by low level, second phase inverter 330 can be exported high level, yet because capacitor 340 is parallel between the input end and output terminal of second phase inverter 330, therefore, second phase inverter 330 can't rise to high level apace.At this moment, second phase inverter, 330 output terminals can produce one first charging current I1 by capacitor 340 through resistance 322 to first phase inverters 310 output terminals, therefore, the voltage on the capacitor 340 can rise to high level lentamente.At this moment, can be considered capacitor 340 by the high level that charges to of first direction.
That is when capacitor 340 was charged by first direction, second phase inverter, 330 output terminals can rise to high level lentamente.Therefore, control circuit 300 can the drive signal that the gradient is precipitous be converted into milder drive signal.Therefore, can make the switch element c1 that wins to last switch element cn complete opening simultaneously almost.
Otherwise, when drive signal drops to low level apace by high level, second phase inverter meeting output low level, yet because capacitor 340 is parallel between the input end and output terminal of second phase inverter, and stored the voltage of a high level on the capacitor 340, therefore, second phase inverter, 330 output terminals can't drop to low level apace.
For second phase inverter, 330 output terminals being dropped to low level, first phase inverter, 310 output terminals can produce one second charging current I2 by resistance 322 through capacitor 340 to second phase inverters 330 output terminals, at this moment, the high level voltage discharge that capacitor 340 can will originally store, and utilize the second charging current I2 oppositely to charge to high level voltage.At this moment, can be considered capacitor 340 by the high level that charges to of second direction.
That is when capacitor 340 was charged by second direction, second phase inverter, 330 output terminals can drop to low level lentamente.That is to say that control circuit can the drive signal that the gradient is precipitous be converted into the milder drive signal of the gradient.Therefore, the switch element c1 that wins almost can be closed simultaneously fully to last switch element cn.
Since the capacitor 340 in the control circuit 300 of the present invention can be two-way charging, therefore, the layout area of capacitor 340 can reduce and reach the purpose of mild drive signal effectively.
Moreover, please refer to Fig. 6 A and B, it is shown to be second embodiment and the schematic equivalent circuit thereof of control circuit of the present invention.Wherein, control circuit 400 comprises one first phase inverter 410, one second phase inverter 420, one the 3rd phase inverter 430, a resistance 440, a capacitor 450.
Moreover the input end of control circuit 400 is the input end of first phase inverter 410, and the output terminal of control circuit 400 is the output terminal of second phase inverter 420.First phase inverter, 410 output terminals are connected to second phase inverter, 420 input ends; Second phase inverter, 420 output terminals are connected to the 3rd phase inverter 430 input ends; And be connected in series capacitor 450 and resistance 440 between the 3rd phase inverter 430 input ends and the output terminal.
Wherein, first phase inverter 410, second phase inverter 420, the 3rd phase inverter 430, capacitor 450 all can be made up of the transistor shown in first embodiment, and all certainly phase inverters also can be made up of all N-type transistor or full P transistor npn npn.
Moreover resistance 440 is to be connected to form a transmission gate (transmission gate) by the 4th P transistor npn npn P4 and the 4th N transistor npn npn N4; The grid of the 4th P transistor npn npn P4 and the 4th N transistor npn npn N4 is connected to earth terminal and voltage source respectively; The source electrode of the 4th P transistor npn npn P4 and the 4th N transistor npn npn N4 interconnects the input end that becomes transmission gate; The drain electrode of the 4th P transistor npn npn P4 and the 4th N transistor npn npn N4 interconnects the output terminal that becomes transmission gate.And two ends of resistance 440 are the output terminal and the input end of transmission gate.
Please refer to Fig. 6 C, it is shown to be the equivalent electrical circuit of the gate line circuit of second embodiment of the invention.When the drive signal of gate drivers 230 generations rises to high level apace by low level, second phase inverter 420 of control circuit 400 can be exported high level, yet because the capacitor 450 and the resistance 440 of serial connection are connected between the input end and output terminal of the 3rd phase inverter 430, therefore, second phase inverter 420 can't rise to high level apace.At this moment, second phase inverter, 420 output terminals can produce one the 3rd charging current I3 by capacitor 450 through resistance 440 to the 3rd phase inverters 430 output terminals, therefore, the voltage on the capacitor 450 can rise to high level lentamente.At this moment, can be considered capacitor 450 by the high level that charges to of first direction.
That is when capacitor 450 was charged by first direction, second phase inverter, 420 output terminals can rise to high level lentamente.Therefore, control circuit 400 can the drive signal that the gradient is precipitous be converted into the milder drive signal of the gradient.Therefore, can make the switch element c1 that wins to last switch element cn complete opening simultaneously almost.
Otherwise, when drive signal drops to low level apace by high level, second phase inverter, 420 meeting output low levels, yet because between the input end and output terminal that the resistance of serial connection and capacitor are connected in the 3rd phase inverter, and stored the voltage of a high level on the capacitor 450, therefore, second phase inverter, 420 output terminals can't drop to low level apace.
For second phase inverter, 420 output terminals being dropped to low level, the 3rd phase inverter 430 output terminals can produce one the 4th charging current I4 by resistance 440 through capacitor 450 to second phase inverters 420 output terminals, at this moment, the high level voltage discharge that capacitor 450 can will originally store, and utilize the 4th charging current I4 oppositely to charge to high level voltage.At this moment, can be considered capacitor 450 by the high level that charges to of second direction.
That is when capacitor 450 was charged by second direction, second phase inverter, 420 output terminals can drop to low level lentamente.That is to say that control circuit can the drive signal that the gradient is precipitous be converted into the milder drive signal of the gradient.Therefore, the switch element c1 that wins almost can be closed simultaneously fully to last switch element cn.
Since the capacitor 450 in the control circuit 400 of the present invention can be two-way discharge and recharge, therefore, capacitance does not need too big, so the layout area of capacitor 450 can reduce and reach the purpose of the mild drive signal rising/negative edge gradient effectively.
When control circuit is passed to all switch element c1～cn with mild drive signal, the first switch element c1 to last switch element cn almost simultaneously complete opening with close.Therefore, first pixel components has identical feed-trough voltage effect with last pixel components.Therefore, can solve brightness or the uneven problem of image that display panel presents.
Please refer to Fig. 7, it is shown to be display panel synoptic diagram of the present invention.Display panel comprises a plurality of pixel components 701～726 that array is arranged, and all comprises a storage element c701～c726 and a switch element m701～m726 in each pixel components 701～726.Wherein, switch element m701～m726 is a transistor, and storage element c701～c726 then is a capacitor.
Include a DCU data control unit 750 and a grid-control system unit 760 on the display panel.Grid-control system unit 760 has many gate line g1～g3, and DCU data control unit 750 has many data line d1～d6.Via grid-control system unit controls switch element m701～m726, the pixel data on data line d1～d6 can be stored in storage element c701～c726 smoothly.Certainly, along with the size of display panel becomes big, pixel components, gate line, with data line also can be many more.Moreover, grid-control system of the present invention unit 760 also comprises a plurality of gate drivers and a plurality of control circuit, for example first grid driver 761 and first control circuit 762, second grid driver 763 and second control circuit 764, and the 3rd gate drivers 765 and the 3rd control circuit 766, and the output terminal of control circuit promptly is connected to corresponding gate line g1～g3.
Moreover, please refer to Fig. 8, it is shown to be image display system of the present invention.Image display system 800 comprises a display panel 820 and a power supply unit 810.Wherein, power supply unit 810 can provide display panel 820 required power supply, and display panel 820 display panel illustrated in fig. 7 as described above, it comprises above-mentioned grid circuit, makes image display system 800 can solve brightness or the uneven problem of image that display panel presents.
Moreover image display system 800 can be any during mobile phone, digital camera, personal digital assistant, mobile computer, desk-top computer, TV, GPS (GPS), automobile-used display, aviation are installed with display, digital frame (Digital Photo Frame) or portable DVD player projector etc.
In sum; though the present invention with the preferred embodiment explanation as above; right its is not in order to limit the present invention; any those of ordinary skills; do not breaking away within the spirit and scope of the present invention; when doing various changes and retouching, therefore, protection scope of the present invention is as the criterion when looking appended the scope that claim defined.
Claims (10)
1. display panel comprises:
One gate line circuit comprises:
One gate drivers, the output terminal of this gate drivers can produce one first drive signal, and this first drive signal is a high level and a low level alternating signals, and have one first rising edge and one first negative edge;
One control circuit, the input end of this control circuit is connected to the output terminal of this gate drivers in order to receive this first drive signal, and produce one second drive signal in the output terminal of this control circuit, this second drive signal has one second rising edge and one second negative edge, the gradient of this second rising edge is mild than the gradient of this first rising edge, and the gradient of this second negative edge is mild than the gradient of this first negative edge; And
One gate line is connected in the output terminal of this control circuit;
Wherein, this control circuit comprises a capacitor at least, can be when this first rising edge of this first drive signal with a first direction this capacitor that charges; And can be when this first negative edge of this first drive signal with a second direction this capacitor that charges.
2. display panel as claimed in claim 1 also comprises a plurality of switch elements, is connected in this gate line and can comes the described a plurality of switch elements of open and close according to this second drive signal; Wherein, described a plurality of switch elements are positioned at a plurality of pixel components on this display panel, and a plurality of storage elements in the described a plurality of pixel components of may command receive corresponding a plurality of pixel data.
3. display panel as claimed in claim 1, wherein this control circuit also comprises:
One first phase inverter, the input end of this first phase inverter are the input end of this control circuit;
One resistance; And
One second phase inverter, the input end of this second phase inverter is connected this resistance with the output terminal of this first phase inverter, be connected this capacitor between the output terminal of the input end of this second phase inverter and this second phase inverter, and the output terminal of this second phase inverter is the output terminal of this control circuit.
4. display panel as claimed in claim 3, wherein this first phase inverter comprises:
One the one P transistor npn npn, the source electrode of a P transistor npn npn is connected to a voltage source; And
One the one N transistor npn npn, the one a P transistor npn npn and a N transistor npn npn grid interconnect the input end that becomes this first phase inverter, the drain electrode of the one a P transistor npn npn and a N transistor npn npn interconnects and becomes the output terminal of this first phase inverter, and the source electrode of a N transistor npn npn is connected to an earth terminal.
5. display panel as claimed in claim 3, wherein this resistance comprises:
One the 2nd P transistor npn npn, the grid of the 2nd P transistor npn npn is connected to an earth terminal; And
One the 2nd N transistor npn npn, the grid of the 2nd N transistor npn npn is connected to a voltage source, the source electrode of the 2nd P transistor npn npn and the 2nd N transistor npn npn interconnects first end that becomes this resistance, and the drain electrode of the 2nd P transistor npn npn and the 2nd N transistor npn npn interconnects second end that becomes this resistance.
6. display panel as claimed in claim 1, wherein this capacitor is made up of one the 4th transistor, and the 4th transistorized grid is first end of this capacitor, and the 4th transistor drain and source electrode interconnect and become second end of this capacitor.
7. display panel as claimed in claim 1, wherein this control circuit also comprises:
One first phase inverter, the input end of this first phase inverter are the input end of this control circuit;
One second phase inverter, the input end of this second phase inverter is connected to the output terminal of this first phase inverter, and the output terminal of this second phase inverter is the output terminal of this control circuit;
One resistance; And
One the 3rd phase inverter, the input end of the 3rd phase inverter is connected to the output terminal of this second phase inverter, and is connected this resistance and this capacitor of polyphone between the output terminal of the input end of the 3rd phase inverter and the 3rd phase inverter.
8. display panel as claimed in claim 7, wherein this first phase inverter comprises:
One the one P transistor npn npn, the source electrode of a P transistor npn npn is connected to a voltage source; And
One the one N transistor npn npn, the one a P transistor npn npn and a N transistor npn npn grid interconnect the input end that becomes this first phase inverter, the drain electrode of the one a P transistor npn npn and a N transistor npn npn interconnects and becomes the output terminal of this first phase inverter, and the source electrode of a N transistor npn npn is connected to an earth terminal.
9. display panel as claimed in claim 7, wherein, this resistance comprises:
One the 2nd P transistor npn npn, the grid of the 2nd P transistor npn npn is connected to an earth terminal; And
One the 2nd N transistor npn npn, the grid of the 2nd N transistor npn npn is connected to a voltage source, the source electrode of the 2nd P transistor npn npn and the 2nd N transistor npn npn interconnects first end that becomes this resistance, and the drain electrode of the 2nd P transistor npn npn and the 2nd N transistor npn npn interconnects second end that becomes this resistance; And
The 3rd phase inverter comprises:
One the 3rd P transistor npn npn, the source electrode of the 3rd P transistor npn npn is connected to a voltage source; And
One the 3rd N transistor npn npn, the 3rd P transistor npn npn and the 3rd N transistor npn npn grid interconnect the input end that becomes the 3rd phase inverter, the drain electrode of the 3rd P transistor npn npn and the 3rd N transistor npn npn interconnects and becomes the output terminal of the 3rd phase inverter, and the source electrode of the 3rd N transistor npn npn is connected to an earth terminal.
10. image display system comprises:
Display panel as claimed in claim 1; And
One power supply unit is coupled to this display panel and provides power supply to this display panel; Wherein, this image display system is a mobile phone, a digital camera, a personal digital assistant, a mobile computer, a desk-top computer, a TV, a GPS, an automobile-used display, an aviation display, a digital frame or a portable DVD player projector.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1322169A (en) * | 1999-10-22 | 2001-11-14 | 日本板硝子株式会社 | Circuit for driving self-scanned luminescent array |
| CN1354454A (en) * | 2000-11-22 | 2002-06-19 | 株式会社日立制作所 | Display device with improved voltage-level converter circuit |
| CN1794334A (en) * | 2004-12-21 | 2006-06-28 | 株式会社瑞萨科技 | Semiconductor integrated circuit for liquid crystal display driver |
| JP2008191375A (en) * | 2007-02-05 | 2008-08-21 | Sharp Corp | Display device, and driving circuit and driving method thereof |
| CN101312012A (en) * | 2007-05-21 | 2008-11-26 | 索尼株式会社 | Display device, driving method thereof, and electronic device |
-
2009
- 2009-01-06 CN CN 200910001704 patent/CN101770737B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1322169A (en) * | 1999-10-22 | 2001-11-14 | 日本板硝子株式会社 | Circuit for driving self-scanned luminescent array |
| CN1354454A (en) * | 2000-11-22 | 2002-06-19 | 株式会社日立制作所 | Display device with improved voltage-level converter circuit |
| CN1794334A (en) * | 2004-12-21 | 2006-06-28 | 株式会社瑞萨科技 | Semiconductor integrated circuit for liquid crystal display driver |
| JP2008191375A (en) * | 2007-02-05 | 2008-08-21 | Sharp Corp | Display device, and driving circuit and driving method thereof |
| CN101312012A (en) * | 2007-05-21 | 2008-11-26 | 索尼株式会社 | Display device, driving method thereof, and electronic device |
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|---|---|
| CN101770737B (en) | 2013-09-11 |
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Address after: Miaoli County, Taiwan, China Applicant after: INNOLUX DISPLAY CORP. Address before: Miaoli County, Taiwan, China Applicant before: CHI MEI OPTOELECTRONICS CORP. Address after: Miaoli County, Taiwan, China Applicant after: CHI MEI OPTOELECTRONICS CORP. Address before: Miaoli County, Taiwan, China Applicant before: TOPPOLY OPTOELECTRONICS Corp. |
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Free format text: CORRECT: APPLICANT; FROM: QIMEI ELECTRONIC CO LTD TO: INNOLUX DISPLAY CORPORATION Free format text: CORRECT: APPLICANT; FROM: TONGBAO OPTOELECTRONICS CO., LTD. TO: QIMEI ELECTRONIC CO LTD |
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