CN101740404A - 一种半导体封装件的结构以及其制法 - Google Patents
一种半导体封装件的结构以及其制法 Download PDFInfo
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Abstract
一种半导体封装件的结构以及其制法,提供一具有相对的第一表面和第二表面的具有开口的强化件;接置于该强化件的第一表面的多个导脚;以及接置于该强化件的第二表面的具有相对的上表面和下表面的基板;接置于该开口所外露的部分基板的芯片;接着以焊线方式电性连接该芯片至该基板与该导脚;然后,再进行封装模压作业,以形成一个封装胶体包覆该基板、芯片、强化件与导脚,且该封装胶体与该基板的下表面齐平的封装件。通过该强化件的设置,该封装件的整体强度会相应地增加,且由于基板的下表面的外露,可以设置多个导电元件以提升该封装件的电性输出/输入点。
Description
技术领域
本发明涉及一种半导体封装件结构以及其制法,特别是涉及一种能增加电性输出/输入端且能避免变形现象的半导体封装件结构以及其制法。
背景技术
请参阅图1a所示,传统的导线架式半导体封装件,四方扁平式半导体封装件(Quad Flat Package,QFP),其制作方式是提供一具有芯片垫2(Die Pad)及多个导脚31(Lead)的导线架3,以在该芯片垫2上黏置一芯片1,再通过多条焊线4(Wire)电性连接该芯片1上表面的焊垫(Pad)与其对应的多个导脚31,并以一封装胶体5包覆该芯片1及焊线4而形成一导线架型式半导体封装件。
此种传统的导线架式半导体封装件的缺陷是作为电性输入/输出端(I/O)的导脚仅能排列于封装胶体的周边,所以它所具有的I/O将受制于封装胶体的大小,而无法满足业界电子产品多I/O的需求。为解决上述的问题遂有球栅阵列式(BGA)半导体封装件的产生。
参图1b所示,如美国专利第5,508,556号,该发明也提供了一种传统的球栅阵列式(BGA)半导体封装件,其中,该芯片12是粘置于该接地线路层13的上方,但由于该基底14为单层的绝缘层,且导电通孔15沿着该线路层13的垂直方向延伸以电性连接该线路层13以及该输出垫16,因此,该导电元件17仅能形成于该线路层13的下方,故该导电元件17的线路布置以及数量也因此受到限制,进而影响到该半导体封装件的功效。
另请参阅图1c所示,如美国专利第5,854,512号,传统的球栅阵列式(BGA)半导体封装件的制法是使用一上、下表面设有线路层7的绝缘层6作为基板(substrate),以在该基板的上表面上粘置一芯片垫9及接置于该芯片垫9上一芯片8,再通过焊线10电性连该芯片8上表面的焊垫(Pad)与该基板上表面的线路层7,还通过基板内部的导电通孔而电性连接至基板下表面的线路,还在形成于该基板下表面线路层7的线路终端的焊球垫(ball pad)上植设锡球11,以供芯片8电性连接至外部装置,从而利用整个基板的面积的I/O安排从而得到更多I/O;然而,当该半导体封装件的基板面积太大时,在后续的焊线或者遇有热度的加工时会导致基板的变形,影响打线时的品质和良率。
综上所述,如何解决传统的导线架具有较少的输出和输入连接端的问题,并能使半导体封装件的输出和输入连接端的布线不受到限制,而且还可以避免该基板因为变形而造成较低的打线品质和良率,实为此产业急需解决的问题。
发明内容
鉴于上述现有技术的种种缺陷,本发明的目的是提供一种半导体封装件结构以及其制法,进而解决传统的导线架具有较少的输出和输入连接端的缺陷。
本发明的又一目的是提供一种半导体封装件的结构以及其制法,从而使半导体封装件的输出和输入连接端的布线不受到限制。
本发明的又一目的是提供一种半导体封装件的结构以及其制法,从而能避免该基板因为变形而造成较低的打线品质和良率。
为达到上述目的及其他目的,本发明的半导体封装件结构制法,包括:提供一具有相对的第一表面和第二表面的强化件,而且该强化件具有一开口;然后在该强化件的第一表面上接置多个导脚,以及在该强化件的第二表面接置一具有相对的上表面和下表面的基板;通过上述的步骤形成一由导脚、强化件以及基板所组成的结构体;接着将芯片接置于该强化件的开口所露出来的部分基板,并且以焊线的方式电性连接该芯片至该导脚以及基板;之后,进行封装模压作业,以使封装胶体包覆该基板、芯片、强化件、焊线与导脚,而且该封装胶体形成与该基板的下表面齐平,用以外露该基板的下表面并设置多个导电元件于该下表面上。
在上述半导体封装件结构的制法中,该封装压模作业是以一具有上、下模的模具进行,且该下模的模腔深度小于该强化件与该基板粘置之后的厚度,用以避免模压作业时封装胶体溢流至该基板的下表面,进而影响导电元件的设置。
在上述半导体封装件结构的制法中,由于利用该强化件接置该导脚以及该基板,因此,可以在基板的面积较大时强化基板的结构强度,避免基板产生变形的现象,进而增进打线时的品质与良率,以及避免模压作业时封装胶体溢流至该基板的下表面。
同时,由于上述的本发明的半导体封装件制法,采用在上下表面具有多线路层的多层基板,因此,该基板并非单层的绝缘层,且非以单一的导电通孔贯穿,也就是说,设置于基板下表面的导电元件并非一定需要位于相对焊线的线路层的下方,因而该导电元件的布置并不会受到限制。
本发明还提供一种半导体封装件结构,包括:基板,具有一相对的上表面及下表面;强化件,接置于该基板的上表面并具有开口,且该开口露出部分该基板作为置晶区;多个导脚,接置于该强化件上;芯片,接置于该基板的置晶区上;焊线,电性连接该芯片至该导脚与该基板;封装胶体,形成于该基板、芯片、强化件、焊线与导脚之间,并切齐于该基板的下表面,用以包覆该基板、芯片、强化件与导脚并露出该基板的下表面。
因此,通过上述的本发明的半导体封装件结构,可以提供一个比传统导线架更多的电性输出/输入端,且由于该基板为上下表面具有多线路层的多层基板,因此该电性输出/输入端的布置并不会受到限制。
附图说明
图1a为传统的导线架结构示意图;
图1b、1c为传统的球栅阵列式(BGA)半导体封装件结构示意图;
图2a至2e为本发明的半导体封装件制法的实施例的剖面示意图及立体图;
图2a’是显示本发明的强化件的立体图;
图2b’是显示本发明的基板、导脚和强化件结构立体图。
主要元件符号说明:
1、8、12、23芯片
2、9芯片垫
3导线架
4、10、24焊线
5、26封装胶体
6、21c绝缘层;介电层
7、13、21a线路层
11、17、27导电元件;锡球
14基底
15、21b导电通孔
16输出垫
20强化件
201第一表面
202第二表面
21基板
21d核心板
211上表面
212下表面
2110置晶区
22、31导脚
25模具
251上模
252下模
a1、b1距离
具体实施方式
以下通过特定的具体实例说明本发明的实施方式,本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点与功效。
请参阅图2a至图2e,为本发明的半导体封装件制法的实施例的剖面示意图及立体图。
如图2a以及图2a’所示,首先,提供一强化件20,该强化件20是以金属或非金属硬质材料制成,且该强化件20具有开口以及一相对的第一表面201以及第二表面202。
如图2b所示,接着,在该强化件20的第一表面201上接置多个导脚22,且该导脚22大致接置于齐平该强化件20开口的位置。
接着,再将该强化件20以及该导脚22的结构体,于该强化件20的第二表面202上接置一具有相对的上表面211、下表面212的基板21,该基板21通过接置该强化件20于该上表面211上,可避免基板21变形而得以在后续的焊线制造工艺时避免焊线品质不良及良率低的缺陷。
其中,该基板21为多个介电层21c以及核心板21d所组成的多层板,且该上表面211以及下表面212形成有线路层21a,在该核心板21d中,具有导电通孔21b以电性连接该基板21的上下表面的线路层21a。
如图2b’所示,上述的该导脚22及强化件20是以环氧树脂、聚亚酰胺等高分子材料接置,或者,该强化件20与基板21之间是以环氧树脂或聚亚酰胺等高分子材料接置,且该强化件20的开口外露部分该基板21的上表面211,作为后续置放芯片时用的置晶区2110。
如图2c所示,待该导脚22、强化件20以及基板21接置为一结构体后,再将芯片23接置于该基板21的上表面211的置晶区2110,其中,该芯片23的主动面朝上,接着,再以焊线24制造工艺(wire bonding)的方式将该芯片23电性连接至该导脚22以及该基板21,而该焊线24制造工艺与现有技术相同,故不在此赘述。
如图2d所示,然后,进行封装模压的作业,将含有芯片23、导脚22、强化件20、焊线24以及基板21的结构体置入一由上、下模251、252组成的模具25中,以进行模压作业,用以形成一包覆该芯片23、导脚22、强化件20、焊线24以及基板21的结构体的封装胶体,其中,该强化件20的第一表面201至该基板21的下表面212的厚度为距离b1,而该下模252的模腔深度为距离a1,通过该距离b1的高度会高于该距离a1以避免模压时,胶体会溢流至该基板21的下表面212,进而影响到导电元件的设置以及该半导体封装件的电性输出。
如图2e所示,在完成封装模压工艺之后,该半导体封装件的底面露出该基板21的下表面212,接着在该基板21的下表面212的线路层21a上设置例如为锡球的导电元件27,即可形成本发明的半导体封装件。
请参阅图2e,为前述的半导体封装件制法所制成的半导体封装结构,包括:基板21,具有一相对的上表面211及下表面212;强化件20,接置于该基板21的上表面211并具有开口,通过该开口露出部分该基板21作为芯片置入时放置的置晶区2110;多个导脚22,接置于该强化件20上,位置大致齐平于该强化件20的开口;芯片23,接置于该基板21的置晶区2110上,且该芯片23的主动面朝上;焊线24,电性连接该芯片23至该导脚22以及该基板21;封装胶体26,形成于该基板21、芯片23、强化件20与导脚22之间,并切齐于该基板21的下表面212,用以包覆该基板21、芯片23、强化件20与导脚22并且露出该基板21的下表面212;导电元件27,形成于该基板21的下表面212的线路层21a上,用以电性输出或输入外部装置至该芯片23。
前述的半导体封装件通过在该导脚和基板之间设置强化件,以增加基板的强度,降低基板变形的机会,进而增加导脚和基板的焊线的品质和良率,同时,也可避免在模压工艺时,溢胶至该基板的下表面的机会。
上述实施例仅例示性说明本发明的原理及其功效,而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下,对上述实施例进行修饰与改变。因此,本发明的权利保护范围,应以权利要求书的范围为依据。
Claims (10)
1.一种半导体封装件的制法,其特征在于,包括:
提供一具有相对的第一表面和第二表面的强化件,且该强化件具有一开口;
在该强化件的第一表面上接置多个导脚,并将一具有相对的上表面和下表面的基板通过其上表面结合至该强化件的第二表面上,且该开口露出部分该基板的上表面作为置晶区;
将芯片接置于该置晶区,并以焊线方式电性连接该芯片至该基板与该导脚;
进行封装模压作业,以使封装胶体包覆该基板、芯片、强化件与导脚,且该封装胶体与该基板的下表面齐平,用以外露该下表面并设置多个导电元件于该下表面上。
2.根据权利要求1所述的半导体封装件的制法,其特征在于:该封装模压作业通过一具有上、下模的模具进行,且该下模的模腔深度小于该第一表面至该下表面的距离,用以避免封装胶体溢流至该下表面。
3.根据权利要求1所述的半导体封装件的制法,其特征在于:该导电元件为锡球。
4.根据权利要求1所述的半导体封装件的制法,其特征在于:该导脚与该强化件是以环氧树脂或聚亚酰胺的其中之一者粘合。
5.根据权利要求1所述的半导体封装件的制法,其特征在于:该强化件与该基板的上表面是以环氧树脂或聚亚酰胺的其中之一者粘合。
6.一种半导体封装结构,其特征在于,包括:
基板,具有一相对的上表面及下表面;
强化件,接置于该基板的上表面并具有开口,且该开口露出部分该基板作为置晶区;
多个导脚,接置于该强化件上;
芯片,接置于该基板的置晶区上;
焊线,电性连接该芯片至该导脚与该基板;
封装胶体,形成于该基板、芯片、强化件与导脚之间,并切齐于该基板的下表面,用以包覆该基板、芯片、强化件、焊线与导脚并露出该基板的下表面。
7.根据权利要求6所述的半导体封装结构,其特征在于:该基板的下表面上设置有多个导电元件,藉以供该芯片与外界装置形成电性连接关系。
8.根据权利要求8所述的半导体装结构,其特征在于:该导电元件为锡球。
9.根据权利要求6所述的半导体封装结构,其特征在于:该导脚与该强化件是以环氧树脂或聚亚酰胺的其中之一者粘合。
10.根据权利要求6所述的半导体封装结构,其特征在于:该强化件与该基板的上表面是以环氧树脂或聚亚酰胺的其中之一者粘合。
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